CN114220778A - Chip packaging structure and method - Google Patents

Chip packaging structure and method Download PDF

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Publication number
CN114220778A
CN114220778A CN202111535118.0A CN202111535118A CN114220778A CN 114220778 A CN114220778 A CN 114220778A CN 202111535118 A CN202111535118 A CN 202111535118A CN 114220778 A CN114220778 A CN 114220778A
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CN
China
Prior art keywords
chip
film layer
heat dissipation
metal
heat
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CN202111535118.0A
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Chinese (zh)
Inventor
王栋
严杰
吴定益
冯建超
付焰峰
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Wuhan Optical Valley Information Optoelectronic Innovation Center Co Ltd
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Wuhan Optical Valley Information Optoelectronic Innovation Center Co Ltd
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Priority to CN202111535118.0A priority Critical patent/CN114220778A/en
Publication of CN114220778A publication Critical patent/CN114220778A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/06—Containers; Seals characterised by the material of the container or its electrical properties
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate

Abstract

The embodiment of the disclosure provides a chip packaging structure and a chip packaging method. The chip packaging structure comprises: the packaging structure comprises a packaging carrier plate, a heat dissipation structure layer, a metal connecting structure and a metal sealing cover which are arranged in a stacked mode, wherein a groove is formed in the surface, close to the metal sealing cover, of the packaging carrier plate; the heat radiation structure layer comprises: the heat dissipation film layer and the chip are sequentially stacked on the bottom surface of the groove, wherein the coverage area of the heat dissipation film layer on the bottom surface of the groove is larger than the area of the bottom surface of the chip; the metal sealing cover is fixed on the packaging carrier plate, and the packaging carrier plate and the metal sealing cover are connected in a sealing manner to form a sealed cavity; the metal connecting structure is fixed in the sealed cavity, a first surface of the metal connecting structure is in contact with the metal sealing cover, a second surface of the metal connecting structure is in contact with a surface of the heat dissipation film layer, which is relatively close to the metal connecting structure, and the first surface and the second surface are opposite.

Description

Chip packaging structure and method
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a chip package structure and a method thereof.
Background
The high-frequency chip is a microwave circuit chip, and microwave and millimeter-wave active elements and passive elements can be manufactured on the same semiconductor substrate, and the operating frequency can be from 1GHz to far more than 100 GHz. The high-frequency chip is widely applied to scenes such as civil communication instruments, weaponry and the like. With the development trend of miniaturization, multifunction and high integration of various devices, the integration of high-frequency chips is higher and higher, and monolithic integration of a plurality of functional elements on the same chip becomes a development trend. The power consumption of the chip is higher and higher. Therefore, when the chip is packaged, there is a problem that heat dissipation is difficult.
Disclosure of Invention
According to a first aspect of the embodiments of the present disclosure, there is provided a chip packaging structure, including:
the packaging structure comprises a packaging carrier plate, a heat dissipation structure layer, a metal connecting structure and a metal sealing cover which are arranged in a stacked mode, wherein a groove is formed in the surface, close to the metal sealing cover, of the packaging carrier plate;
the heat radiation structure layer comprises: the heat dissipation film layer and the chip are sequentially stacked on the bottom surface of the groove, wherein the coverage area of the heat dissipation film layer on the bottom surface of the groove is larger than the area of the bottom surface of the chip;
the metal sealing cover is fixed on the packaging carrier plate, and the packaging carrier plate and the metal sealing cover are connected in a sealing manner to form a sealed cavity;
the metal connecting structure is fixed in the sealed cavity, a first surface of the metal connecting structure is in contact with the metal sealing cover, a second surface of the metal connecting structure is in contact with a surface of the heat dissipation film layer, which is relatively close to the metal connecting structure, and the first surface and the second surface are opposite.
In some embodiments, the heat dissipation structure layer further includes: a heat conductive film layer; wherein the content of the first and second substances,
the first surface of the heat conducting film layer is in contact with the surface of the heat dissipation film layer relatively close to the metal connecting structure, and the second surface of the heat conducting film layer is in contact with the second surface of the metal connecting structure;
and on the surface of the heat dissipation film layer relatively close to the metal connecting structure, the position of the heat conduction film layer is different from that of the chip.
In some embodiments of the present invention, the,
the chip packaging structure further comprises: a bonding structure;
a conductive medium is arranged in the packaging carrier plate;
wherein the chip and the conductive medium are electrically connected through the bonding structure.
In some embodiments, the chip package structure further comprises:
and the conductive structure is positioned on the surface of the package carrier plate relatively far away from the metal sealing cover, is electrically connected with the chip through the conductive medium and the bonding structure, and is configured to realize the signal input and output of the chip packaging structure.
In some embodiments, the heat spreading film layer comprises:
a graphene film layer;
and/or the presence of a gas in the gas,
a metal film layer.
In some embodiments, the chip comprises a high frequency front-mounted chip.
In some embodiments, the metal connecting structure and the metal cover are a unitary structure.
According to a second aspect of the embodiments of the present disclosure, there is provided a chip packaging method, including:
providing a packaging carrier plate, and forming a groove on the surface of the packaging carrier plate;
forming a heat dissipation film layer covering the bottom surface of the groove;
bonding a chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove; the covering area of the heat dissipation film layer on the bottom surface of the groove is larger than the area of the bottom surface of the chip;
forming a metal connecting structure in contact with the heat dissipation film layer on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove; the position of the metal connecting structure is different from that of the chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove;
fixedly connecting a metal sealing cover and the packaging carrier plate to enable the packaging carrier plate and the metal sealing cover to be connected in a sealing mode to form a sealed cavity; and the surface of the metal connecting structure relatively far away from the heat dissipation film layer is contacted with the metal sealing cover.
In some embodiments, the method further comprises:
forming a heat conducting film layer on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove, wherein the position of the heat conducting film layer is different from that of the chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove;
and after the heat conduction film layer is formed, forming the metal connecting structure on the surface of the heat conduction film layer relatively far away from the heat dissipation film layer.
In some embodiments, after the attaching the chip to the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove, the method further includes:
and forming a bonding structure between the chip and the packaging carrier plate, wherein a conductive medium is arranged in the packaging carrier plate, and the chip is electrically connected with the conductive medium through the bonding structure.
The chip packaging structure provided by the embodiment of the disclosure conducts heat generated by the chip to the metal connecting structure through the heat dissipation film layer contacted with the bottom of the chip, and transmits the heat of the chip out through the metal connecting structure and the metal sealing cover, so that efficient heat dissipation of the chip is realized. In addition, because the upper surface of the chip is not provided with additional metal conductors or other objects which are in direct contact with the upper surface of the chip, the additional metal conductors or other objects cannot be in direct contact with or have a very short distance from conductors in a signal link of the upper surface of the chip, gold wire bonding wires and the like, the problems of crosstalk, resonance, antenna effect and the like of chip signals during transmission are reduced, the signal transmission performance of the chip cannot be influenced, and the normal operation of the chip is ensured. In addition, compared with the case that the chip is placed on the surface of the package carrier, the chip is placed in the groove of the package carrier in the embodiment of the disclosure, which can effectively shorten the connection length between the chip and the surface of the package carrier, facilitate the subsequent electrical connection between the chip and the package carrier, reduce the performance loss of the chip in the signal transmission process, and thus improve the signal transmission capability between the chip and the package carrier.
Drawings
Fig. 1 is a schematic cross-sectional view illustrating a chip package structure according to an embodiment of the disclosure;
fig. 2 is a schematic cross-sectional view illustrating a chip package structure according to another embodiment of the disclosure;
fig. 3 is a schematic cross-sectional view illustrating a chip package structure according to another embodiment of the disclosure;
fig. 4 is a schematic cross-sectional view illustrating a chip package structure according to still another embodiment of the disclosure;
fig. 5 is a schematic flow chart of a chip packaging method according to an embodiment of the disclosure.
Description of the reference numerals
10-a package carrier; 20-a heat dissipation structure layer; 30-metal connection structure; 40-metal cover; a 50-bonded structure; 60-a conductive structure; 70-sealant or solder; 21-a heat dissipation film layer; 22-a chip; 23-heat conducting film layer.
Detailed Description
In order to make the technical solutions and advantages of the embodiments of the present disclosure clearer, the following describes the technical solutions of the present disclosure in further detail with reference to the drawings and specific embodiments of the specification.
The term "epitaxy" as used herein refers to the step of growing a semiconductor layer on a substrate.
In the embodiments of the present disclosure, the terms "first", "second", and the like are used for distinguishing similar objects, and are not used for describing a particular order or sequence.
In the embodiments of the present disclosure, unless otherwise explicitly specified or limited, an "upper" or "lower" relationship between two layers in a semiconductor structure may be a direct contact between the two layers, or an indirect contact between the two layers through an intermediate layer.
In embodiments of the present disclosure, the term "layer" refers to a portion of material that includes a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure or may have an extent that is less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal pair of surfaces at the top and bottom surfaces of a continuous structure. The layers may extend horizontally, vertically and/or along inclined surfaces. Also, a layer may include multiple sublayers.
When packaging a front-mounted high-frequency chip, heat dissipation is difficult. For the heat dissipation problem of the packaging of the normally-installed high-frequency chip, the traditional solution is to place a metal conductor directly above the chip to dissipate the heat. However, for high frequency chips, especially gallium arsenide, gallium nitride and the like, the surface layer thereof may be designed with high frequency signal interconnection links. The metal conductor used for heat dissipation in the packaging structure is directly contacted with or is very close to a conductor in a signal link on the upper surface of the chip and a gold wire bonding wire, so that the problems of crosstalk, resonance, antenna effect and the like of high-frequency signals during transmission occur, and the signal transmission performance of the high-frequency chip is seriously influenced.
In addition, heat conduction holes or heat conduction metal blocks can be designed in the package carrier. The heat generated by the chip can be dissipated through the heat conduction holes or the heat conduction metal blocks in the package carrier. However, this heat dissipation method also needs to directly contact the bottom of the package device with the circuit board to achieve a better heat dissipation effect. The bottom of the packaging device may have input and output pins, most area of the bottom is used for signal transmission, and the area for heat dissipation is greatly reduced, so that the thermal resistance between the packaging device and the circuit board is increased, and the heat dissipation capability of the heat dissipation mode is limited. The chip package structure of the present disclosure will be described in detail below with reference to the accompanying drawings.
The embodiment of the disclosure provides a chip packaging structure, and fig. 1 is a schematic cross-sectional view of the chip packaging structure provided by the embodiment of the disclosure. As shown in fig. 1, the chip package structure includes:
the package carrier 10, the heat dissipation structure layer 20, the metal connection structure 30 and the metal cap 40 are stacked, wherein a groove is formed on a surface of the package carrier 10 relatively close to the metal cap 40;
the heat dissipation structure layer 20 includes: the heat dissipation film layer 21 and the chip 22 are sequentially stacked on the bottom surface of the groove, wherein the coverage area of the heat dissipation film layer 21 on the bottom surface of the groove is larger than that of the chip 22;
the metal sealing cover 40 is fixed on the package carrier 10, and the package carrier 10 and the metal sealing cover 40 are hermetically connected to form a sealed cavity;
the metal connecting structure 30 is fixed in the sealed cavity, a first surface of the metal connecting structure 30 is in contact with the metal sealing cover 40, a second surface of the metal connecting structure 30 is in contact with the surface of the heat dissipation film layer 21 relatively close to the metal connecting structure 30, and the first surface and the second surface are opposite.
In some embodiments, the material of the package carrier 10 may be an insulating material such as a ceramic board or an organic board.
A heat dissipation film layer 21 and a chip 22 sequentially stacked on the bottom surface of the groove are disposed in the groove on the surface of the package carrier 10. Referring to fig. 1, the package carrier 10 includes a surface and a recess recessed from the surface for accommodating the chip 22, wherein the recess has a side surface, and the chip 22 has an upper surface a1 and a side surface b 1. For the mode of bonding the bottom surface of the chip 22 on the planar surface of the package carrier 10, the chip 22 can be fixed in the groove in the embodiment, and the chip 22 is not easy to slide out in the transmission process by bonding two or three side surfaces of the chip 22 with the side surfaces of the groove, so that the assembly and assembly requirements of the chip are met, and a plastic package adhesive layer for fixing the chip does not need to be arranged above the chip 22, thereby simplifying the packaging process and saving the cost.
In some embodiments, there may be a height difference between the surface a2 of the package carrier 10 and the upper surface a1 of the chip 22 or the surface a2 of the package carrier 10 is flush with the upper surface a1 of the chip 22. The height difference between the package carrier 10 and the chip 22 may be that the surface a2 of the package carrier 10 is higher or lower than the upper surface a1 of the chip 22.
Referring to fig. 1, in the embodiment, preferably, the chip 22 is placed in the groove of the package carrier 10, and the surface a2 of the package carrier 10 is flush with the upper surface a1 of the chip 22, so that the connection length between the chip 22 and the surface a2 of the package carrier 10 can be effectively shortened, the subsequent electrical connection between the chip 22 and the package carrier 10 can be conveniently realized, the performance loss of the chip 22 in the signal transmission process can be effectively reduced, and the signal transmission capability between the chip 22 and the package carrier 10 can be improved.
In addition, the side distance between the side surface of the groove of the package carrier 10 and the side surface b1 of the chip 22 may be set according to the connection length between the chip 22 and the package carrier 10.
Here, the package carrier 10 has a recess on its surface. However, the number of the grooves is not limited to this, and in practical applications, the number of the grooves can be set according to the specific number and the specific size of the packaged chips. The depth of the recess may be designed according to the thickness of the carrier of the package carrier 10 and the thickness of the chip 22.
In order to protect the chip 22, the chip package structure further includes a metal cap 40, and referring to fig. 1, the metal cap 40 is fixed on the package carrier 10. To achieve better sealing effect, a better sealing property is formed at the joint of the metal cap 40 and the package carrier 10 by using a sealant or solder 70. The hermetic or quasi-hermetic package inside the chip package structure can be realized by sealing with the sealant or solder 70, so as to effectively protect the chip 22.
The present embodiment is illustrated that the chip package structure may include two chips 22. However, the number and arrangement of the chips 22 are not limited to this, and may be set according to specific situations in practical applications, and the number of the chips 22 may be 1, 2 or more.
Referring to fig. 1, the bottom surface of the groove of the package carrier 10 is covered with a heat dissipation film 21. In order to better conduct the heat generated by the chip away, the coverage area of the heat dissipation film 21 on the bottom surface of the groove needs to be larger than the area of the bottom surface of the chip 22. I.e. the periphery of the chip 22 is covered with the heat dissipation film layer 21 except for the area where the chip 22 is located. The heat dissipation film layer 21 has excellent heat diffusion and heat radiation performance, so that high-density heat generated by the chip 22 can be timely expanded to the surface of the whole heat dissipation film layer 21 and then output, and the overall heat dissipation capacity of the chip packaging structure is greatly improved.
On the surface of the heat dissipation film layer 21 relatively far away from the bottom surface of the groove, the position of the metal connection structure 30 is different from that of the chip 22, that is, the chip 22 is in contact with a first area of the upper surface of the heat dissipation film layer, and the metal connection structure is in contact with a second area of the upper surface of the heat dissipation film layer 21, wherein the first area is different from the second area. The heat generated by the chip can be conducted to the metal connecting structure 30 contacted with the other end of the heat dissipation film layer 21 through the heat dissipation film layer 21 contacted with the bottom of the chip 22, and the heat of the chip 22 is transmitted out through the metal connecting structure 30 and the metal sealing cover 40, so that the efficient heat dissipation of the chip is realized.
Because no additional metal conductor or plastic package adhesive layer or other objects exist on the upper surface of the chip 22, the chip 22 cannot be in direct contact with or very close to a conductor in a signal link on the upper surface of the chip 22, a gold wire bonding wire or the like, the problems of crosstalk, resonance, antenna effect and the like of a chip 22 signal during transmission are reduced, the signal transmission performance of the chip cannot be influenced, and the normal operation of the chip is ensured.
The chip packaging structure provided by the embodiment of the disclosure realizes efficient heat dissipation on the premise of not influencing the signal transmission performance of the chip.
Referring to fig. 2, the heat dissipation structure layer 20 further includes: a heat conductive film layer 23; wherein the content of the first and second substances,
the first surface of the heat conducting film layer 23 is in contact with the surface of the heat dissipation film layer 21 relatively close to the metal connecting structure 30, and the second surface of the heat conducting film layer 23 is in contact with the second surface of the metal connecting structure 30;
wherein, on the surface of the heat dissipation film layer 21 relatively close to the metal connection structure 30, the position of the heat conduction film layer 23 is different from the position of the chip 22.
Referring to fig. 2, a heat conductive film layer 23 is disposed between the heat dissipation film layer 21 and the metal connection structure 30. After the heat generated by the chip is conducted to the heat conducting film layer 23 by the heat dissipating film layer 21, the heat of the chip 22 is transmitted out through the metal connecting structure 30 and the metal sealing cover 40.
Illustratively, a heat conductive film layer 23 is positioned between the heat dissipation film layer 21 and the metal connection structure 30 for heat conduction between the heat dissipation film layer 21 and the metal connection structure 30. The thermal conductivity of the thermal conductive film layer 23 is relatively high.
In some embodiments, the heat conductive film layer 23 can deform under the action of external force. Specifically, in the process of preparing the chip package structure, the heat conductive film layer 23 covering the heat dissipation film layer 21 may be formed, and then the metal connection structure 30 is placed on the heat conductive film layer 23. It should be emphasized that the metal connection structure 30 may apply a certain pressure to the heat conducting film layer 23, and the heat conducting film layer 23 with a certain flexibility deforms under the action of the pressure, so that the heat conducting film layer 23 is not only located between the metal connection structure 30 and the heat dissipation film layer 21, but also at least part of the constituent materials of the heat conducting film layer 23 extend to at least part of the side surface wrapping the metal connection structure 30, so as to increase the contact area between the heat conducting film layer 23 and the metal connection structure 30, which is beneficial to increase the heat conducting effect.
The material of the heat conductive film layer 23 may include heat conductive silicone, vulcanized rubber, or metal (gold, silver, copper, etc.). However, the material of the heat conducting film layer 23 is not limited to this, and may be set according to specific situations in practical applications.
Here, the Material of the heat conductive film layer 23 is preferably a Thermal Interface Material (TIM). The TIM may be a silicone gel. TIMs have some flexibility and higher thermal conductivity.
Because TIM has certain flexibility, can produce deformation, and has good adhesion to metal and non-metal materials. When the TIM is in contact with the heat dissipation film layer 21 and the metal connection structure 30, the shape of the TIM itself can be adjusted according to the shape of the contact surface, so that the heat dissipation film layer 21 can be in close contact with the metal connection structure 30, and the thermal contact resistance generated between the heat dissipation film layer 21 and the metal connection structure 30 is reduced. The thermal conductivity of the heat generated by the chip after passing through the heat conducting film layer 23 is higher than that of the heat conducting film layer without the heat conducting film layer 23.
The material of the heat conducting film layer is not limited to this, and may be set according to the specific situation in the practical application.
The embodiment of the present disclosure adds the heat conducting film layer 23, and compared with the direct contact between the heat dissipating film layer 21 and the metal connecting structure 30, the addition of the heat conducting film layer 23 can improve the contact stability between the heat dissipating film layer 21 and the metal connecting structure 30, and reduce the thermal contact resistance generated between the two. Moreover, the heat conducting film layer 23 also has high heat conductivity, which can significantly improve the heat conductivity of the heat generated by the chip on the heat dissipation path.
In some embodiments, referring to fig. 1 or 2, the chip packaging structure further includes: a bonding structure 50;
a conductive medium is arranged inside the package carrier 10;
wherein the chip 22 and the conductive medium are electrically connected through the bonding structure 50.
In practical applications, the bonding structure 50 may include a bonding wire, and the material of the bonding wire may be one or more of silver, gold, aluminum, copper, chromium, nickel, or an alloy thereof. The bonding wire can be manufactured by adopting the processes of evaporation, electroplating, metal wire ball planting and the like.
Specifically, the bonding wires may include gold bonding wires, and the electrical connection between the chip 22 and the conductive medium in the package carrier 10 is completed by using the gold bonding wires.
Here, the bonding wire may take the form of a single, double, or multiple pieces. The bonding wire can realize smaller integrated inductance and improve the packaging performance.
In some embodiments, the chip 22 is placed in the groove of the package carrier 10, and the surface a2 of the package carrier 10 is flush with the upper surface a1 of the chip 22, so that the connection length of the bonding wire between the chip 22 and the surface a2 of the package carrier 10 can be effectively shortened, the parasitic inductance of the bonding wire is reduced, the signal transmission capability between the chip 22 and the package carrier 10 is improved, and the radio frequency performance of the chip 22 is ensured.
In addition, to realize the electrical connection between the chip 22 and the conductive medium in the package carrier 10, an optional implementation manner further includes: interconnection pads (not shown) are disposed between the groove side of the package carrier 10 and the side surface b1 of the chip 22, wherein one example of the interconnection pads may be Ball Grid Array (BGA) bumps. The side surface b1 of the chip 22 is soldered to the corresponding ball grid array bump on the side surface of the groove of the package carrier 10, so as to electrically connect the chip 22 and the conductive medium in the package carrier 10. The method has higher integration level, but has certain requirements on the area of the side surface of the groove of the package carrier 10, and if the area of the side surface of the groove of the package carrier 10 is relatively small, the manufacturing process complexity is higher.
The manner of electrically connecting the chip 22 and the conductive medium in the package carrier 10 is not limited to this, and may be set according to specific situations in practical applications.
In the embodiment of the disclosure, the bonding structure 50 is used to electrically connect the chip 22 and the conductive medium in the package carrier 10, so as to facilitate signal transmission of the chip 22. And the mode of arranging the bonding wire for electric connection is simple in process and low in cost.
In some embodiments, referring to fig. 3 or 4, the chip packaging structure further includes:
the conductive structure 60, located on the surface of the package carrier 10 relatively far away from the metal cap 40, is electrically connected to the chip 22 through the conductive medium and the bonding structure 50, and is configured to implement signal input and output of the chip package structure.
Here, the package carrier 10 may be stacked by multiple ceramic substrates. Each layer of ceramic substrate inside the package carrier 10 may be provided with a conductive medium according to actual needs.
In the specific implementation process, the fewer the turning or connecting nodes in the electric connection, the better the electric connection characteristic is. Therefore, the smaller the number of layers of the ceramic substrate constituting the package carrier 10, the better the electrical connection characteristics.
The conductive structure 60 in the embodiment of the present disclosure may include a ball grid array BGA structure, which is electrically connected to the chip 22 through the ball grid array structure, the conductive medium, and the bonding structure 50, so as to implement signal input and output of the chip package structure.
In some embodiments, the heat dissipation film layer 21 includes:
a graphene film layer;
and/or the presence of a gas in the gas,
a metal film layer.
In practical applications, the heat dissipation film layer 21 may have a single-layer structure or a multi-layer structure. The heat dissipation film layer 21 may be one or more of a graphene film layer, a metal film layer, a carbon nanotube layer, or a combination thereof.
In some embodiments, the thinner the heat spreading material thickness, the lower the thermal resistance. In consideration of the thickness of the package carrier 10 and the thickness of the chip 22, the heat dissipation film layer 21 is preferably a single-layer structure.
The metal film layer may be made of gold, silver, copper, etc. and has a thermal conductivity of about 300-420W/m.k. The thermal conductivity of carbon nanotubes is about 1750W/m.K. The thermal conductivity of the graphene is more than 4000W/m.K. The higher the thermal conductivity, the better the thermal conductivity, and the preferable material of the heat dissipation film layer 21 is graphene.
In some embodiments, since the graphene surface has a certain adhesiveness, when the heat dissipation film layer 21 covering the bottom surface of the groove is formed, there is no need to provide an adhesive layer between the groove and the heat dissipation film layer 21, and the heat dissipation film layer 21 made of graphene material can be adhered to the bottom surface of the groove by surface adhesiveness. Moreover, the surface of the heat dissipation film layer 21 relatively far away from the bottom surface of the groove can be bonded with the chip 22 through graphene surface adhesion, and an adhesive layer does not need to be arranged between the heat dissipation film layer 21 and the chip 22. Compared with the case that the heat dissipation film layer 21 is made of metal or carbon nano tubes, bonding layers such as conductive silver adhesive and the like need to be arranged, the heat dissipation film layer 21 is made of graphene, so that the packaging process can be simplified, and the cost is saved.
Here, the heat dissipation film layer 21 may also be made of other heat conductive materials with adhesive surfaces, which are not limited to graphene, and may be set according to specific situations in practical applications.
The hardness of the graphene is high, and the single-layer graphene film layer is not easy to break. Graphene has a certain ductility and can be stretched by 20%. The excellent ductility of graphene enables the resulting single-layer graphene film to be very thin and light. Graphene has high conductivity: the electron mobility at normal temperature exceeds 15000cm 2/V.s, and the resistivity is low. Graphene also has high thermal conductivity and good processability. The material of the heat dissipation film layer 21 is not limited to this, and may be set according to specific situations in practical application.
Here, in order to achieve a high heat conduction effect and reduce the thermal resistance, the thermal conductivity and the material thickness of the heat dissipation material of the heat dissipation film layer 21 are considered in combination. The heat dissipation film layer 21 is preferably a single graphene film layer. The single-layer graphene has the thermal conductivity coefficient as high as 5300W/m.K, excellent heat radiation performance, is thin and can be 0.001-50.0 mu m thick.
The embodiment of the present disclosure may form the heat dissipation film layer 21 using graphene. By utilizing the characteristic of high thermal conductivity (4000 to 5300W/mK) of the graphene film layer in the direction X, Y, heat generated by the chip 22 is conducted to the other end, close to the metal connecting structure 30, of the graphene film layer, the surface, relatively close to the metal connecting structure 30, of the graphene film layer is in contact with the heat conducting film layer 23 or the metal connecting structure 30 directly, the heat of the chip 22 is transmitted out through the metal connecting structure 30 and the metal sealing cover 40, efficient heat dissipation of the chip 22 is achieved, and normal operation of the chip 22 is ensured.
In some embodiments, a ground layer may be disposed inside the package carrier 10 according to actual needs.
Here, the heat dissipation film layer 21 may include a graphene film layer. Due to the high conductivity of graphene, the chip 22 is electrically connected to the ground layer through the conductive graphene film layer and the conductive medium in the package carrier 10.
The chip packaging structure provided by the embodiment of the disclosure can also meet the requirement of the chip 22 on grounding interconnection during packaging.
In some embodiments, chip 22 comprises a high frequency front-mounted chip.
For high-frequency chips, especially gallium arsenide, gallium nitride and other chips, a high-frequency signal interconnection link is designed on the surface layer of the high-frequency chip. In the traditional packaging structure, a metal conductor is arranged on the surface layer of the high-frequency chip for heat dissipation. However, the metal conductor for heat dissipation may be in direct contact with or in close proximity to the conductor in the high-frequency signal interconnection link on the surface layer of the high-frequency chip and the gold wire bonding wire, which may cause problems such as crosstalk, resonance, and antenna effect of the high-frequency signal interconnection link during transmission, and may seriously affect the signal transmission performance of the high-frequency chip.
In the chip packaging structure provided by the embodiment of the present disclosure, the chip 22 includes a high-frequency normally-mounted chip, and because there is no additional metal conductor or other objects such as a plastic package adhesive layer on the upper surface of the high-frequency normally-mounted chip, the chip will not directly contact or be in close proximity to a conductor in a high-frequency signal interconnection link on the upper surface of the high-frequency normally-mounted chip, a gold wire bonding wire, and the like, so that the problems of crosstalk, resonance, antenna effect, and the like of a high-frequency signal during transmission are reduced. On the premise of not influencing the signal transmission performance of the chip, the efficient heat dissipation is realized, and the normal operation of the chip is ensured.
In some embodiments, referring to fig. 4, the metal connection structure 30 and the metal cover 40 are a unitary structure.
In practical applications, the metal cap 40 may be adhered to the package carrier 10 by a sealant or solder 70, so that the bump portion inside the metal cap 40, i.e. the metal connection structure 30, may be in full contact with the heat conducting film layer 23.
In addition, the metal connection structure 30 and the metal cover 40 may be a connected structure. At this time, in order to reduce the occurrence of poor contact and decrease the heat conduction efficiency, it is also necessary to provide a TIM layer between the metal connection structure 30 and the metal lid 40. A first surface of the metal connection structure 30 is in contact with the metal cap 40 via the TIM layer, and a second surface of the metal connection structure 30 is in contact with a surface of the thermally conductive film layer 23 relatively close to the metal connection structure 30. In some embodiments, the package carrier 10 and the metal cover 40 are hermetically connected to form a sealed cavity. The chip packaging structure with the sealing cavity enables an air layer with low dielectric loss to exist above the chip 22, and the dielectric loss factor of the air is far smaller than that of plastic packaging materials such as common plastic packaging glue, so that the dielectric loss caused by the fact that the chip needs to directly contact the plastic packaging glue in the traditional chip packaging process can be reduced, and the performance loss of the chip 22 in the signal transmission process is effectively reduced.
In the embodiment of the present disclosure, the metal connection structure 30 and the metal cover 40 are integrated, and compared with the case that the metal connection structure 30 and the metal cover 40 are integrated, the embodiment of the present disclosure not only can significantly improve the thermal conductivity of the heat generated by the chip on the heat dissipation path, but also has a simple manufacturing process and a low cost.
According to a second aspect of the embodiments of the present disclosure, there is provided a chip packaging method, and referring to fig. 5, the chip packaging method includes:
s10, providing a package carrier, forming a groove on the surface of the package carrier;
s20, forming a heat dissipation film layer covering the bottom surface of the groove;
s30, bonding the chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove; the covering area of the heat dissipation film layer on the bottom surface of the groove is larger than the area of the bottom surface of the chip;
s40, forming a metal connecting structure contacting with the heat dissipation film layer on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove; the position of the metal connecting structure is different from that of the chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove;
s50, fixedly connecting a metal cover and the package carrier plate to make the package carrier plate and the metal cover be hermetically connected to form a sealed cavity; and the surface of the metal connecting structure relatively far away from the heat dissipation film layer is contacted with the metal sealing cover.
In some embodiments, the package carrier may be made of an insulating material such as a ceramic board or an organic board. And etching the surface of the packaging carrier plate to form a groove. The etching method includes, but is not limited to, dry etching.
Specifically, a heat dissipation material may be coated/printed/sprayed/dip-coated on a surface groove of the package carrier, the groove is filled with the heat dissipation material according to the designed thickness of the heat dissipation film, and the heat dissipation film is formed after curing and molding. Or, directly growing the heat dissipation film layer on the surface groove of the packaging and loading plate by a chemical vapor deposition method. Or, bonding a pre-formed heat dissipation film layer in the surface groove of the package carrier.
The method of forming the heat dissipation film layer covering the bottom surface of the groove is not limited to this, and may be set according to specific situations in practical applications.
In some embodiments, the bottom surface of the chip is bonded to the surface of the heat-dissipating film layer relatively far away from the bottom surface of the groove by an adhesive layer.
Here, different types of bonding layer materials are used for chips of different structure types. The adhesive layer may be made of a conductive material such as a conductive paste, a eutectic material, or the like, or may be made of an insulating material such as an insulating paste. The thermal conductivity of the adhesive layer material may be 0.5W/mK or more, and the upper limit of the thermal conductivity of the adhesive layer material is not limited. The higher the thermal conductivity coefficient of the bonding layer material is, the better the heat of the chip can be transmitted to the heat dissipation film layer.
The bottom surface of the groove of the packaging carrier plate is covered with a heat dissipation film layer. In order to better conduct the heat generated by the chip away, the coverage area of the heat dissipation film layer on the bottom surface of the groove needs to be larger than the area of the bottom surface of the chip. Namely, except the area where the chip is located, the periphery of the chip is also covered with the heat dissipation film layer. The heat dissipation film layer has excellent heat diffusion and heat radiation performance, so that high-density heat generated by the chip can be timely expanded to the surface of the whole heat dissipation film layer and then output, and the overall heat dissipation capacity of the chip packaging structure is greatly improved.
The packaging carrier plate comprises a surface and a groove which is sunken from the surface and is used for accommodating a chip, wherein a side surface is arranged in the groove, and the chip is provided with an upper surface and a side surface. For the mode that bonds the chip bottom surface on the plane surface at the encapsulation support plate, this embodiment can be at the recess internal fixation chip, through bonding two or three side surfaces with the recess side of chip for the chip is difficult for the roll-off in transmission process, satisfies the assembly demand of chip, and need not to set up the plastic envelope glue film that is used for fixed chip above the chip, has simplified packaging technology, practices thrift the cost.
In some embodiments, there may be a height difference between the surface of the package carrier and the upper surface of the chip or the surface of the package carrier is flush with the upper surface of the chip. The height difference between the package carrier and the chip may be that the surface of the package carrier is higher or lower than the upper surface of the chip.
In the embodiment, the chip is preferably placed in the groove of the package carrier, the surface of the package carrier is flush with the upper surface of the chip, the connection length between the chip and the surface of the package carrier can be effectively shortened, the subsequent electric connection between the chip and the package carrier is conveniently realized, the performance loss of the chip in the signal transmission process is effectively reduced, and therefore the signal transmission capability between the chip and the package carrier is improved.
In addition, the side margin between the side surface of the groove of the package carrier and the side surface of the chip can be set according to the connection length between the chip and the package carrier.
Here, a groove is etched on the surface of the package carrier. However, the number of the grooves is not limited to this, and in practical applications, the number of the grooves can be set according to the specific number and the specific size of the packaged chips. The depth of the groove can be designed according to the thickness of the carrier plate of the packaging carrier plate and the thickness of the chip.
The chip package structure of the present embodiment may include two chips. The number of chips is not limited to this, and may be set according to specific situations in practical applications, and the number of chips may be 1, 2 or more.
In some embodiments, a metal material may be coated/printed/sprayed/dip-coated on the surface of the heat dissipation film layer relatively far from the bottom surface of the groove, and the metal connection structure is formed after curing and molding. Or, directly growing the metal connecting structure on the surface groove of the encapsulation loading plate by a chemical vapor deposition method to obtain the metal connecting structure. Or, a preformed metal connecting structure is adhered to the bottom surface of the heat dissipation film layer relatively far away from the groove.
The manner of forming the metal connection structure is not limited to this, and may be set according to specific situations in practical applications.
In some embodiments, in order to protect the chip and achieve a better sealing effect, the metal cap is fixed on the package carrier by using a sealant or a solder. The mode of sealing by adopting the sealant or the solder can realize the airtight or quasi-airtight packaging inside the chip packaging structure, thereby effectively protecting the chip.
In some embodiments, the position of the metal connection structure on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove is different from the position of the chip, that is, the chip is in contact with a first area of the upper surface of the heat dissipation film layer, and the metal connection structure is in contact with a second area of the upper surface of the heat dissipation film layer, wherein the first area is different from the second area. The heat generated by the chip can be conducted to the metal connecting structure contacted with the other end of the heat dissipation film layer through the heat dissipation film layer contacted with the bottom of the chip, and the heat of the chip is transmitted out through the metal connecting structure and the metal sealing cover, so that the efficient heat dissipation of the chip is realized.
Because other objects such as extra metal conductors or plastic packaging adhesive layers do not exist on the upper surface of the chip, the chip can not be in direct contact with or very close to conductors in a signal link of the upper surface of the chip, gold wire bonding wires and the like, the problems of crosstalk, resonance, antenna effect and the like of chip signals during transmission are reduced, the signal transmission performance of the chip can not be influenced, and the normal operation of the chip is ensured.
The chip packaging method provided by the embodiment of the disclosure realizes efficient heat dissipation on the premise of not influencing the signal transmission performance of the chip.
In some embodiments, the method further comprises:
forming a heat-conducting film layer on the surface of the heat-radiating film layer relatively far away from the bottom surface of the groove, wherein the position of the heat-conducting film layer is different from that of the chip on the surface of the heat-radiating film layer relatively far away from the bottom surface of the groove;
after the heat-conducting film layer is formed, a metal connecting structure is formed on the surface of the heat-conducting film layer relatively far away from the heat-radiating film layer.
In practical application, a heat conducting film layer is arranged between the heat dissipation film layer and the metal connecting structure. After the heat generated by the chip is conducted to the heat conducting film layer by the heat radiating film layer, the heat of the chip is transmitted out through the metal connecting structure and the metal sealing cover.
Illustratively, a heat conducting film layer is located between the heat dissipation film layer and the metal connection structure for conducting heat between the heat dissipation film layer and the metal connection structure. The thermal conductivity of the thermal conductive film is relatively high.
In some embodiments, the heat conductive film layer can deform under the action of an external force. Specifically, in the process of preparing the chip package structure, a heat conductive film layer covering the heat dissipation film layer may be formed, and then the metal connection structure is placed on the heat conductive film layer. It should be emphasized that the metal connection structure may apply a certain pressure to the heat conducting film layer, and the heat conducting film layer with a certain flexibility deforms under the action of the pressure, so that the heat conducting film layer is not only located between the metal connection structure and the heat dissipation film layer, but also at least part of the constituent materials of the heat conducting film layer extend to at least part of the side surface wrapping the metal connection structure, so as to increase the contact area between the heat conducting film layer and the metal connection structure, and to facilitate the increase of the heat conducting effect.
The material of the heat conductive film layer may include heat conductive silicone, vulcanized rubber, or metal (gold, silver, copper, etc.). However, the material of the heat conducting film layer 23 is not limited to this, and may be set according to specific situations in practical applications.
Here, the Material of the heat conductive film layer is preferably a heat conductive Interface Material (TIM). The TIM may be a silicone gel. TIMs have some flexibility and higher thermal conductivity.
Because TIM has certain flexibility, can produce deformation, and has good adhesion to metal and non-metal materials. When the TIM is in contact with the heat dissipation film layer and the metal connecting structure, the shape of the TIM can be adjusted according to the shape of the contact surface, the close contact between the heat dissipation film layer and the metal connecting structure can be realized, and the thermal contact resistance generated between the heat dissipation film layer and the metal connecting structure is reduced. The heat conductivity of the heat generated by the chip after passing through the heat conducting film layer is higher than that of the heat generated by the chip without the heat conducting film layer.
The material of the heat conducting film layer is not limited to this, and may be set according to the specific situation in the practical application.
The embodiment of the disclosure adds the heat-conducting film layer, and compared with the direct contact between the heat-radiating film layer and the metal connecting structure, the increased heat-conducting film layer can improve the contact stability between the heat-radiating film layer and the metal connecting structure and reduce the thermal contact resistance generated between the heat-radiating film layer and the metal connecting structure. And the heat conduction film layer also has high heat conductivity, so that the heat conductivity of heat generated by the chip on a heat dissipation path can be obviously improved.
In some embodiments, after attaching the die to the surface of the heat-spreading film layer opposite to the bottom surface of the groove, the method further comprises:
and forming a bonding structure between the chip and the packaging carrier plate, wherein a conductive medium is arranged in the packaging carrier plate, and the chip is electrically connected with the conductive medium through the bonding structure.
In practical applications, the bonding structure may include a bonding wire, and the material of the bonding wire may be one or more of silver, gold, aluminum, copper, chromium, nickel, or an alloy thereof. The bonding wire can be manufactured by adopting the processes of evaporation, electroplating, metal wire ball planting and the like.
Specifically, the bonding wires may include gold bonding wires, and the electrical connection between the chip and the conductive medium in the package carrier is completed by using the gold bonding wires.
Here, the bonding wire may take the form of a single, double, or multiple pieces. The bonding wire can realize smaller integrated inductance and improve the packaging performance.
In some embodiments, the chip is placed in the groove of the packaging carrier plate, and the surface of the packaging carrier plate is flush with the upper surface of the chip, so that the connection length of a bonding wire between the chip and the surface of the packaging carrier plate can be effectively shortened, the parasitic inductance of the bonding wire is reduced, the signal transmission capability between the chip and the packaging carrier plate is improved, and the radio frequency performance of the chip is ensured.
In addition, the chip and the conductive medium in the package carrier are electrically connected, and an optional implementation manner further includes: interconnection pads (not shown) are disposed between the side surface of the groove and the side surface of the chip of the package carrier, wherein one example of the interconnection pads may be Ball Grid Array (BGA) bumps. And welding the side surface of the chip and the corresponding ball grid array salient points on the side surface of the groove of the packaging carrier plate to complete the electric connection between the chip and the conductive medium in the packaging carrier plate. The method has higher integration level, but has certain requirements on the area of the side surface of the groove of the package carrier, and if the area of the side surface of the groove of the package carrier is relatively smaller, the complexity of the manufacturing process is higher.
The manner of electrically connecting the chip and the conductive medium in the package carrier is not limited to this, and may be set according to specific situations in practical applications.
According to the embodiment of the disclosure, the chip and the conductive medium in the package carrier plate are electrically connected through the bonding structure, so that the chip can conveniently transmit signals.
In some embodiments, the method further comprises:
forming a conductive structure on the surface of the packaging carrier plate relatively far away from the metal sealing cover; the conductive medium and the bonding structure are electrically connected with the chip and are configured to realize signal input and output of the chip packaging structure.
Here, the package carrier may be stacked by multiple ceramic substrates. And conductive media can be arranged on each layer of ceramic substrate in the packaging carrier plate according to actual needs.
In the specific implementation process, the fewer the turning or connecting nodes in the electric connection, the better the electric connection characteristic is. Therefore, the smaller the number of layers of the ceramic substrate constituting the package carrier, the better the electrical connection characteristics.
The conductive structure in the embodiment of the disclosure may include a ball grid array BGA structure, and the signal input and output of the chip package structure is realized by electrically connecting the ball grid array structure, the conductive medium, and the bonding structure to the chip.
In some embodiments, the heat dissipation film layer may include:
a graphene film layer;
and/or the presence of a gas in the gas,
a metal film layer.
In practical applications, the heat dissipation film layer may be a single-layer structure or a multi-layer structure. The heat dissipation film layer can be one or more of a graphene film layer, a metal film layer and a carbon nanotube layer or a combination thereof.
In some embodiments, the thinner the material thickness, the lower the thermal resistance. In consideration of the thickness of the encapsulating board and the thickness of the chip, the heat dissipation film layer is preferably a single-layer structure.
The metal film layer may be made of gold, silver, copper, etc. and has a thermal conductivity of about 300-420W/m.k. The thermal conductivity of carbon nanotubes is about 1750W/m.K. The thermal conductivity of the graphene is more than 4000W/m.K. The higher the heat conductivity coefficient is, the better the heat conduction effect is, and the material of the preferred heat dissipation film layer is graphene.
In some embodiments, since the graphene surface has a certain adhesiveness, when the heat dissipation film layer covering the bottom surface of the groove is formed, an adhesive layer does not need to be disposed between the groove and the heat dissipation film layer, and the heat dissipation film layer made of the graphene material can be adhered to the bottom surface of the groove through the surface adhesiveness. Moreover, the surface of the heat dissipation film layer, which is relatively far away from the bottom surface of the groove, can be bonded with the chip through the graphene surface adhesion, and an adhesive layer does not need to be arranged between the heat dissipation film layer and the chip. Compared with the bonding layers such as conductive silver adhesive and the like which are required to be arranged when the material of the heat dissipation film layer is metal or carbon nano tubes, the material of the heat dissipation film layer is graphene, so that the packaging process can be simplified, and the cost is saved.
Here, the heat dissipation rete can also select other surfaces to have sticky heat conduction material, is not limited to graphite alkene, can set for according to particular case in the practical application.
The hardness of the graphene is high, and the single-layer graphene film layer is not easy to break. Graphene has a certain ductility and can be stretched by 20%. The excellent ductility of graphene enables the resulting single-layer graphene film to be very thin and light. Graphene has high conductivity: the electron mobility at normal temperature exceeds 15000cm2V.s, and low resistivity. Graphene also has high thermal conductivity and good processability. The material of the heat dissipation film layer is not limited to this, and may be set according to specific situations in practical applications.
Here, in order to achieve a high heat conduction effect and reduce thermal resistance, the thermal conductivity and material thickness of the heat dissipation material of the heat dissipation film layer are considered comprehensively. The heat dissipation film layer is preferably a single-layer graphene film layer. The single-layer graphene has the thermal conductivity coefficient as high as 5300W/m.K, excellent heat radiation performance, is thin and can be 0.001-50.0 mu m thick.
The embodiment of the present disclosure may form a heat dissipation film layer using graphene. By utilizing the characteristic of high thermal conductivity (4000-5300W/mK) of the graphene film layer in the direction X, Y, heat generated by the chip is conducted to the other end, close to the metal connecting structure, of the graphene film layer, the surface, relatively close to the metal connecting structure, of the graphene film layer is in contact with the heat conducting film layer or directly with the metal connecting structure, the heat of the chip is transmitted out through the metal connecting structure and the metal sealing cover, efficient heat dissipation of the chip is achieved, and normal operation of the chip is guaranteed.
In some embodiments, a ground layer may be disposed inside the package carrier according to actual needs.
Here, the heat dissipation film layer may include a graphene film layer. Due to the high conductivity of the graphene, the chip is electrically connected to the grounding layer through the conductive graphene film layer and the conductive medium in the packaging carrier plate.
The chip packaging structure provided by the embodiment of the disclosure can also meet the grounding interconnection requirement of the chip during packaging.
In some embodiments, the chip may comprise a high frequency front-mounted chip.
For high-frequency chips, especially gallium arsenide, gallium nitride and other chips, a high-frequency signal interconnection link is designed on the surface layer of the high-frequency chip. In the traditional packaging structure, a metal conductor is arranged on the surface layer of the high-frequency chip for heat dissipation. However, the metal conductor for heat dissipation may be in direct contact with or in close proximity to the conductor in the high-frequency signal interconnection link on the surface layer of the high-frequency chip and the gold wire bonding wire, which may cause problems such as crosstalk, resonance, and antenna effect of the high-frequency signal interconnection link during transmission, and may seriously affect the signal transmission performance of the high-frequency chip.
According to the chip packaging structure provided by the embodiment of the disclosure, the chip can comprise a high-frequency normally-installed chip, and because no additional metal conductor or other objects such as a plastic packaging adhesive layer exist on the upper surface of the high-frequency normally-installed chip, the chip cannot be in direct contact with or very close to a conductor in a high-frequency signal interconnection link on the upper surface of the high-frequency normally-installed chip, a gold wire bonding wire and the like, so that the problems of crosstalk, resonance, antenna effect and the like of a high-frequency signal during transmission are reduced. On the premise of not influencing the signal transmission performance of the chip, the efficient heat dissipation is realized, and the normal operation of the chip is ensured.
In some embodiments, the metal connecting structure and the metal cover are a unitary structure.
In practical application, the metal sealing cover can be adhered to the package carrier plate through sealant or solder, so that the bump portion inside the metal sealing cover, i.e. the metal connection structure, can be in full contact with the heat dissipation film layer or the heat conduction film layer.
In addition, the metal connecting structure and the metal cover can be of a connected structure. At this time, in order to reduce the occurrence of poor contact and decrease the heat conduction efficiency, it is also necessary to provide a TIM layer between the metal connection structure and the metal cap. The first surface of the metal connecting structure is contacted with the metal sealing cover through the TIM layer, and the second surface of the metal connecting structure is contacted with the surface of the heat conducting film layer relatively close to the metal connecting structure. In some embodiments, the package carrier and the metal cap are hermetically connected to form a sealed cavity. The chip packaging structure with the sealing cavity enables an air layer with low dielectric loss to exist above the chip, and the dielectric loss factor of the air is far smaller than that of common plastic packaging materials such as plastic packaging glue, so that the dielectric loss caused by the fact that the chip needs to directly contact the plastic packaging glue in the traditional chip packaging process can be reduced, and the performance loss of the chip in the signal transmission process is effectively reduced.
The metal connecting structure and the metal sealing cover are arranged into an integral structure, so that the heat conductivity of heat generated by the chip on a heat dissipation path can be obviously improved, and the manufacturing process is simple and the cost is low compared with the case that the metal connecting structure and the metal sealing cover are of an integral structure.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing module, or each unit may be separately regarded as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit. Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The methods disclosed in the several method embodiments provided in this disclosure may be combined arbitrarily without conflict to arrive at new method embodiments.
Features disclosed in several of the product embodiments provided in this disclosure may be combined in any combination to yield new product embodiments without conflict.
The features disclosed in the several method or apparatus embodiments provided in this disclosure may be combined in any combination to arrive at a new method or apparatus embodiment without conflict.
The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present disclosure, and all the changes or substitutions should be covered within the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (10)

1. A chip package structure, comprising:
the packaging structure comprises a packaging carrier plate, a heat dissipation structure layer, a metal connecting structure and a metal sealing cover which are arranged in a stacked mode, wherein a groove is formed in the surface, close to the metal sealing cover, of the packaging carrier plate;
the heat radiation structure layer comprises: the heat dissipation film layer and the chip are sequentially stacked on the bottom surface of the groove, wherein the coverage area of the heat dissipation film layer on the bottom surface of the groove is larger than the area of the bottom surface of the chip;
the metal sealing cover is fixed on the packaging carrier plate, and the packaging carrier plate and the metal sealing cover are connected in a sealing manner to form a sealed cavity;
the metal connecting structure is fixed in the sealed cavity, a first surface of the metal connecting structure is in contact with the metal sealing cover, a second surface of the metal connecting structure is in contact with a surface of the heat dissipation film layer, which is relatively close to the metal connecting structure, and the first surface and the second surface are opposite.
2. The chip package structure of claim 1, wherein the heat dissipation structure layer further comprises: a heat conductive film layer; wherein the content of the first and second substances,
the first surface of the heat conducting film layer is in contact with the surface of the heat dissipation film layer relatively close to the metal connecting structure, and the second surface of the heat conducting film layer is in contact with the second surface of the metal connecting structure;
and on the surface of the heat dissipation film layer relatively close to the metal connecting structure, the position of the heat conduction film layer is different from that of the chip.
3. The chip package structure of claim 1,
the chip packaging structure further comprises: a bonding structure;
a conductive medium is arranged in the packaging carrier plate;
wherein the chip and the conductive medium are electrically connected through the bonding structure.
4. The chip package structure according to claim 3, further comprising:
and the conductive structure is positioned on the surface of the package carrier plate relatively far away from the metal sealing cover, is electrically connected with the chip through the conductive medium and the bonding structure, and is configured to realize the signal input and output of the chip packaging structure.
5. The chip package structure according to claim 1, wherein the heat dissipation film layer comprises:
a graphene film layer;
and/or the presence of a gas in the gas,
a metal film layer.
6. The chip package structure of claim 1, wherein the chip comprises a high frequency front-mounted chip.
7. The chip package structure according to claim 1, wherein the metal connection structure and the metal cap are a unitary structure.
8. A method of chip packaging, the method comprising:
providing a packaging carrier plate, and forming a groove on the surface of the packaging carrier plate;
forming a heat dissipation film layer covering the bottom surface of the groove;
bonding a chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove; the covering area of the heat dissipation film layer on the bottom surface of the groove is larger than the area of the bottom surface of the chip;
forming a metal connecting structure in contact with the heat dissipation film layer on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove; the position of the metal connecting structure is different from that of the chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove;
fixedly connecting a metal sealing cover and the packaging carrier plate to enable the packaging carrier plate and the metal sealing cover to be connected in a sealing mode to form a sealed cavity; and the surface of the metal connecting structure relatively far away from the heat dissipation film layer is contacted with the metal sealing cover.
9. The chip packaging method according to claim 8, further comprising:
forming a heat conducting film layer on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove, wherein the position of the heat conducting film layer is different from that of the chip on the surface of the heat dissipation film layer relatively far away from the bottom surface of the groove;
and after the heat conduction film layer is formed, forming the metal connecting structure on the surface of the heat conduction film layer relatively far away from the heat dissipation film layer.
10. The method of claim 8, wherein after the attaching the die to the surface of the heat-spreading film layer relatively far from the bottom surface of the groove, the method further comprises:
and forming a bonding structure between the chip and the packaging carrier plate, wherein a conductive medium is arranged in the packaging carrier plate, and the chip is electrically connected with the conductive medium through the bonding structure.
CN202111535118.0A 2021-12-15 2021-12-15 Chip packaging structure and method Pending CN114220778A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116759388A (en) * 2023-08-18 2023-09-15 合肥阿基米德电子科技有限公司 Welding-free module packaging structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116759388A (en) * 2023-08-18 2023-09-15 合肥阿基米德电子科技有限公司 Welding-free module packaging structure
CN116759388B (en) * 2023-08-18 2023-10-27 合肥阿基米德电子科技有限公司 Welding-free module packaging structure

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