CN114205994A - Circuit board - Google Patents
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- CN114205994A CN114205994A CN202111348860.0A CN202111348860A CN114205994A CN 114205994 A CN114205994 A CN 114205994A CN 202111348860 A CN202111348860 A CN 202111348860A CN 114205994 A CN114205994 A CN 114205994A
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- 230000008054 signal transmission Effects 0.000 abstract description 11
- 239000010410 layer Substances 0.000 description 268
- 238000010586 diagram Methods 0.000 description 19
- 238000000034 method Methods 0.000 description 10
- 238000003475 lamination Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/024—Dielectric details, e.g. changing the dielectric material around a transmission line
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
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Abstract
The present application relates to a circuit board, which includes: the circuit comprises at least one first circuit layer and at least one second circuit layer, wherein the first circuit layer and the second circuit layer are arranged at intervals in the vertical direction, and the first circuit layer is provided with a gradual change signal line; the second circuit layer comprises a hollow-out area, and the position of the hollow-out area corresponds to the position of the gradual change signal line on the adjacent first circuit layer. Because the hollowed-out area is hollowed out according to the wiring mode of the gradually-changed signal line on the first circuit layer, the thicker line width can be designed on the first circuit layer by increasing the thickness of the medium, and the purpose of reducing the signal loss is achieved. Correspondingly, the impedance change of the area where the gradual change line signal is located can be minimized by optimizing the hollow-out area, so that the problem of discontinuous impedance of the gradual change line area is solved, and the signal transmission quality of the circuit on duty is improved.
Description
Technical Field
The present application relates to the field of electronic technology, and more particularly, to a circuit board.
Background
With the continuous development of electronic technology, especially high-speed signal technology, such as 32G two-level signal Modulation (Non-Return-to-Zero, NRZ) and 56G four-level signal Modulation (PAM 4), the requirement for signal quality is higher and higher.
At present, for the routing of a high-speed signal link, the problem of large signal loss caused by the fact that the routing length and the routing path cannot be further optimized generally exists. In order to reduce signal loss, wider traces may be designed in a local area on the circuit board to reduce signal loss. However, the connector area or Fan-out (Fan-out) area of the chip on the circuit board has dense via holes, and the line width of the wiring cannot be increased, these areas can only select thin lines to ensure the Fan-out of the wiring, and the area outside the connector or Fan-out area of the chip (i.e. Open Field area) can select wide lines to control the loss, in this process, the design of a gradual change line occurs, and the gradual change line represents an impedance discontinuity point, and when a signal with a fast rising edge encounters impedance discontinuity, the phenomena of signal reflection, jitter and the like which affect the signal quality are generated.
Therefore, how to increase the line width of the signal line and reduce the impedance discontinuity of the gradual change region becomes a technical problem to be solved when the signal line is laid out on the lower circuit board.
Disclosure of Invention
In view of the above, it is necessary to provide a circuit board, in which the trace and ground hole design of each circuit layer of the circuit board is optimized to reduce the problem of discontinuous impedance of the gradual change region on the circuit board.
In a first aspect, a circuit board, the circuit board comprising: the circuit comprises at least one first circuit layer and at least one second circuit layer, wherein the first circuit layer and the second circuit layer are arranged at intervals in the vertical direction, and a gradual change signal line is arranged on the first circuit layer;
the second circuit layer comprises a hollow-out area, and the position of the hollow-out area corresponds to the position of the gradient signal line on the adjacent first circuit layer.
In this embodiment, since the hollow area is hollowed out according to the routing manner of the gradually-changed signal line on the first circuit layer, by increasing the thickness of the medium, a thicker line width can be designed on the first circuit layer, so as to achieve the purpose of reducing signal loss. Correspondingly, the impedance change of the area where the gradual change line signal is located can be minimized by optimizing the hollow-out area, so that the problem of discontinuous impedance of the gradual change line area is solved, and the quality of signal transmission on the circuit board is improved.
In one embodiment, the circuit board further includes a plurality of ground holes disposed around the gradation signal lines, and a horizontal distance between each ground hole and the gradation signal line is reduced as a width of the gradation signal line is reduced.
In the embodiment, the influence of the ground hole on the impedance change of the area where the gradually-changed signal line is located is considered, and the impedance discontinuity of the area where the gradually-changed signal line is located can be reduced by designing that the horizontal distance between the ground hole and the gradually-changed signal line changes along with the change of the width of the gradually-changed signal line.
In one embodiment, the shortest distance between the center point of the ground hole and the edge line of the hollowed-out area is less than a preset threshold value.
In this embodiment, the ground hole is disposed at a position close to the edge line of the hollow area, so that the impedance influence of the ground hole on the area where the gradually-changed signal line is located can be reduced.
In one embodiment, the ground holes comprise first ground holes arranged in two side areas where the width of the gradually-changed signal line is constant, and second ground holes arranged in two side areas where the width of the gradually-changed signal line is changed; the distance between two adjacent first ground holes is greater than the distance between two adjacent second ground holes.
In this embodiment, through the optimization of the placement design of the ground holes, the ground holes are arranged on the circuit board around the gradually-changing signal lines in an arc shape, which not only plays an isolation role and reduces the signal crosstalk between different gradually-changing signal lines, but also can reduce the variation of the impedance of the area where the gradually-changing signal lines are located, so as to solve the problem of discontinuous impedance of the area where the gradually-changing signal lines are located.
In one embodiment, the first circuit layer further includes at least one first flat plate disposed between two adjacent gradation signal lines in a horizontal direction.
In the embodiment, the first flat panel is arranged between different gradient signal lines in the horizontal direction, so that signal crosstalk between different gradient signal lines in the horizontal direction can be reduced, and the quality of signal transmission on the circuit board is improved.
In one embodiment, the position of the first flat panel on each first circuit layer corresponds to the position of the gradient signal line on the adjacent first circuit layer.
The circuit board structure has the advantages that the gradually-changed signal lines on different layers and the first flat panel are arranged in a staggered mode, so that the gradually-changed signal lines on the same layer are far away from each other in the horizontal direction, and the gradually-changed signal lines close to each other in the vertical direction are located on different layers, and crosstalk among the gradually-changed signal lines is reduced.
In one embodiment, the circuit board further includes a second flat panel disposed between two adjacent second circuit layers.
The second flat panel is arranged between the second circuit layers which are different in the vertical direction, so that signal crosstalk between different gradient signal lines in the vertical direction can be reduced, and the quality of signal transmission on the circuit board is improved.
In one embodiment, the first circuit layer further includes at least one third flat panel disposed between two adjacent gradation signal lines in the horizontal direction.
In the embodiment, the third flat panel is arranged between different gradient signal lines in the horizontal direction and the third flat panel is arranged between different second circuit layers in the vertical direction, so that signal crosstalk between different gradient signal lines in the horizontal direction and the vertical direction can be reduced respectively, and the quality of signal transmission on the circuit board is improved.
In one embodiment, the shape of the hollow-out area is a U shape.
In this embodiment, the design of the hollow area can facilitate the routing of the relatively wide line in the gradually-changed signal line, thereby reducing the signal loss on the circuit board
In one embodiment, the bottom of the U-shape is a three-fold line structure, and the shape of the three-fold line structure is matched with the shape of the gradually-changed signal line.
The hollow area designed by the embodiment enables the impedance change of the area where the gradual change signal line is located to be minimum, and therefore impedance discontinuity can be reduced.
Drawings
FIG. 1 is a schematic diagram of a circuit board in one embodiment;
FIG. 2 is a schematic diagram of a tapered signal line in one embodiment;
FIG. 3 is a schematic view of a hollowed-out area in one embodiment;
FIG. 4 is a schematic view of a hollowed-out area in one embodiment;
FIG. 5 is a schematic diagram of a second circuit layer in one embodiment;
FIG. 6 is a top plan view of a second circuit layer in one embodiment;
FIG. 7 is a top plan view of a first circuit layer in one embodiment;
FIG. 8 is a top plan view of a first circuit layer and a second circuit layer superimposed in one embodiment;
FIG. 9 is a top plan view of a first plane in one embodiment;
FIG. 10 is a schematic diagram of a circuit board in one embodiment;
FIG. 11 is a schematic diagram of a circuit board in one embodiment;
FIG. 12 is a top plan view of a first plane superimposed with a first circuit layer and a second circuit layer in one embodiment;
FIG. 13 is a schematic diagram of a circuit board in one embodiment;
FIG. 14 is a schematic diagram of a circuit board in one embodiment;
FIG. 15 is a schematic diagram of a circuit board in one embodiment;
FIG. 16 is a schematic diagram of a circuit board in one embodiment;
reference numerals:
a ground hole 0, a first circuit layer 1 and a second circuit layer 2;
a first ground hole 01, a second ground hole 02 and a gradual change signal line 11;
a first flat panel 12, a second flat panel 13, a third flat panel 14;
a hollow area 21, an area 211 where the bottom of the U-shape is located;
a U-shaped upper region 212, a left edge line 213 of the hollow region;
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The terms "first," "second," "third," and "fourth," etc. in the description and claims of this application and in the accompanying drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "include" and "have," as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
At present, when an existing Circuit Board, for example, a Printed Circuit Board (PCB) is wired, the routing length and routing path on the PCB may be optimized to reduce loss, but if the overall link loss on the PCB is close to a limit, the routing length and routing path may not be further optimized, and a wider routing line may be designed in a local area to reduce loss. However, the connector area or the Fan-out area of the chip on the PCB has dense via holes, so that the line width of the wiring cannot be increased, the fine lines are selected in these areas to ensure the Fan-out of the wiring, and the thick lines can be used outside the Fan-out area of the connector or the chip (Open Field area) to control the loss. Therefore, there is a design of a gradual signal line on a circuit board, and a point of impedance discontinuity may occur in an area where the gradual signal line is located, so in practical applications, when a signal with a fast rising edge encounters the point of impedance discontinuity, problems of signal reflection, jitter, and signal quality influence may occur. For the existing gradual change signal line area, the impedance change is rarely concerned, and even if the impedance change is concerned, no effective method is provided for solving or reducing the discontinuity of the impedance change, and the influence of the ground hole on the impedance of the gradual change area is not considered. In practical circuit board applications, especially when the signal rate is high, the problem of impedance discontinuity in the transition region greatly affects the quality of the signal, so how to optimize the impedance of the transition region where the transition signal line is located is important to reduce the impedance discontinuity. Based on the above problems, the problem that the impedance of a gradual change area where a gradual change signal line is located is discontinuous can be effectively solved, and the signal transmission quality is extremely high is designed. The following examples will specifically explain the circuit board provided in the present application.
Fig. 1 is a schematic diagram of a circuit board according to an embodiment, as shown in fig. 1, the circuit board includes: the circuit comprises at least one first circuit layer 1 and at least one second circuit layer 2, wherein the first circuit layer 1 and the second circuit layer 2 are arranged at intervals in the vertical direction, and a gradual change signal line 11 is arranged on the first circuit layer 1; the second circuit layer 2 includes a hollow area 21, and the position of the hollow area 21 corresponds to the position of the gradual-change signal line 11 on the adjacent first circuit layer 1.
The gradation signal line 11 is a signal line whose width is narrowed (see gradation signal line a shown in fig. 2), or may be a signal line whose width is narrowed (see gradation signal line b shown in fig. 2); the gradation signal line 11 may be a high-speed signal line or a low-speed signal line; the gradation signal line 11 may be a single signal line or a differential line pair (see gradation signal line c shown in fig. 2).
The first circuit layer 1 is provided with a plurality of connector areas, chip Fan-out areas and Open Field areas, and the connector areas or the chip Fan-out areas, and a connection area between each connector area or the corresponding chip Fan-out area and the corresponding Open Field area generally corresponds to an area where a gradually-changed signal line is located, that is, a signal line with a relatively narrow width in the gradually-changed signal line is located in the connector area or the corresponding chip Fan-out area, and a signal line with a relatively wider width in the gradually-changed signal line is located in the corresponding Open Field area, for example, a line segment with a narrower width in the gradually-changed signal line 11 in fig. 2 a is located in the connector area or the corresponding chip Fan-out area, and a line segment with a wider width in the gradually-changed signal line 11 in fig. 2 a is located in the corresponding Open Field area.
The shape of the hollow area 21 may be any shape, and the position of the hollow area 21 corresponds to the position of the gradually-changed signal line 11 on the adjacent first circuit layer, for example, referring to fig. 1, the position of the gradually-changed signal line 11 corresponds to the positions of the hollow areas 21 of the two adjacent second circuit layers 2, and the shape, size, and position of the hollow area 21 on the respective second circuit layers 2 are also the same. The relatively wide circuit of width can be walked in the gradual change signal line through the design of fretwork region, and then reduces the loss of signal on the circuit board.
Optionally, the shape of the hollow area 21 may be a U shape (such as the shape of the hollow area 21 in fig. 3), the area 211 where the bottom of the U shape is located corresponds to the width change area and a part of the area with a narrower width of the gradation signal line 11, and the area 212 where the upper of the U shape is located corresponds to a part of the area with a wider width of the gradation signal line 11. Optionally, the bottom of the U-shape is a three-fold line structure, and the shape of the three-fold line structure is adapted to the shape of the gradual change signal line 11, that is, as the shape of the hollow area 21 in fig. 4, two sides of the wider width of the gradual change signal line 11 correspond to the area where the upper portion of the U-shape is located, the gradual change signal line 11 starts to fold inward at the turning point a from wide to narrow, and finally, a straight line is taken at the position B where the gradual change signal line is to be narrowed, so as to form a three-fold line structure, and the hollow area designed in this way minimizes the impedance change of the area where the gradual change signal line is located, thereby reducing the impedance discontinuity. It should be noted that, the shape of the tri-fold line structure is adapted to the shape of the gradual change signal line 11, and it can indicate that the inclination (slope) of the fold line (such as the line segment AB in fig. 4) in the tri-fold line structure is the same as the inclination (the line segment L1 or L2 in fig. 4) of any edge line of the width change region of the gradual change signal line, such a design can further minimize the impedance change of the region where the gradual change signal line is located, and greatly reduce the impedance discontinuity.
In this embodiment, when the trace is routed on the circuit board, the location of the gradually-changed signal line can be determined on each first circuit layer on the circuit board, when the gradual change signal line is routed at the position, the medium at the corresponding position on the adjacent second circuit layer in the vertical direction of the gradual change signal line is correspondingly hollowed, for example, the layers of the circuit board in fig. 1, the layer # 2, the layer #3, the layer #4, the layer #5, the layer # 6, the layer #7, the layer # 8 and the layer #9 are defined from top to bottom in the vertical direction, and referring to the position of the first gradually-changed signal line 11 on the right side of the layer #3 in fig. 1, the corresponding medium of the second circuit layer 2 of the layer # 2 and the corresponding medium of the second circuit layer 2 of the layer #4 which are adjacent up and down are hollowed out, so that hollowed-out areas 21 on the two layers # 2 and #4 are formed, and a structure that the first circuit layer 1 and the second circuit layer 2 are arranged at intervals is formed.
It should be noted that, the shapes of the hollow areas 21 in fig. 3 and fig. 4 are adapted to the gradual-change signal lines 11, which are illustrated by taking the gradual-change signal lines with widths that are narrower than the widths of the gradual-change signal lines as examples, and for other types of gradual-change signal lines, the adaptation methods corresponding to the hollow areas are similar, and are not described again here. In addition, a plurality of gradient signal lines are arranged on the first circuit board, and a plurality of hollow areas are arranged on the second circuit board, in the above embodiments, one gradient signal line and one hollow area are used for explanation, and the characteristics of other gradient signal lines and the characteristics of the hollow areas are consistent, which is not repeated again. Moreover, fig. 1 only shows a structure including two gradient signal lines or hollow-out regions on each layer of circuit board, and the right side of the structure may be derived continuously, so that each first circuit layer includes a plurality of gradient signal lines, each second circuit layer includes a plurality of hollow-out regions, and the structure of each layer of circuit layer of each circuit board (fig. 1, 10, 11, 13, 14, 15, and 16) provided later may be extended in this way, and a description will not be repeated.
The above-mentioned circuit board includes: the circuit comprises at least one first circuit layer and at least one second circuit layer, wherein the first circuit layer and the second circuit layer are arranged at intervals in the vertical direction, and the first circuit layer is provided with a gradual change signal line; the second circuit layer comprises a hollow-out area, and the position of the hollow-out area corresponds to the position of the gradual change signal line on the adjacent first circuit layer. Because the hollowed-out area is hollowed out according to the wiring mode of the gradually-changed signal line on the first circuit layer, the thicker line width can be designed on the first circuit layer by increasing the thickness of the medium, and the purpose of reducing the signal loss is achieved. Correspondingly, the impedance change of the area where the gradual change line signal is located can be minimized by optimizing the hollow-out area, so that the problem of discontinuous impedance of the gradual change line area is solved, and the signal transmission quality of the circuit on duty is improved.
The routing of the gradual change signal line is optimized on the circuit board shown in the embodiment of fig. 1, the application also provides an optimized design method of the ground hole on the circuit board, that is, the circuit board shown in the embodiment of fig. 1 further includes a plurality of ground holes 0 disposed around the tapered signal lines 11, the horizontal distance between each ground hole 0 and the tapered signal line 11 decreases as the width of the tapered signal line 11 decreases (see the schematic plan view of the second circuit layer 2 superimposed on the first circuit layer 1 shown in fig. 5), and the shortest distance between the center point of each ground via 0 and the edge line of the hollow area 21 (the left edge line 213 of the hollow area or the right edge line 214 of the hollow area) is smaller than a preset threshold, the ground via 0 includes first ground vias 01 disposed in both side areas where the width of the gradation signal line 11 is not changed, and second ground holes 02 provided in both side areas where the width of the gradation signal line 11 changes; the distance between two adjacent first ground holes 01 is greater than the distance between two adjacent second ground holes 02.
The ground holes 0 in this embodiment are disposed on the first circuit layers 1 on two sides of the gradually-changing signal line 11, and the distance between every two adjacent ground holes 0 can be set to any distance, usually set to 30mil or 40mil, the ground holes 0 are disposed around the gradually-changing signal line 11, so that crosstalk of the gradually-changing signal line 11 can be reduced to a certain extent, and the routing is not uniform in the area where the gradually-changing signal line is located, so that the ground holes 0 need to be disposed in a certain manner, as shown in fig. 5, the placement of the ground holes 0 is optimized, specifically, the ground holes 0 are disposed in the two side areas of the gradually-changing signal line 11, for example, three first ground holes 01 are disposed in the two side areas where the width of the gradually-changing signal line 11 is not changed, and are symmetrically disposed, and two second ground holes 02 are disposed in the two side areas where the width of the gradually-changing signal line 11 is changed, and are symmetrically disposed, along with the change of the width of the gradually-changing signal line 11, the distance between the adjacent ground holes 0 also changes with the width of the gradually-changed signal line 11, specifically, decreases with the narrowing of the width of the gradually-changed signal line 11, the distance between two adjacent first ground holes 01 is the same, the distance between two adjacent second ground holes 02 is the same, as shown in fig. 5, the distance between two adjacent first ground holes 01 is greater than the distance between two adjacent second ground holes 02, for example, the distance between the first ground holes 01 is 30 mils, and the distance between the second ground holes 02 is 20 mils. The optimized design of the arrangement position of the ground holes considers the influence of the ground holes on the impedance change of the area where the gradual change signal line is located, and the impedance discontinuity of the area where the gradual change signal line is located can be reduced by designing that the horizontal distance between the ground holes and the gradual change signal line changes along with the width change of the gradual change signal line.
In practical applications, the ground hole 0 is usually disposed near an edge line of the hollow area 21, for example, a distance between the first ground hole 01 on the left and the left edge line 213 of the hollow area 21 is smaller than a preset threshold, and a distance between the first ground hole 01 on the right and the right edge line 214 of the hollow area 21 is smaller than a preset threshold; the distance between the second hole 02 on the left and the left edge line 213 of the hollow area 21 is smaller than the preset threshold, and the distance between the second hole 02 on the right and the right edge line 214 of the hollow area 21 is smaller than the preset threshold. The preset threshold may be determined in advance according to the requirement of the optimized ground hole, and in general, the preset threshold is small, so that the first ground hole 01 on the left side of the first circuit layer 1 is very close to the left edge line 213 of the hollow area 21, and the first ground hole 01 on the right side is very close to the right edge line 214 of the hollow area 21; the second hole 02 on the left side of the first circuit layer 1 is close to the left edge 213 of the hollow area 21, and the second hole 02 on the right side is close to the right edge 214 of the hollow area 21, so as to isolate different gradient signal lines 11. In addition, the ground hole is arranged at a position which is close to the edge line of the hollow area, so that the impedance influence of the ground hole on the area where the gradual change signal line is located can be reduced. Referring to the design effect diagram of the ground holes placed near the hollowed-out area on the second circuit layer of the actual design circuit board, as shown in fig. 6, for example, the diagram may represent a top plan view of the ground holes placed near the hollowed-out area on the second circuit layer of the layer # 2 on the circuit board in fig. 1, or may represent a top plan view of the ground holes placed near the hollowed-out area on any other layer, which is not limited herein. In addition, a top plan view of the first circuit layer of the actual designed circuit board may also be seen, as shown in fig. 7, in which the ground holes are arranged on the first circuit board 1 around the gradually changed signal lines, and this view may represent a top plan view of the first circuit layer 1 of any one of the layers # 1, #5 and #9 on the circuit board in fig. 1. Further, referring to a top plan view of a second wiring layer of an actually designed circuit board superimposed on a first wiring layer, as shown in fig. 8, for example, a top plan view of a second wiring layer 2 of a #2 layer superimposed on a first wiring layer 1 of a #1 layer on the circuit board in fig. 1, or a top plan view of the other two wiring layers superimposed may be shown.
It should be noted that, the placement of the ground holes 0 (including 01 and 02) in fig. 5, 6, 7, or 8 is adapted to the tapered signal lines 11, which are all described by taking a differential trace type tapered signal line with a width that is narrowed from a wide width as an example, and for other types of tapered signal lines, the placement method of the ground holes 0 is similar, and the description is omitted here.
In the above embodiment, the placement design of the ground holes is optimized, so that the ground holes are arranged on the circuit board around the gradually-changing signal lines in an arc shape, which not only plays a role in isolation and reduces signal crosstalk between different gradually-changing signal lines, but also can reduce the impedance variation of the area where the gradually-changing signal lines are located, thereby solving the problem of discontinuous impedance of the area where the gradually-changing signal lines are located.
The first circuit layer 1 in any of the above embodiments further includes at least one first flat plate 12, and the first flat plate 12 is disposed between two adjacent gradient signal lines 11 in the horizontal direction.
The first plane board 12 can be used as a reference plane of the gradual change signal line 11, the first plane board 12 is provided with a ground hole 0, and the ground hole is opened in the lamination direction (vertical direction) of the circuit board, so that the placing design of the ground hole on the first plane board 12 is the same as the placing design of the ground hole on the first circuit layer and the placing design of the ground hole on the second circuit board, as shown in the top plan view of the first plane board in fig. 9.
The circuit board structure according to the present embodiment is exemplified, for example, as a schematic diagram of a circuit board shown in fig. 10, the layers where the circuit layers in the circuit board are located, layer #1, layer #2, layer #3, layer #4, layer #5, layer #6, layer #7, layer #8 and layer #9 are defined from top to bottom in the vertical direction, and the circuit layers in the middle of the circuit board are exemplified, the first flat plate 12 of the first wiring layer 1 on the layer #1 is disposed between the adjacent two gradation signal lines 11 on the layer #1, the first flat plate 12 of the first wiring layer 1 on the layer #5 is disposed between the adjacent two gradation signal lines 11 on the layer #5, the gradation signal lines 11 corresponding to the two first flat panels 12 are on the first line layer 11 of the #3 layer, and therefore, the gradation signal line 11 on the first line layer 11 of the #3 layer takes the first plane plate 12 of the #1 layer or the first plane plate 12 of the #5 layer as a reference plane; accordingly, the first plane board 12 of the first line layer 1 on the layer #9 is disposed between two adjacent gradation signal lines 11 on the layer #9, the first plane board 12 of the first line layer 1 on the layer #5 is disposed between two adjacent gradation signal lines 11 on the layer #5, and the gradation signal line 11 corresponding to these two first plane boards 12 is on the first line layer 11 on the layer #7, so that the gradation signal line 11 on the first line layer 11 on the layer #7 is referenced to the first plane board 12 on the layer #5 or the first plane board 12 on the layer # 9. In the embodiment, the first flat panel is arranged between different gradient signal lines in the horizontal direction, so that signal crosstalk between different gradient signal lines in the horizontal direction can be reduced, and the quality of signal transmission on the circuit board is improved.
Optionally, based on the first flat panel provided in the foregoing embodiment, the structure of the circuit board may also be as shown in fig. 11, where the first flat panel 12 is disposed between two adjacent gradually-changed signal lines 11 in the horizontal direction, and also may reduce signal crosstalk between different gradually-changed signal lines 11 in the horizontal direction, and the middle gradually-changed signal line on the #3 layer may also use the first flat panel 12 on the #1 layer or the first flat panel 12 on the #5 layer as a reference plane; the middle tapered signal line on layer #7 may also have the first plane plate 12 of layer #5 or the first plane plate 12 of layer #9 as a reference plane.
Optionally, the position of the first flat plate 12 on each first circuit layer 1 on the circuit board provided by the present application corresponds to the position 11 of the gradually-changed signal line on the adjacent first circuit layer 1. As shown in fig. 10, for example, the position of the first flat board 12 on the #1 layer corresponds to the position of the gradation signal line 11 on the first wiring layer 1 of the adjacent #3 layer; the position of the first flat panel 12 on the #5 layer corresponds to the position of the gradation signal line 11 on the first wiring layer 1 of the adjacent #3 layer, and corresponds to the position of the gradation signal line 11 on the first wiring layer 1 of the adjacent #7 layer; the position of the first flat panel 12 on layer #9 corresponds to the position of the gradation signal line 11 on the first wiring layer 1 of the adjacent layer # 7. The design forms a circuit board structure in which the gradually-changed signal lines on different layers and the first flat panel are arranged in a staggered mode, and an interlayer reference design scheme is achieved, so that the gradually-changed signal lines on the same layer are far away from each other in the horizontal direction, and the gradually-changed signal lines closer to each other in the vertical direction are located on different layers, and therefore crosstalk between the gradually-changed signal lines is reduced.
In addition, when there is the first flat panel, see a top plan view of the first flat panel overlapping the second circuit layer and the first circuit layer, as shown in fig. 12, where the first flat panel 12 overlaps the second circuit layer and the first circuit layer from top to bottom, for example, the first flat panel 12 of layer # 1 in fig. 10 overlaps the first circuit layer 1 of layers # 2 and #3 in layer # 2, and the overlapping manner of other first flat panels is the same, which is not described herein again.
In one embodiment, a circuit board is further designed, and the circuit board further includes a second flat panel 13, and the second flat panel 13 is disposed between two adjacent second circuit layers 2.
The second flat panel 13 can be used as a reference plane of the gradual-change signal line 11, a ground hole 0 is formed in the second flat panel 13, and the ground hole is opened in the lamination direction (vertical direction) of the circuit board, so that the placement design of the ground hole on the second flat panel 13 is the same as the placement design of the ground hole on the first circuit layer and the placement design of the ground hole on the second circuit board, as shown in fig. 9, for the schematic diagram of the first flat panel (the structure of the second flat panel 13 is the same as that of the first flat panel 12).
For example, as shown in a schematic diagram of a circuit board shown in fig. 13, layers in which the circuit layers of the circuit board are located are defined from top to bottom in a vertical direction, a layer #1, a layer #2, a layer #3, a layer #4, a layer #5, a layer #6, a layer #7, a layer #8, a layer #9, a layer #10, a layer #11, a layer #12, and a layer #13, and each second flat plate 13 of the first circuit layer 1 on the layer #1 is disposed on the second circuit layer 2 of the adjacent layer # 2; each second flat plate 13 of the first wiring layer 1 on the #5 layer is disposed between the adjacent second wiring layer 2 of the #4 layer and the second wiring layer 2 of the #6 layer; each second flat plate 13 of the first wiring layer 1 on the #9 layer is disposed between the adjacent second wiring layer 2 of the #8 layer and the second wiring layer 2 of the #10 layer; each second flat panel 13 of the first line layer 1 on the #13 layer is disposed under the second line layer 2 of the adjacent #12 layer. Moreover, in this design structure, each gradation signal line may have the vertically adjacent second flat panel as a reference plane, and as shown in fig. 13, the gradation signal line 11 on layer #3 has the second flat panel 13 on layer # 1 or the second flat panel 13 on layer #5 as a reference plane; the gradation signal line 11 on layer #7 has the second flat panel 13 of layer #5 or the second flat panel 13 of layer #9 as a reference plane; the gradation signal line 11 on layer # 11 has the second flat panel 13 of layer #9 or the second flat panel 13 of layer # 13 as a reference plane. The second flat panel is arranged between the second circuit layers which are different in the vertical direction, so that signal crosstalk between different gradient signal lines in the vertical direction can be reduced, and the quality of signal transmission on the circuit board is improved.
In one embodiment, on the basis of the circuit board described in the embodiment of fig. 13, a circuit board is further designed, and at least one third flat panel 14 is further included on the first circuit layer 1 in the circuit board, and the third flat panel 14 is horizontally disposed between two adjacent gradient signal lines 11.
The third flat panel 14 is provided with ground holes, and the ground holes are opened in the lamination direction (vertical direction) of the circuit board, so that the layout design of the ground holes on the third flat panel 14 is the same as the layout design of the ground holes on the first circuit layer and the layout design of the ground holes on the second circuit board, as shown in the schematic diagram of the first flat panel shown in fig. 9 (the structure of the third flat panel 14 is the same as that of the first flat panel 12).
For example, as shown in a schematic diagram of a circuit board shown in fig. 14, layers in which respective circuit layers in the circuit board are located are defined from top to bottom in a vertical direction, a layer #1, a layer #2, a layer #3, a layer #4, a layer #5, a layer #6, a layer #7, a layer #8, a layer #9, a layer #10, a layer #11, a layer #12, and a layer #13, and in a horizontal direction, a third flat panel 14 of a first circuit layer 1 on the layer #3 is disposed between two adjacent gradient signal lines 11 on the same layer; the third flat panel 14 of the first line layer 1 on the #7 layer is disposed between the two gradation signal lines 11 adjacent on the same layer; the third flat panel 14 of the first wiring layer 1 on the #11 layer is disposed between two adjacent gradation signal lines 11 on the same layer; correspondingly, in the vertical direction, a second flat panel 13 is disposed on the first circuit layer 1 on the #1, #5, #9, #13 layers, respectively; in the embodiment, the third flat panel is arranged between different gradient signal lines in the horizontal direction, and the second flat panel is arranged between different second circuit layers in the vertical direction, so that the signal crosstalk between different gradient signal lines in the horizontal direction and the signal crosstalk between different gradient signal lines in the vertical direction can be respectively reduced, and the quality of signal transmission on the circuit board is further improved.
Optionally, on the basis of the circuit board described in the embodiment of fig. 14, a circuit board is further designed, as shown in fig. 15, the position of the third flat plate 14 on each first circuit layer 1 in the circuit board corresponds to the position of the gradually-changed signal line 11 on the adjacent first circuit layer 1.
As in the circuit board shown in fig. 15, for example, the position of the third flat plate 14 on the #3 layer corresponds to the position of the gradation signal line 11 on the first wiring layer 1 of the adjacent #7 layer; the position of one third flat panel 14 on the #7 layer corresponds to the position of the gradation signal line 11 on the first wiring layer 1 of the adjacent # 11 layer, and the position of the other third flat panel 14 on the #7 layer corresponds to the position of the gradation signal line 11 on the first wiring layer 1 of the adjacent # 11 layer. The design forms a circuit board structure in which the gradually-changed signal lines on different layers and the third flat panel are arranged in a staggered mode, and an interlayer reference design scheme is achieved, so that the gradually-changed signal lines on the same layer are far away from each other in the horizontal direction, and the gradually-changed signal lines closer to each other in the vertical direction are located on different layers, and therefore crosstalk between the gradually-changed signal lines is reduced.
In an embodiment, on the basis of the circuit board described in the embodiment of fig. 13, a circuit board is further designed, as shown in fig. 16, and the second circuit layer 2 in the circuit board further includes at least one third flat panel 14, where the third flat panel 14 is horizontally disposed between two adjacent hollow areas 21 on the second circuit layer 2.
The third flat plate 14 can be used as a reference plane of the gradient signal line 11 adjacent to the third flat plate 14 in the vertical direction, and the third flat plate 14 is provided with a ground hole, and since the ground hole is opened in the lamination direction (vertical direction) of the circuit board, the layout design of the ground hole on the third flat plate 14 and the layout design of the ground hole on the first circuit layer are the same as the layout design of the ground hole on the second circuit board, see the schematic diagram of the first flat plate shown in fig. 9 (the third flat plate 14 and the first flat plate 12 have the same structure).
For example, as shown in a schematic circuit board diagram of fig. 16, the layers of the circuit layers in the circuit board are defined from top to bottom in the vertical direction, the layers #1, #2, #3, #4, #5, #6, #7, #8, #9, #10, #11, #12 and #13, and the third flat panel 14 of the second circuit layer 2 on the layer #2 is disposed between two adjacent hollow areas 21 on the same layer in the horizontal direction; the third flat panel 14 of the second circuit layer 2 on the #6 layer is arranged between two adjacent hollowed-out areas 21 on the same layer; the third flat panel 14 of the second circuit layer 2 on the #10 layer is arranged between two adjacent hollowed-out regions 21 on the same layer; correspondingly, in the vertical direction, a second flat panel 13 is disposed on the first circuit layer 1 on the #1, #5, #9, #13 layers, respectively; in the embodiment, the third flat panel is arranged between different hollow areas in the horizontal direction, and the second flat panel is arranged between different second circuit layers in the vertical direction, so that signal crosstalk between different gradually-changed signal lines in the horizontal direction and the vertical direction can be reduced respectively, and the quality of signal transmission on the circuit board is improved.
Those skilled in the art should also appreciate that the embodiments described in this specification are all alternative embodiments and that the acts and modules involved are not necessarily required for this application. In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the above description of the embodiments is only provided to help understand the method and the core concept of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A circuit board, comprising: the circuit comprises at least one first circuit layer and at least one second circuit layer, wherein the first circuit layer and the second circuit layer are arranged at intervals in the vertical direction, and a gradual change signal line is arranged on the first circuit layer;
the second circuit layer comprises a hollow-out area, and the position of the hollow-out area corresponds to the position of the gradient signal line on the adjacent first circuit layer.
2. The circuit board of claim 1, further comprising a plurality of ground holes disposed around the tapered signal lines, wherein a horizontal distance between each ground hole and the tapered signal line decreases as a width of the tapered signal line decreases.
3. The circuit board of claim 2, wherein a shortest distance between a center point of each ground hole and an edge line of the hollow area is less than a preset threshold.
4. The circuit board of claim 3, wherein the ground holes include first ground holes provided at both side regions where the width of the gradation signal line is constant, and second ground holes provided at both side regions where the width of the gradation signal line is varied; the distance between two adjacent first ground holes is greater than the distance between two adjacent second ground holes.
5. The circuit board according to any one of claims 1 to 4, wherein the first circuit layer further comprises at least one first flat plate, and the first flat plate is disposed between two adjacent tapered signal lines in a horizontal direction.
6. The circuit board of claim 5, wherein the first plane plate on each first circuit layer is located at a position corresponding to the location of the tapered signal line on the adjacent first circuit layer.
7. The circuit board according to any one of claims 1 to 4, further comprising a second planar board disposed between two adjacent second circuit layers.
8. The circuit board of claim 7, further comprising at least one third flat panel on the first circuit layer, wherein the third flat panel is disposed between two adjacent gradation signal lines in a horizontal direction.
9. The circuit board of claim 1, wherein the hollowed-out area is U-shaped.
10. The circuit board of claim 9, wherein the bottom of the U-shape is a tri-fold line structure, and the shape of the tri-fold line structure is adapted to the shape of the tapered signal line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111348860.0A CN114205994A (en) | 2021-11-15 | 2021-11-15 | Circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111348860.0A CN114205994A (en) | 2021-11-15 | 2021-11-15 | Circuit board |
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| CN114205994A true CN114205994A (en) | 2022-03-18 |
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| CN202111348860.0A Pending CN114205994A (en) | 2021-11-15 | 2021-11-15 | Circuit board |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2024212473A1 (en) * | 2023-04-14 | 2024-10-17 | 广州广合科技股份有限公司 | Manufacturing method for circuit board, and circuit board |
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| US20040174228A1 (en) * | 2002-12-05 | 2004-09-09 | Hiroshi Kanno | High-frequency circuit and high-frequency package |
| US20070194434A1 (en) * | 2006-02-20 | 2007-08-23 | Chin-Sung Lin | Differential signal transmission structure, wiring board, and chip package |
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