CN114205181A - Closed loop network and automatic routing method thereof - Google Patents
Closed loop network and automatic routing method thereof Download PDFInfo
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- CN114205181A CN114205181A CN202111440919.9A CN202111440919A CN114205181A CN 114205181 A CN114205181 A CN 114205181A CN 202111440919 A CN202111440919 A CN 202111440919A CN 114205181 A CN114205181 A CN 114205181A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/22—Alternate routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/422—Synchronisation for ring networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
- H04L12/437—Ring fault isolation or reconfiguration
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/16—Multipoint routing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/28—Routing or path finding of packets in data switching networks using route fault recovery
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Abstract
The invention discloses a closed loop network and an automatic routing method thereof, comprising n nodes connected end to end; each node consists of an FPGA, m transmitting units and m receiving units; the input ends of the m receiving units form m input ends of the nodes respectively, and the output ends of the m transmitting units form m output ends of the nodes respectively; the output ends of the m receiving units are connected with the input end of the FPGA, and the input ends of the m transmitting units are connected with the output end of the FPGA. Due to the adoption of the mode of automatic selection of link data, when a certain node and a certain loop break down, the system can automatically extract data from other nodes and loops for transmission, and under the limit condition, as long as a smooth link still exists in the system, the data of all nodes in the system can be normally transmitted, so that the stability and reliability of the system are greatly improved.
Description
Technical Field
The invention relates to the technical field of underwater information networks, in particular to a closed loop network and an automatic routing method thereof.
Background
With the development of underwater information networks and national ocean strategies, various underwater detection, acquisition, communication platforms, underwater navigation and countermeasure platforms are built in sequence, and optical fibers are increasingly applied to the underwater information networks due to the advantages of light weight, good confidentiality, large transmission capacity and the like. However, due to the inherent characteristics of the underwater information network, the maintenance cost and difficulty of the underwater information network are much higher than those of ground equipment, even increased by orders of magnitude, and thus, the requirements on the reliability and stability of signals are also increased.
Disclosure of Invention
The invention provides a closed loop network and an automatic routing method thereof aiming at the transmission requirement of an underwater information network with high requirements on signal transmission reliability and stability.
In order to solve the problems, the invention is realized by the following technical scheme:
a closed loop network includes n nodes. Each node consists of an FPGA, m transmitting units and m receiving units; the output ends of the m receiving units are connected with the input end of the FPGA, and the input ends of the m transmitting units are connected with the output end of the FPGA; the inputs of the m receiving units form the m inputs of the node, respectively, and the outputs of the m transmitting units form the m outputs of the node, respectively. The n nodes are connected end to end, namely: 1 st of the 1 st node
Each input terminal is connected with the nth node
An output terminal, the 1 st node
Output terminals are respectively connected with the nth node
An input terminal, the 1 st node
Having an input connected to the 2 nd node
An output terminal, the 1 st node
An output terminal connected to the 2 nd node
An input terminal; the ith node
The input ends are respectively connected with the (i-1) th node
An output terminal, the ith node
The output ends are respectively connected with the (i + 1) th node
An input terminal, an ith node
The input terminal of the first node is connected with the (i-1) th node
An output terminal, the ith node
The output end is connected with the (i + 1) th node
An input terminal. The i is 2,3, …, n-1, n is a positive integer greater than or equal to 2; m is an even number of 2 or more.
In the above scheme, each receiving unit is provided with a serial-to-parallel conversion module and a CDR module; the serial-parallel conversion module is connected with the input end of the CDR module and forms the input end of the receiving unit; the output end of the serial-parallel conversion module forms one path of output end of the receiving unit, and the output end of the CDR module forms the other path of output end of the receiving unit.
In the scheme, a clock transceiving module and a data selection module are arranged in the FPGA; the input end of the clock transceiving module is connected with the output ends of the CDR modules of all receiving units in the node, and the input end of the data selection module is connected with the output ends of the serial-parallel conversion modules of all receiving units in the node; the output end of the data selection module is connected with the input ends of all the transmitting units in the node.
In the scheme, in the same node, the output end of the receiving unit is connected with the input end of the FPGA in a parallel mode, and the input end of the transmitting unit is connected with the output end of the FPGA in a parallel mode.
In the above scheme, between adjacent nodes, the input end of the receiving unit and the output end of the transmitting unit are connected in a serial manner.
The automatic routing method of the closed loop network realized by the closed loop network comprises the following steps:
the receiving unit of the current node divides the signal transmitted by the transmitting unit of the previous node into two paths: one path of signal is recovered by a CDR module of the receiving unit to be a clock and the state of the clock is input to a clock transceiving module of the FPGA; one path of signal recovers data through the serial-parallel conversion module of the receiving unit and the state of the data is transmitted to the data selection module of the FPGA;
the clock transceiving module of the FPGA of the current node selects one clock from all clocks and state information thereof as a working clock of the current node by utilizing a set clock selection strategy for the clocks and the state information thereof sent by all receiving units; and the data selection module of the FPGA of the current node transmits the data and the state information thereof sent by each receiving unit to one receiving unit of the next node from one transmitting unit of the current node by using a set routing strategy.
The preferred clock selection strategy is inverse clock priority and outer ring priority; namely: preferentially selecting a clock of an outer ring link of the inverse clock; secondly, the clock of the inner ring link of the inverse clock; again the clock of the clockwise outer loop link; finally, the clock for the clockwise inner loop link.
The preferred routing strategy is loop-first and same-direction-first, namely: preferentially selecting data which is the same as the signal transmission loop and has the same direction; secondly, data of different loops and the same direction are obtained; the data in the same loop and different directions are obtained again; and finally, the data of different loops and different directions.
Compared with the prior art, the invention has the following characteristics:
1. compared with a point-to-point transmission mode, the method adopts a mode of uploading signals step by step in a closed loop, so that the link bandwidth is utilized to the maximum extent, the requirement of the system on a transmission link is reduced, and the difficulty and the cost of system laying are reduced.
2. Due to the adoption of the mode of automatic selection of link data, when a certain node and a certain loop break down, the system can automatically extract data from other nodes and loops for transmission, and under the limit condition, as long as a smooth link still exists in the system, the data of all nodes in the system can be normally transmitted, so that the stability and reliability of the system are greatly improved.
Drawings
FIG. 1 is a schematic block diagram of a closed loop network;
fig. 2 is a schematic block diagram of a node.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to specific examples.
Referring to fig. 1, a closed loop network includes n end-to-end nodes. Each node comprises m inputs and m outputs. 1 st of the 1 st node
Each input terminal is connected with the nth node
An output terminal, the 1 st node
Output terminals are respectively connected with the nth node
An input terminal, the 1 st node
Having an input connected to the 2 nd node
An output terminal, the 1 st node
An output terminal connected to the 2 nd node
An input terminal; the ith node
The input ends are respectively connected with the (i-1) th node
An output terminal, the ith node
The output ends are respectively connected with the (i + 1) th node
An input terminal, an ith node
The input terminal of the first node is connected with the (i-1) th node
An output terminal, the ith node
The output end is connected with the (i + 1) th node
An input terminal. Between adjacent nodes, the input end of the receiving unit and the output end of the transmitting unit are connected in a serial mode. Wherein i is 2,3, …, n-1, n is a positive integer greater than or equal to 2; m is an even number equal to or greater than 2, and in the present embodiment, n is 20 and m is 4.
Referring to fig. 2, each node is composed of an FPGA, m transmitting units, and m receiving units. The FGPA chip logic unit is larger than 43k, Slice is larger than 6.8k, the number of IO ports is larger than 300, the number of GTP transceivers is larger than 4 pairs, the signal processing capacity is larger than 200MHz, the clock frequency is 30 MHz-150 MHz, and the frequency stability is kept within 10ppm after multi-stage transmission. A serial-parallel conversion module and a CDR (clock recovery) module are arranged in each receiving unit; the serial-parallel conversion module is connected with the input end of the CDR module and forms the input end of the receiving unit; the output end of the serial-parallel conversion module forms one path of output end of the receiving unit, and the output end of the CDR module forms the other path of output end of the receiving unit. A clock transceiving module and a data selection module are arranged in the FPGA; the input end of the clock transceiving module is connected with the output ends of the CDR modules of all receiving units in the node, and the input end of the data selection module is connected with the output ends of the serial-parallel conversion modules of all receiving units in the node; the output end of the data selection module is connected with the input ends of all the transmitting units in the node. In the same node, the output end of the receiving unit is connected with the input end of the FPGA in a parallel mode, and the input end of the transmitting unit is connected with the output end of the FPGA in a parallel mode. The inputs of the m receiving units form the m inputs of the node, respectively, and the outputs of the m transmitting units form the m outputs of the node, respectively.
The method for automatically selecting the route of the closed loop network realized by the closed loop network specifically comprises the following steps:
the receiving unit of the current node divides the signal transmitted by the transmitting unit of the previous node into two paths: one path of signal is recovered by a CDR module of the receiving unit to be a clock and the state of the clock is input to a clock transceiving module of the FPGA; one path of signal recovers data through the serial-parallel conversion module of the receiving unit and the state of the signal is transmitted to the data selection module of the FPGA.
And the clock transceiver module of the FPGA of the current node selects one clock from all the clocks and the state information thereof as the working clock of the current node by utilizing a set clock selection strategy for the clocks and the state information thereof sent by all the receiving units. In the implementation, the clock selection strategy is inverse clock priority and outer ring priority; namely: preferentially selecting a clock of an outer ring link of the inverse clock; secondly, the clock of the inner ring link of the inverse clock; again the clock of the clockwise outer loop link; finally, the clock for the clockwise inner loop link.
And the data selection module of the FPGA of the current node transmits the data and the state information thereof sent by each receiving unit to one receiving unit of the next node from one transmitting unit of the current node by using a set routing strategy. In this implementation, the routing policy is loop-first and syntropy-first, that is: preferentially selecting data which is the same as the signal transmission loop and has the same direction; secondly, data of different loops and the same direction are obtained; the data in the same loop and different directions are obtained again; and finally, the data of different loops and different directions.
Each node automatically selects data and channels according to signals of the front and rear nodes connected with the node, and reliable transmission of the signals is completed. The receiving unit of each node receives a signal sent by a previous node of the current loop, automatically judges the data and the state of the previous node and the current node, and outputs the data and the state information to the FPGA; the FPGA automatically selects data according to a routing strategy and transmits the data to the transmitting unit according to the data of all loops connected with the current node and the state information of the loops, and the transmitting unit is responsible for converting the data transmitted by the FPGA into serial high-speed data and transmitting the serial high-speed data to the next node. Each node receiving unit receives a signal sent by a previous node of a current loop, recovers a clock and a state thereof from data by adopting a CDR technology, and outputs clock and state information thereof to the FPGA; the FPGA automatically selects one clock as a working clock of the node according to the clocks of all loops connected with the current node and the state information of the clocks, and the clock is used as a main clock for subsequent data processing.
The following describes the working process of the present invention in detail with the 2 nd node as the current node:
the signal transmitted in the ring 1 direction of the first receiving unit of the current node is transmitted from one of the transmitting units of the previous node (the 1 st node), and is divided into two paths in the first receiving unit of the current node: one path of the clock is recovered by a CDR module of the first receiving unit and the state of the first clock is input into a clock transceiving module of the FPGA; one path of data is recovered by the serial-parallel conversion module of the first receiving unit to obtain first data and the state of the first data is transmitted to the data selection module of the FPGA.
The signal transmitted in the ring 2 direction of the second receiving unit of the current node is transmitted from one transmitting unit of the previous node (the 1 st node), and is divided into two paths in the second receiving unit of the current node: one path of clock is recovered by a CDR module of the second receiving unit, and a second clock and the state of the second clock are input to a clock transceiver module of the FPGA; one path of data is recovered by the serial-parallel conversion module of the second receiving unit to second data and the state of the second data is transmitted to the data selection module of the FPGA.
The signal transmitted in the ring 3 direction of the third receiving unit of the current node is transmitted from one of the transmitting units of the next node (the 3 rd node), and is divided into two paths in the third receiving unit of the current node: one path of clock is recovered by a CDR module of a third receiving unit and a third clock and the state of the third clock are input into a clock transceiver module of the FPGA; and one path of data is recovered by the serial-parallel conversion module of the third receiving unit to obtain third data and the state of the third data is transmitted to the data selection module of the FPGA.
The signal transmitted in the ring 4 direction of the fourth receiving unit of the current node is transmitted from one of the transmitting units of the next node (the 3 rd node), and is divided into two paths in the fourth receiving unit of the current node: one path of the clock is recovered by a CDR module of the fourth receiving unit, and a fourth clock and the state of the fourth clock are input into a clock transceiving module of the FPGA; and one path of data is recovered by the serial-parallel conversion module of the fourth receiving unit to obtain fourth data and the state of the fourth data is transmitted to the data selection module of the FPGA.
And the clock transceiver module of the FPGA of the current node selects one clock from the 4 clocks and the state information as a working clock of the current node according to the clocks and the state information provided by the 4 receiving units and the set clock selection strategy. The clock is extracted from the data of the previous node in each loop direction and is synchronous with the data of the previous node, and all the link nodes trace back step by step and finally reach the first node, so that the clocks used by all the nodes on the link are synchronous clocks, and the consistency of system clock signals is ensured. The clock selection strategy is: the inverse clock is preferred, and the outer ring is preferred; namely: the counter clock outer loop link clock (loop 1) is preferably selected, followed by the counter clock inner loop clock (loop 2), followed by the clockwise outer loop clock (loop 3), and followed by the clockwise inner loop clock (loop 4).
And the data selection module of the FPGA of the current node selects a loop from the input data to recover the data and transmits the data and the data of the node to one of the transmitting units of the adjacent node in parallel according to the data state information provided by each receiving unit and the set data selection strategy. The transmitting unit receives the parallel data transmitted by the data selection module, completes parallel/serial conversion and 8B/10B coding and then transmits the data to the adjacent node through a high-speed serial port. The signals transmitted by each loop of the current node to the next-level node are related to the routing strategy of the data selection module. The same strategy is adopted for each loop data selection: the data selection refers to the state of the previous link, firstly judges the loop states in four directions (same-direction same loop sign S1, same-direction different loop signs S3, different-direction same loop sign S2, namely different-direction different loop signs S4) connected with the node, and selects the data to be relayed to the next node according to the different link states. The data selection policy is: loop first, syntropy first, i.e.: the data with the same direction and the same direction as the signal transmission loop are preferentially selected, then the data with different loops and the same direction, then the data with the same loop and the different direction, and finally the data with different loops and different directions are selected, namely the priority is S1, S3, S2 and S4. And after the data selection is finished, packaging the data collected by the local terminal and the data together and sending the data from four directions. And the reliable transmission of the acquired data signals and the state signals of each node is completed by adopting a step-by-step uploading mode. The routing strategy has the advantages that under the condition that the four loops of the system are normal, the four loops are identical in transmission, but the transmission links of the four loops are not crossed, and the data of the four nodes can be checked and compared by the last data aggregation unit, so that the subsequent data analysis is facilitated.
It should be noted that, although the above-mentioned embodiments of the present invention are illustrative, the present invention is not limited thereto, and thus the present invention is not limited to the above-mentioned embodiments. Other embodiments, which can be made by those skilled in the art in light of the teachings of the present invention, are considered to be within the scope of the present invention without departing from its principles.
Claims (8)
1. A closed loop network is characterized by comprising n nodes; each node consists of an FPGA, m transmitting units and m receiving units; the output ends of the m receiving units are connected with the input end of the FPGA, and the input ends of the m transmitting units are connected with the output end of the FPGA; the input ends of the m receiving units form m input ends of the nodes respectively, and the output ends of the m transmitting units form m output ends of the nodes respectively;
the n nodes are connected end to end, namely: 1 st of the 1 st node
Each input terminal is connected with the nth node
An output terminal, the 1 st node
Output terminals are respectively connected with the nth node
An input terminal, the 1 st node
Having an input connected to the 2 nd node
An output terminal, the 1 st node
An output terminal connected to the 2 nd node
An input terminal; the ith node
An input terminalThe (i) th node is connected with the (1) th node
An output terminal, the ith node
The output ends are respectively connected with the (i + 1) th node
An input terminal, an ith node
The input terminal of the first node is connected with the (i-1) th node
An output terminal, the ith node
The output end is connected with the (i + 1) th node
An input terminal;
the i is 2,3, …, n-1, n is a positive integer greater than or equal to 2; m is an even number of 2 or more.
2. A closed loop network as claimed in claim 1, wherein each receiving unit has a serial-to-parallel conversion module and a CDR module; the serial-parallel conversion module is connected with the input end of the CDR module and forms the input end of the receiving unit; the output end of the serial-parallel conversion module forms one path of output end of the receiving unit, and the output end of the CDR module forms the other path of output end of the receiving unit.
3. The closed loop network of claim 2, wherein the FPGA is provided with a clock transceiver module and a data selection module; the input end of the clock transceiving module is connected with the output ends of the CDR modules of all receiving units in the node, and the input end of the data selection module is connected with the output ends of the serial-parallel conversion modules of all receiving units in the node; the output end of the data selection module is connected with the input ends of all the transmitting units in the node.
4. The closed-loop network and the automatic routing method thereof as claimed in claim 1, wherein in the same node, the output terminal of the receiving unit is connected with the input terminal of the FPGA in a parallel manner, and the input terminal of the transmitting unit is connected with the output terminal of the FPGA in a parallel manner.
5. A closed loop network as claimed in claim 1, wherein the input of the receiving unit is connected in series with the output of the transmitting unit between adjacent nodes.
6. A method for automatic routing of a closed loop network implemented by the closed loop network of claim 1, comprising the steps of:
the receiving unit of the current node divides the signal transmitted by the transmitting unit of the previous node into two paths: one path of signal is recovered by a CDR module of the receiving unit to be a clock and the state of the clock is input to a clock transceiving module of the FPGA; one path of signal recovers data through the serial-parallel conversion module of the receiving unit and the state of the data is transmitted to the data selection module of the FPGA;
the clock transceiving module of the FPGA of the current node selects one clock from all clocks and state information thereof as a working clock of the current node by utilizing a set clock selection strategy for the clocks and the state information thereof sent by all receiving units; and the data selection module of the FPGA of the current node transmits the data and the state information thereof sent by each receiving unit to one receiving unit of the next node from one transmitting unit of the current node by using a set routing strategy.
7. The method of claim 6, wherein the clock selection strategy is inverse clock first and outer loop first; namely: preferentially selecting a clock of an outer ring link of the inverse clock; secondly, the clock of the inner ring link of the inverse clock; again the clock of the clockwise outer loop link; finally, the clock for the clockwise inner loop link.
8. The method as claimed in claim 6, wherein the routing strategy is loop priority and same direction priority, that is: preferentially selecting data which is the same as the signal transmission loop and has the same direction; secondly, data of different loops and the same direction are obtained; the data in the same loop and different directions are obtained again; and finally, the data of different loops and different directions.
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