CN114189247A - Reference voltage buffer for differential successive approximation register type ADC - Google Patents
Reference voltage buffer for differential successive approximation register type ADC Download PDFInfo
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- CN114189247A CN114189247A CN202111481568.6A CN202111481568A CN114189247A CN 114189247 A CN114189247 A CN 114189247A CN 202111481568 A CN202111481568 A CN 202111481568A CN 114189247 A CN114189247 A CN 114189247A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
Abstract
The invention discloses a reference voltage buffer for a differential successive approximation register type ADC (analog-to-digital converter), which comprises a first voltage buffer capable of being modified and adjusted, a second voltage buffer for generating a positive reference voltage Vrp and a third voltage buffer for generating a common-mode voltage Vcm, wherein a band-gap reference voltage is output to the input end of the second voltage buffer and the input end of the third voltage buffer through the first voltage buffer. The first voltage buffer can change the output voltage thereof through the trimming resistor R1, so as to trim the output voltage of the second voltage buffer; the third voltage buffer enables fast building-up of Vcm at very low bias currents by speeding up the pull-down of the high voltage detector HD. The requirements of the first voltage buffer on low power consumption are consistent with the requirements of accurate adjustment; meanwhile, the second voltage buffer of the present invention requires an accurate output voltage and the third voltage buffer does not require an accurate output voltage. The invention can well meet the requirement of the differential SAR type ADC on the on-chip reference voltage buffer.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a buffer for providing a series of reference voltages for a high-precision fully-differential successive approximation register type ADC.
Background
Analog-to-Digital Converter (ADC) is a bridge between the real world and the Digital world, and a Successive Approximation Register (SAR) type structure is very suitable for realizing an ADC with medium speed and medium and high precision, and has the advantages of compact structure, low power consumption, capability of benefiting from the progress of a manufacturing process, and the like.
Fig. 1 to 4 illustrate the quantization process of the differential SAR ADC by taking 3 bits as an example, where fig. 1 shows the sampling phase state, fig. 2 shows b2 obtained by the first comparison, fig. 3 shows b1 obtained by the second comparison, and fig. 4 shows b0 obtained by the third comparison. The capacitor array Digital-to-Analog Converter (DAC) architecture is generally referred to as a DAC based on common-mode voltage in academic, and has the advantages of low switching power consumption, good matching performance, small comparator detuning and the like. How to design the buffer to provide the three reference voltages (positive reference voltage Vrp, negative reference voltage Vrn, common mode voltage Vcm) required by such a differential structure with the least power consumption is a key issue when designing a differential SAR-type ADC, and therefore, the power consumption of the reference voltage buffer tends to occupy most of the overall power consumption of the SAR-type ADC. In a single power supply system, the reference ground is usually chosen to be a negative reference voltage Vrn, and then the reference voltage buffer needs to provide two voltages, namely a positive reference voltage Vrp and a common mode voltage Vcm.
Voltage series negative feedback is a basic approach to implement a reference voltage buffer. First, the loop gain must be high enough to overcome the static output voltage error caused by the variation of the error amplifier gain due to process, voltage, temperature variations; secondly, in the worst case scenario, the buffer must be able to complete the setup of the output voltage within a specified time, and we generally use a dynamic error smaller than half of the minimum resolution Bit (LSB) voltage as the standard for the setup completion. In addition, of the two reference voltages required by the SAR ADC, the positive reference voltage Vrp must have high absolute precision to make the quantization range consistent with the design target, and the common mode voltage Vcm has no requirement for absolute precision because it only has the function of defining the common mode level of the output voltage of the capacitor array DAC.
Disclosure of Invention
The invention aims to provide a reference voltage buffer for a differential successive approximation register type ADC, which has the characteristics of good transient characteristic, low power consumption and easiness in trimming.
The technical scheme of the invention is as follows: a reference voltage buffer for a differential successive approximation register ADC comprises a first voltage buffer capable of being modified and adjusted, a second voltage buffer generating a positive reference voltage Vrp and a third voltage buffer generating a common-mode voltage Vcm, wherein a band-gap reference voltage is output to the input end of the second voltage buffer and the input end of the third voltage buffer through the first voltage buffer;
the first voltage buffer comprises a first error amplifier A1, a first PMOS tube P1, a first resistor R1 and a second resistor R2;
the second voltage buffer comprises a second error amplifier A2, a second PMOS tube P2, a third resistor R3 and a fourth resistor R4;
the third voltage buffer includes a third error amplifier a3, a first NMOS transistor N1, a second NMOS transistor N2, a first current source I1, and a high voltage detector HD.
In the above technical solution, the bias current of the first voltage buffer is smaller than the bias current of the third voltage buffer and is smaller than the bias current of the second voltage buffer.
In the above technical solution, an inverting input terminal of the first error amplifier a1 is electrically connected to the bandgap reference voltage, a non-inverting input terminal is electrically connected to one end of the first resistor R1 and one end of the second resistor R2, and an output terminal is electrically connected to the gate of the PMOS transistor P1;
the source electrode of the PMOS tube P1 is electrically connected to a power supply VDD, and the drain electrode is respectively electrically connected to the other end of the second resistor R2, the inverting input end of the second error amplifier A2, the non-inverting input end of the third error amplifier A3 and the reference input end of the high voltage detector HD;
the other end of the first resistor R1 is grounded;
the non-inverting input end of the second error amplifier a2 is electrically connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively, and the output end is electrically connected to the gate of the PMOS transistor P2;
the source electrode of the PMOS tube P2 is electrically connected to a power supply VDD, and the drain electrode of the PMOS tube P2 is respectively and electrically connected to the other end of the fourth resistor R4 and an output power supply end Vrp;
the other end of the third resistor R3 is grounded;
the inverting input end of the third error amplifier a3 is electrically connected to the detection input end of the high voltage detector HD and the drain of the NMOS transistor N2, respectively, and is grounded through the bias current source IB 1, and the output end is electrically connected to the gate of the NMOS transistor N1;
the detection output end of the high-voltage detector HD is electrically connected to the grid electrode of an NMOS tube N2, and the source electrode of the NMOS tube N2 is grounded;
the drain of the NMOS transistor N1 is electrically connected to the power supply VDD, and the source is electrically connected to the output power terminal Vcm and grounded via the bias current source IB 1.
In the above technical solution, the first resistor R1 is a trimmable resistor whose resistance value can be trimmed by a control word.
In the above technical solution, the high voltage detector HD comprises a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N3, an NMOS transistor N4, and a bias current source I2, wherein,
the source electrode of the PMOS tube P3 is electrically connected to a power supply voltage VDD through a bias current source I2, the grid electrode is electrically connected to the reference input end of the high-voltage detector HD, and the drain electrode is respectively and electrically connected to the drain electrode of the NMOS tube N3 and the output end of the high-voltage detector HD;
the source electrode of the PMOS tube P4 is electrically connected to a power supply voltage VDD through a bias current source I2, the grid electrode is electrically connected to the detection input end of the high-voltage detector HD, and the drain electrode is respectively and electrically connected to the drain electrode and the grid electrode of an NMOS tube N4 and the grid electrode of an NMOS tube N3;
the source electrode of the NMOS transistor N3 is grounded;
the source of the NMOS transistor N4 is grounded.
In the above technical solution, the sizes of the third NMOS transistor N3 and the fourth NMOS transistor N4 are matched with each other, and the size ratio of the third NMOS transistor N3 to the fourth NMOS transistor N4 is 3: 1.
In the above technical solution, the high voltage detector HD is configured to output a high level when detecting that the voltage at the detection input terminal is higher than the voltage at the reference input terminal by more than a predetermined ratio.
In the above technical solution, the preset proportion is 20%.
The invention has the advantages that:
1. the resistance values of the first resistor R1 and the second resistor R2 are very large, and the output voltage Vrp with high absolute accuracy can be obtained easily by digitally trimming the resistance value of the first resistor R1;
2. the first voltage buffer and the second voltage buffer both adopt a traditional two-stage amplification structure and a Miller frequency compensation method, and have the advantage of good transient characteristic;
3. the high voltage detector HD of the present invention can greatly reduce the bias current allocated to the first current source I1 in the third voltage buffer because the high voltage detector HD temporarily turns on the NMOS transistor N2 to increase the pull-down speed when the common mode voltage Vcm is connected to a higher level.
Drawings
The invention is further described with reference to the following figures and examples:
fig. 1 to 4 are schematic diagrams of quantization processes of differential SAR ADC in the related art.
FIG. 5 is a circuit diagram of a reference voltage buffer according to the present invention.
Fig. 6 is a circuit configuration diagram of the high voltage detector HD of the present invention.
FIG. 7 shows the results of the stability simulation of the present invention under a 55nm CMOS process (3.3V supply voltage).
FIG. 8 shows the transient response simulation results of the reference voltage buffer of the present invention buffered from 2.5V and 0V to 1.25V, respectively, under a 55nm CMOS process (3.3V supply voltage).
FIG. 9 is a partially enlarged view of the transient response simulation results of the reference voltage buffer of the present invention buffered from 2.5V and 0V to 1.25V, respectively, under a 55nm CMOS process (3.3V supply voltage).
FIG. 10 is a graph comparing the output voltage transient simulation results of the present invention and the conventional reference voltage buffer.
Detailed Description
Example (b):
referring to fig. 5, the present embodiment provides a reference voltage buffer for a differential successive approximation register ADC, including a first voltage buffer capable of being modified and adjusted, a second voltage buffer generating a positive reference voltage Vrp, and a third voltage buffer generating a common mode voltage Vcm, wherein a bandgap reference voltage is output to an input terminal of the second voltage buffer and an input terminal of the third voltage buffer through the first voltage buffer;
the first voltage buffer comprises a first error amplifier A1, a first PMOS tube P1, a first resistor R1 and a second resistor R2;
the second voltage buffer comprises a second error amplifier A2, a second PMOS tube P2, a third resistor R3 and a fourth resistor R4;
the third voltage buffer includes a third error amplifier a3, a first NMOS transistor N1, a second NMOS transistor N2, a first current source I1, and a high voltage detector HD.
In one embodiment, the bias current of the first voltage buffer is less than the bias current of the third voltage buffer is less than the bias current of the second voltage buffer.
In one embodiment, the inverting input terminal of the first error amplifier a1 is electrically connected to the bandgap reference voltage, the non-inverting input terminal is electrically connected to one end of the first resistor R1 and one end of the second resistor R2, and the output terminal is electrically connected to the gate of the PMOS transistor P1;
the source electrode of the PMOS tube P1 is electrically connected to a power supply VDD, and the drain electrode is respectively electrically connected to the other end of the second resistor R2, the inverting input end of the second error amplifier A2, the non-inverting input end of the third error amplifier A3 and the reference input end of the high voltage detector HD;
the other end of the first resistor R1 is grounded;
the non-inverting input end of the second error amplifier a2 is electrically connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively, and the output end is electrically connected to the gate of the PMOS transistor P2;
the source electrode of the PMOS tube P2 is electrically connected to a power supply VDD, and the drain electrode of the PMOS tube P2 is respectively and electrically connected to the other end of the fourth resistor R4 and an output power supply end Vrp;
the other end of the third resistor R3 is grounded;
the inverting input end of the third error amplifier a3 is electrically connected to the detection input end of the high voltage detector HD and the drain of the NMOS transistor N2, respectively, and is grounded through the bias current source IB 1, and the output end is electrically connected to the gate of the NMOS transistor N1;
the detection output end of the high-voltage detector HD is electrically connected to the grid electrode of an NMOS tube N2, and the source electrode of the NMOS tube N2 is grounded;
the drain of the NMOS transistor N1 is electrically connected to the power supply VDD, and the source is electrically connected to the output power terminal Vcm and grounded via the bias current source IB 1.
In one embodiment, the first resistor R1 is a trimmable resistor whose resistance can be trimmed by a control word.
Referring to fig. 6, in one embodiment, the high voltage detector HD comprises a PMOS transistor P3, a PMOS transistor P4, an NMOS transistor N3, an NMOS transistor N4, and a bias current source I2, wherein,
the source electrode of the PMOS tube P3 is electrically connected to a power supply voltage VDD through a bias current source I2, the grid electrode is electrically connected to the reference input end of the high-voltage detector HD, and the drain electrode is respectively and electrically connected to the drain electrode of the NMOS tube N3 and the output end of the high-voltage detector HD;
the source electrode of the PMOS tube P4 is electrically connected to a power supply voltage VDD through a bias current source I2, the grid electrode is electrically connected to the detection input end of the high-voltage detector HD, and the drain electrode is respectively and electrically connected to the drain electrode and the grid electrode of an NMOS tube N4 and the grid electrode of an NMOS tube N3;
the source electrode of the NMOS transistor N3 is grounded;
the source of the NMOS transistor N4 is grounded.
In one embodiment, the sizes of the third NMOS transistor N3 and the fourth NMOS transistor N4 are matched, and the size ratio of the third NMOS transistor N3 to the fourth NMOS transistor N4 is 3: 1.
In one embodiment, the high voltage detector HD is configured to output a high level when detecting that the voltage at the detection input terminal is higher than the voltage at the reference input terminal by more than a predetermined ratio.
In one embodiment, the preset ratio is 20%.
The advantages of the present invention will be described in detail with reference to the accompanying drawings
Referring to fig. 7, the loop gain bandwidth product of the reference voltage buffer of the present invention is 80kHz, the 0dB bandwidth is 47MHz, the phase margin is 80 degrees, and the loop stability is good.
Referring to fig. 8, which is a diagram showing a simulation result of an output voltage transient of the reference voltage buffer, considering the setup time of the comparator in the ADC, the reference voltage needs to be buffered to a stable 1.25V within 250ns, and it can be seen that the reference voltage buffer of the present invention can achieve a stable output within 100 ns.
Referring to fig. 9, which is a partial enlarged view of the simulation result of the output voltage, it can be seen that the lower overshoot voltage and the upper overshoot voltage can be restored to within a range of ± 0.5LSB (i.e., 1.2497V to 1.2503V) within 58ns and 52ns, respectively.
Referring to fig. 10, comparing the transient simulation results of the output voltage of the present invention with the transient simulation results of the output voltage of the conventional reference voltage buffer, it can be seen that the conventional reference voltage buffer requires 160ns to complete the setup, but the present invention controls N2 to be turned on by detecting the output voltage by the high voltage detector HD, thereby greatly increasing the pull-down speed and shortening the setup time to 52 ns.
It should be understood that the above-mentioned embodiments are only illustrative of the technical concepts and features of the present invention, and are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and not to limit the scope of the present invention. All modifications made according to the spirit of the main technical scheme of the invention are covered in the protection scope of the invention.
Claims (8)
1. A reference voltage buffer for a differential successive approximation register ADC, characterized by: the band gap reference voltage generating circuit comprises a first voltage buffer capable of being modified and adjusted, a second voltage buffer generating a positive reference voltage Vrp and a third voltage buffer generating a common mode voltage Vcm, wherein a band gap reference voltage is output to the input end of the second voltage buffer and the input end of the third voltage buffer through the first voltage buffer;
the first voltage buffer comprises a first error amplifier A1, a first PMOS tube P1, a first resistor R1 and a second resistor R2;
the second voltage buffer comprises a second error amplifier A2, a second PMOS tube P2, a third resistor R3 and a fourth resistor R4;
the third voltage buffer includes a third error amplifier a3, a first NMOS transistor N1, a second NMOS transistor N2, a first current source I1, and a high voltage detector HD.
2. The reference voltage buffer for a differential successive approximation register ADC according to claim 1, wherein: the bias current of the first voltage buffer is smaller than the bias current of the third voltage buffer and is smaller than the bias current of the second voltage buffer.
3. The reference voltage buffer for a differential successive approximation register ADC according to claim 1, wherein: the inverting input end of the first error amplifier A1 is electrically connected to the bandgap reference voltage, the non-inverting input end is electrically connected to one end of the first resistor R1 and one end of the second resistor R2, and the output end is electrically connected to the gate of the PMOS transistor P1;
the source electrode of the PMOS tube P1 is electrically connected to a power supply VDD, and the drain electrode is respectively electrically connected to the other end of the second resistor R2, the inverting input end of the second error amplifier A2, the non-inverting input end of the third error amplifier A3 and the reference input end of the high voltage detector HD;
the other end of the first resistor R1 is grounded;
the non-inverting input end of the second error amplifier a2 is electrically connected to one end of the third resistor R3 and one end of the fourth resistor R4, respectively, and the output end is electrically connected to the gate of the PMOS transistor P2;
the source electrode of the PMOS tube P2 is electrically connected to a power supply VDD, and the drain electrode of the PMOS tube P2 is respectively and electrically connected to the other end of the fourth resistor R4 and an output power supply end Vrp;
the other end of the third resistor R3 is grounded;
the inverting input end of the third error amplifier a3 is electrically connected to the detection input end of the high voltage detector HD and the drain of the NMOS transistor N2, respectively, and is grounded through the bias current source IB 1, and the output end is electrically connected to the gate of the NMOS transistor N1;
the detection output end of the high-voltage detector HD is electrically connected to the grid electrode of an NMOS tube N2, and the source electrode of the NMOS tube N2 is grounded;
the drain of the NMOS transistor N1 is electrically connected to the power supply VDD, and the source is electrically connected to the output power terminal Vcm and grounded via the bias current source IB 1.
4. The reference voltage buffer for a differential successive approximation register ADC according to claim 1, wherein: the first resistor R1 is a tunable resistor whose resistance can be modified by a control word.
5. The reference voltage buffer for a differential successive approximation register ADC according to claim 1, wherein: the high voltage detector HD comprises a PMOS tube P3, a PMOS tube P4, an NMOS tube N3, an NMOS tube N4 and a bias current source I2, wherein,
the source electrode of the PMOS tube P3 is electrically connected to a power supply voltage VDD through a bias current source I2, the grid electrode is electrically connected to the reference input end of the high-voltage detector HD, and the drain electrode is respectively and electrically connected to the drain electrode of the NMOS tube N3 and the output end of the high-voltage detector HD;
the source electrode of the PMOS tube P4 is electrically connected to a power supply voltage VDD through a bias current source I2, the grid electrode is electrically connected to the detection input end of the high-voltage detector HD, and the drain electrode is respectively and electrically connected to the drain electrode and the grid electrode of an NMOS tube N4 and the grid electrode of an NMOS tube N3;
the source electrode of the NMOS transistor N3 is grounded;
the source of the NMOS transistor N4 is grounded.
6. The reference voltage buffer for a differential successive approximation register ADC according to claim 5, wherein: the sizes of the third NMOS transistor N3 and the fourth NMOS transistor N4 are matched, and the size ratio of the third NMOS transistor N3 to the fourth NMOS transistor N4 is 3: 1.
7. The reference voltage buffer for a differential successive approximation register ADC according to claim 5, wherein: the high voltage detector HD is configured to output a high level when detecting that the voltage at the detection input terminal is higher than the voltage at the reference input terminal by more than a predetermined ratio.
8. The reference voltage buffer for a differential successive approximation register ADC according to claim 7, wherein: the preset proportion is 20%.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202111481568.6A CN114189247A (en) | 2021-12-07 | 2021-12-07 | Reference voltage buffer for differential successive approximation register type ADC |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111481568.6A CN114189247A (en) | 2021-12-07 | 2021-12-07 | Reference voltage buffer for differential successive approximation register type ADC |
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| CN114189247A true CN114189247A (en) | 2022-03-15 |
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| CN202111481568.6A Pending CN114189247A (en) | 2021-12-07 | 2021-12-07 | Reference voltage buffer for differential successive approximation register type ADC |
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