CN114189160A - Light-load conduction control method and circuit for clamp tube in active clamp flyback topology - Google Patents
Light-load conduction control method and circuit for clamp tube in active clamp flyback topology Download PDFInfo
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
- H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
Abstract
The invention relates to the technical field of active clamp flyback control, and discloses a light-load conduction control method for a clamp tube in an active clamp flyback topology. According to the invention, the clamp tube is controlled to be conducted twice in one period, a certain degree of negative current is generated twice, and proper conduction time is searched for the first time, so that the second conduction duration is determined to be relatively accurate, the problem that the conduction time of the clamp tube is too short or too long is effectively avoided, zero voltage conduction under light load is accurately realized, and the conduction loss is effectively reduced.
Description
Technical Field
The invention relates to the technical field of active clamp flyback control, in particular to a light-load conduction control method and circuit for a clamp tube in an active clamp flyback topology.
Background
The Active Clamp Flyback (ACF) can realize the recovery of leakage inductance energy and the zero voltage conduction (ZVS) of a primary power device, thereby effectively improving the system efficiency and reducing the conduction loss. An active clamp flyback topology is shown in fig. 1, where LM and Lk respectively represent an equivalent excitation inductor and a leakage inductor of a transformer, C01 is a clamp capacitor, QP0 and QA0 are a main power tube and a clamp tube, respectively, Sp0 and Sa0 are control signals of the main power tube and the clamp tube, and zero-voltage turn-on of a primary side main power tube can be realized by alternately turning on QP0 and QA 0.
Referring to fig. 2, an ideal operating waveform of the active clamp flyback topology is shown, Vds represents the drain voltage of the main power transistor QP0 in fig. 1, Sa represents the conduction control signal of the clamp transistor, Sp represents the conduction control signal of the main power transistor, and ILM represents the current waveform flowing through the excitation inductor LM in fig. 1. And the main power tube is turned off at the time of tc0, after a certain dead time, the voltage on the clamping capacitor reaches the maximum value at the time of tc1, the current on the excitation inductor drops to 0 at the time of tc2, then the drain-source voltage of the main power tube starts to resonate until the time of tc3, the clamping tube QA0 is turned on again for a period of time to the time of tc4, the duration time is Ta0, and the current direction of the excitation inductor is opposite at the period of time. At the time tc4, the clamp tube is turned off, then after a certain time, Vds is discharged to 0 by negative current, and zero voltage conduction of the main power tube is realized by turning on the main power tube at the time tc 5.
In the prior art, the clamp is only turned on for a short time at tc3 shown in fig. 2, and the on time is often fixed, which has two possibilities: one is that the conduction time is too short, in which case the negative current generated is not sufficient and Vds often cannot be bled to 0. Referring to fig. 3, at time te3, the clamp tube is only conducting for a short time, i.e. Ta0 time is shorter than the ideal case shown in fig. 2, at which time Vds has not yet fully discharged to 0, at time te5 the main tube is conducting, at which time Vds at the moment of conducting is fully discharged to 0; in another case, the set on time is too long, and as shown in fig. 4, Ta0 is too long, which results in a fast Vds drop rate and discharges to 0 within td4 and td5, and in this case, the generated negative current is too large, which may cause a problem of potential power transmission instability.
Disclosure of Invention
The invention aims to provide a light-load conduction control method and a light-load conduction control circuit for a clamp tube in an active clamp flyback topology, and solves the problems in the prior art.
In order to achieve the purpose, the invention provides the following technical scheme: a light-load conduction control method for a clamp tube in an active clamp flyback topology comprises an active clamp flyback circuit and a light-load conduction control circuit, wherein the light-load conduction control circuit comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit, the detection circuit and the driving unit are connected with the active clamp flyback circuit, and the control method specifically comprises the following steps:
the first step is as follows: the detection circuit detects the follow current time of the active clamp flyback circuit in a light-load steady state and sets the time as initial conduction time and first conduction time;
the second step is that: the first conduction time control module outputs an initial conduction control signal to the clamping tube through the driving unit according to first conduction time set by the detection circuit, the clamping tube is conducted, the detection circuit detects whether the drain-source voltage of the main power tube is reduced to 0 within a certain time, and according to the result, the first conduction time is reset or second conduction time is set;
the third step: the second conduction time control module outputs two conduction control signals to the clamping tube through the driving unit according to the first conduction time and the second conduction time fed back by the first conduction time control module and the detection circuit, and meanwhile, the next main power tube is started, and the next period starts;
the fourth step: the third step is performed periodically.
In a preferred embodiment of the present invention, in the second step, the detecting circuit detects whether the drain-source voltage of the main power transistor drops to 0 within a certain time, and the specific process of resetting the first on-time or the second on-time according to the result is as follows: the detection circuit detects whether the drain-source voltage of the main power tube is reduced to 0 within a short set time after the clamping tube is conducted for the first time, if not, conduction of the next period is carried out, the duration time of the first conduction of the clamping tube in the next period is increased by a certain time delay, and the time is set as the first conduction time of the next period; if the current value is decreased to 0, the difference between the first conduction time and the initial conduction time in the period, namely the time difference between the moment when the exciting current is decreased to 0 in the first conduction in the period and the initial value of the first conduction time is locked, and the time difference is set as the second conduction time.
As a preferred embodiment of the present invention, in the third step, the driving unit outputs two turn-on control signals to the clamp transistor, so that the clamp transistor is turned on after the main power transistor is turned off and before the main power transistor is turned on next time, and the two turn-on time periods are the first turn-on time and the second turn-on time, respectively.
In a preferred embodiment of the present invention, in the third step, the magnitude of the negative current generated by the first conduction and the second conduction of the clamping tube is equal, and the duration of the negative current is the same.
A light-load conduction control circuit of a clamp tube in an active clamp flyback topology is applied to a light-load conduction control method of the clamp tube in the active clamp flyback topology and comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit.
As a preferred embodiment of the present invention, an output end of the detection circuit is connected to an input end of a first on-time control module, output ends of the first on-time control module and the detection circuit are both connected to an input end of a second on-time control module, and output ends of the first on-time control module and the second on-time control module are both connected to an input end of the driving unit.
Compared with the prior art, the invention provides a light-load conduction control method and a light-load conduction control circuit for a clamp tube in an active clamp flyback topology, which have the following beneficial effects:
according to the light-load conduction control method and the light-load conduction control circuit for the clamp tube in the active clamp flyback topology, the clamp tube is controlled to be conducted twice in one period, negative currents with a certain degree are generated twice, proper conduction time is searched for the first time, so that the second conduction duration is determined to be relatively accurate, the problem that the conduction time of the clamp tube is too short or too long is effectively solved, zero voltage conduction under light load is accurately achieved, and the conduction loss is effectively reduced.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic structural diagram of an active clamp flyback topology;
fig. 2 is a waveform diagram of active clamp flyback operation;
fig. 3 is a working waveform diagram of the active clamp flyback clamp tube when the conduction time is short;
fig. 4 is a working waveform diagram of the active clamp flyback clamp tube when the conduction time is too long;
FIG. 5 is a waveform of the operation of the present invention during one cycle of stable operation;
FIG. 6 is a waveform diagram of the operation of the clamp according to the present invention at different turn-off times after the clamp is turned on for the first time;
FIG. 7 is a waveform illustrating the operation of the Ta adjustment stage according to the present invention;
FIG. 8 is a system block diagram of a light-load conduction control circuit of the clamp tube according to the present invention;
FIG. 9 is a circuit diagram of the detection circuit of the present invention;
FIG. 10 is a circuit diagram of a first on-time control module according to the present invention
FIG. 11 is a circuit diagram of a second on-time control module according to the present invention
FIG. 12 is a waveform diagram of the related signals of the detection circuit of the present invention
FIG. 13 is a circuit diagram of a driving circuit according to the present invention.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
Referring to fig. 1-13, the present invention provides a technical solution: a light-load conduction control method for a clamp tube in an active clamp flyback topology comprises an active clamp flyback circuit and a light-load conduction control circuit, wherein the light-load conduction control circuit is connected with the active clamp flyback circuit and comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit, the detection circuit and the driving unit are connected with the active clamp flyback circuit, and the control method specifically comprises the following steps:
the first step is as follows: the detection circuit detects the freewheeling time Tdis of the active clamp flyback circuit in a light-load steady state, and sets the freewheeling time Tdis as initial conduction time Tdis and first conduction time, the first conduction time is the same as the initial conduction time Tdis, and the initial conduction time Tdis is used in the second step to set Ta;
as shown in fig. 5, the freewheeling time Tdis starts from an extremely short dead time after the main power tube is turned off and ends at the time when the primary excitation inductor current drops to 0;
the second step is that: the first conduction time control module outputs an initial conduction control signal to the clamping tube through the driving unit according to first conduction time (the first conduction time is freewheeling time Tdis when the detection circuit detects the light-load steady state of the active clamping flyback circuit) set by the detection circuit, the clamping tube is conducted, the detection circuit detects whether the drain-source voltage of the main power tube is reduced to 0 within a certain time, and according to the result, the first conduction time is reset or second conduction time Ta is set;
the third step: the second conduction time control module outputs two conduction control signals to the clamping tube through the driving unit according to the first conduction time and the second conduction time fed back by the first conduction time control module and the detection circuit, so that the clamping tube is conducted after the main power tube is turned off and before the main power tube is turned on next time, the two conduction time periods are respectively the first conduction time (the sum of the second conduction time Ta and the initial conduction time Tdis) and the second conduction time Ta, the main power tube is turned on next time, and the next period starts;
as shown in fig. 5, according to Ta information obtained by first turning on of the clamp, the clamp is controlled to be turned on for the second time at time t5 and lasts for Ta time to t6, and the clamp is turned off at time t6, then Vds falls to 0 after the same Td time as the previous turning on, and at this time, the main power transistor is turned on, and zero voltage turning on of the main power transistor is realized because Vds has already been discharged to 0;
the fourth step: the third step is carried out periodically;
as shown in fig. 7, fig. 7 is a working waveform of the Ta adjustment phase of the present invention, the waveform shown in fig. 7 includes three adjustment cycles and a stable cycle, the subsequent waveform will be the same as the waveform of the stable cycle, the first cycle, the clamp is turned on at time t01, turned off at time t02, and there is no negative current when turned off, so the voltage at the lowest point of Vds resonance is not different from that of the ordinary flyback converter, after Tdis is detected, the second cycle, the clamp is turned on at time t04, the on duration is increased by a short time on the basis of Tdis, and turned off at time t07, and the generated negative current will discharge the voltage of Vds to a lower potential than the lowest point of the first cycle, but because the negative current is not negative enough, the lowest point of Vds is still greater than 0; and in the third period, the conduction time of the clamp is continuously increased, the clamp is conducted until the time t13 at the time t11, the negative current generated in the third period is enough to discharge the charges on the drain-source parasitic capacitor of the main power tube, therefore, at the time t14, Vds is discharged to 0, the time difference from t12 to t13 is counted and locked to Ta, the clamp is controlled to be conducted at the time t15 of the current period and lasts for the time Ta to t16, and the clamp is conducted twice in each period after: the first conduction time is Tdis + Ta, the second conduction time is Ta, and the time of Ta represents proper negative current for discharging charges on a drain-source parasitic capacitor of the main power tube.
In this embodiment, in the second step, the specific process of detecting whether the drain-source voltage of the main power transistor drops to 0 within a certain time by the detection circuit and resetting the first on-time or the second on-time according to the result includes: the detection circuit detects whether the drain-source voltage of the main power tube is reduced to 0 within a short set time after the clamping tube is conducted for the first time, if not, conduction of the next period is carried out, the duration time of the first conduction of the clamping tube in the next period is increased by a certain time delay, and the time is set as the first conduction time of the next period; if the current value is decreased to 0, the difference between the first conduction time and the initial conduction time in the period, that is, the time difference between the time when the exciting current is decreased to 0 in the first conduction in the period and the initial value of the first conduction time is latched, the time difference is set as the second conduction time Ta,
in practical application, when the secondary side output voltage of the transformer is fixed, the first time Ta is in positive correlation with the primary side input voltage, and when the input voltage rises, Ta is increased; when the input voltage is reduced, Ta is reduced, when the input voltage of the primary side of the transformer is fixed, the first time Ta is in positive correlation with the output voltage of the secondary side, and when the output voltage is increased, Ta is increased; when the output voltage is reduced, Ta is reduced, meanwhile, it should be noted that the opening interval of the main power tube is approximately kept unchanged in steady-state operation, so that the second conduction time of the clamping tube in each period after Ta is determined can be approximately regarded as being kept unchanged, and the initial time of the second conduction is also approximately kept unchanged.
As shown in fig. 5, if the time controlled by Ta is enough, the current ILM on the excitation inductor will become negative, i.e. maintain in reverse direction for a period of time, after the clamp is turned on for the first time, within a set short time Td, at time t4, the drain terminal voltage Vds of the main power tube is drained to 0 potential by negative current, at time t4, the current of the excitation inductor is 0, then Vds starts to resonate again, the difference between the first on time of the clamp in the current period and the initial on time Tdis, i.e. Ta is locked, which means that the negative current generated by the clamp in time Ta is enough to drain the charge on the source parasitic capacitor of the main power tube.
The waveform shown in fig. 6 indicates the magnitude of negative current at different turn-off times and the variation waveform of the voltage at the drain terminal of the main power tube after turn-off when the clamp tube is turned off for the first time, wherein Vds indicates the drain-source voltage of the main power tube, ILM indicates the current of the excitation inductor, Sa indicates the control signal of the clamp tube, the clamp tubes are all turned on at ts0, if the clamp tube is turned off at ts1, the current of the inductor is just 0 at this time, the generated negative current I _ neg1 is also 0 at this time, the resonance waveform of the voltage at the drain terminal of the main power tube after turn-off is not different from the resonance waveform of the common flyback converter, and the voltage at the lowest resonance point is Vds 1; if the clamp tube is turned off at the ts2 moment, a certain negative current I _ neg2 is generated, and under the action of the negative current, the drain end voltage of the main power tube is discharged to a Vds2 which is lower than Vds1, but the Vds2 is still higher than 0; if the clamp is turned off at ts3, and the negative current I _ neg3 generated at this time is larger than I _ neg2, the drain voltage of the main power tube is drained to a lower potential Vds3 after ts3 is turned off, and Vds3 is just 0. It can be approximately considered that the control of the turn-off time of the clamp tube after the first turn-on can be used for searching for a proper negative current and providing a relatively accurate turn-on time parameter for the subsequent second turn-on.
In this embodiment, in the third step, the negative currents generated on the excitation inductor by the first conduction and the second conduction of the clamping tube are equal in magnitude and same in duration, and the processes of the first conduction and the second conduction are present in each period of the steady state and do not overlap with each other.
A light-load conduction control circuit of a clamp tube in an active clamp flyback topology is applied to a light-load conduction control method of the clamp tube in the active clamp flyback topology and comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit, wherein the detection circuit receives drain-source voltage of a main power tube to judge whether negative current generated after the clamp tube is conducted for the first time is enough or not, generates an enable signal EN to control and adjust the first conduction time, and generates initial conduction time according to the drain-source voltage of the main power tube.
As shown in fig. 9, the detection circuit detects SW, i.e. the drain voltage of the main power transistor, generates Tdis and detects whether the SW voltage drops to about 0 level within Td time after the first turn-on, and if not, generates the enable control signal EN to control the first turn-on unit to control the next period of the clamp transistor to be turned off later for a period of time; if it falls to 0, the current first on time is latched. On the other hand, the detection circuit also detects the initial on-time Tdis;
the detection circuit comprises a voltage signal SW, wherein the voltage signal SW is connected with the drain terminal of a JFET tube QD0, the source terminal of the QD0 is connected with the positive input terminal of a comparator CMP2, the reverse input terminal of the comparator CMP2 is connected with a +100mV voltage signal, the output of the comparator CMP2 is connected with the D terminal of the data input terminal of a D trigger DFF1, the clock input terminal CLK of the DFF1 is connected with a sampling signal Td, and the output of the trigger DFF1 generates a control signal EN which is connected with the input terminal of a first conduction control module; the voltage signal SW is further connected to an upper plate of a capacitor CS, a lower plate of the capacitor CS is connected to one end of a resistor Rs, the other end of the resistor Rs is grounded, a lower plate of the capacitor CS is further connected to a reverse input terminal of a comparator CMP1, a forward input terminal of the comparator CMP1 is connected to a +10mV voltage signal, an output of the comparator CMP1 is connected to a drain terminal of an NMOS transistor MN0, a gate of the NMOS transistor NM0 is connected to a control signal OFF _ LEB, a source of the NMOS transistor NM0 is connected to ground, an output of the comparator CMP1 is further connected to one input terminal of a Nor gate Nor1, another input terminal of the Nor gate 1 is connected to an output of a Nor gate 2, an output of the Nor gate 1 generates a Tdis signal and is connected to an input terminal of a second conduction control module, and is further connected to one input terminal of the Nor gate 2, and two input terminals of the control signal SP _ ON and the control signal OFF _ LEB 3 are connected respectively, the output of the NOR gate Nor3 is connected with the other input end of the NOR gate Nor 2;
in fig. 9, CS and Rs constitute a simple differentiating circuit, the output of which is input to the inverting input of a comparator CMP1 for comparison with a +10mV reference voltage, the output of which is pulled low for the OFF _ LEB time, masking the output of the comparator; after the OFF _ LEB time, the comparator normally outputs a comparison signal. The output of the comparator CMP1 is connected with the input end of the NOR gate Nor1, Nor1 and Nor2 form an SR trigger, the output of Nor1 is Tdis, SP _ ON is the control signal of the main power tube, and OFF _ LEB represents a short dead time after the main power tube is turned OFF. And determining the time point of the follow current to 0, namely the moment when the inductive current reaches 0, by detecting the change rate of the SW, and obtaining the Tdis signal after latching. SW is also connected with a Drain end of a JFET QD0, a source end of a QD0 is connected with an inverting input end of a comparator CMP2, a positive input end of a CMP2 is connected with +100mV voltage, an output of the comparator CMP2 is connected with a Data end of a D flip-flop DFF1, a CLK input end of a DFF1 is connected with a Td control signal, and an output of the comparator CMP2 is sampled at a falling edge of Td to obtain an EN signal. That is, in the Td period, if the SW voltage drops below the reference threshold of 100mV, it is determined that the on-time just generates enough negative current, EN is low, otherwise EN is high, and the first on-control module in the next period is controlled to continuously adjust the first on-time;
FIG. 12 shows the operating waveforms of the key signals in one period in FIG. 9, wherein SW represents the drain voltage of the main power transistor, SP _ ON is the turn-ON signal of the main power transistor, OFF _ LEB is the dead zone control signal after the main power transistor is turned OFF, Tdis is the output control signal of the detection unit, Td is the set detection time signal, and EN is the output of the detection module; in this period shown in fig. 12, Tdis starts at time t _ de3 and ends at time t _ de4, the SW voltage does not drop to 0 after a delay of Td, the output result of the falling edge sampling comparator CMP2 of Td is high, that is, EN is high, and the first on time of the next period continues to increase.
As shown in fig. 10, the first on-time control module outputs a first on-time control signal, and adjusts the first on-time according to the feedback of the detection circuit until a second on-time Ta occurs, so as to control the clamp tube to be turned on for a second time;
a first turn-on time control signal Tdis is connected to the gate of a PMOS transistor MP1, said Tdis signal is further connected to the gate of an NMOS transistor NM1, said Tdis signal is further connected to one input terminal of a Nor gate Nor5, the source of said PMOS transistor MP1 is connected to a current source Ic, the drain of said MP1 is connected to the drain of said NMOS transistor NM1, the drain of said MP1 is further connected to the upper plate of a capacitor CH1, the drain of said MP1 is further connected to one input terminal of a Nor gate Nor4, the other input terminal of said Nor gate Nor4 is connected to the output of said Nor gate Nor 6334, the other input terminal of said Nor gate Nor5 is connected to the output terminal of said Nor gate Nor 38, the lower plate of said capacitor CH1 is connected to ground, the source of said NMOS transistor MN1 is connected to ground, said control signal tdin and said control signal Tdis are connected to the input terminal of a bidirectional counting unit CNT1, said bidirectional counter MP1 outputs a current source Ic or a current source Ic increasing or decreasing current period, the output of the Nor gate Nor4 is a first turn-on control signal T1;
the gates of MP1 and MP2 are connected to control signal Tdis, current Ic charges and discharges capacitor CH1, EN controls bidirectional counting unit CNT1 to control charging current Ic to increase or decrease, and when increasing, first turn-on control signal T1 becomes short; when decreasing, the first on control signal T1 becomes long;
as shown in fig. 11, the second on-time control module obtains a second on-time control signal Ta according to the first on-time control signal T1 fed back by the first on-time control module and the initial on-time Tdis, controls the clamp transistor to generate a second on-time control signal, and generates a second clamp transistor on-off signal according to Ta and the period of the main power transistor in the previous period;
the inverse signal of T1 and Tdis OR logic generate the second conduction control signal Ta;
the driving unit controls the clamping tube to sequentially complete first conduction and second conduction according to control signals generated by the first conduction time control module and the second conduction time control module;
as shown in fig. 9 and 13, the clamping tube is controlled to sequentially complete the first conduction and the second conduction according to the control signals generated by the first conduction time control module and the second conduction time control module;
the control signal T1 of the first conduction control module and the control signal Ta of the second conduction control module are input to the gates of the LDMOS LD1 and LD2 through the OR gate OR1 and the inverter Inv3, level-shifted signals are generated through RD1 and RD2 and are sent to the input end of the RS flip-flop RS1, RD3, PD1 and Cd1 are used to suppress common mode noise, similarly, PD2, RD4 and Cd2 are also used to suppress common mode noise, the output of RS1 drives the gate of the active clamp through the driving buffer DR1, the reference ground of RS1 and DR1 is connected to SW, and the reference power supply is connected to VB, wherein a bootstrap capacitor CB is further connected between VB and SW in series.
In this embodiment, an output end of the detection circuit is connected to an input end of a first on-time control module, output ends of the first on-time control module and the detection circuit are connected to an input end of a second on-time control module, output ends of the first on-time control module and the second on-time control module are both connected to an input end of a driving unit, and an output end of the driving unit is connected to a gate of the active clamp tube.
While there have been shown and described what are at present considered the fundamental principles and essential features of the invention and its advantages, it will be apparent to those skilled in the art that the invention is not limited to the details of the foregoing exemplary embodiments, but is capable of other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (6)
1. A light-load conduction control method for a clamp tube in an active clamp flyback topology comprises an active clamp flyback circuit, and is characterized in that: the light-load conduction control circuit comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit, wherein the detection circuit and the driving unit are connected with the active clamping flyback circuit, and the control method specifically comprises the following steps:
the first step is as follows: the detection circuit detects the follow current time of the active clamp flyback circuit in a light-load steady state and sets the time as initial conduction time and first conduction time;
the second step is that: the first conduction time control module outputs an initial conduction control signal to the clamping tube through the driving unit according to first conduction time set by the detection circuit, the clamping tube is conducted, the detection circuit detects whether the drain-source voltage of the main power tube is reduced to 0 within a certain time, and according to the result, the first conduction time is reset or second conduction time is set;
the third step: the second conduction time control module outputs two conduction control signals to the clamping tube through the driving unit according to the first conduction time and the second conduction time fed back by the first conduction time control module and the detection circuit, and meanwhile, the next main power tube is started, and the next period starts;
the fourth step: the third step is performed periodically.
2. The method for controlling the light-load conduction of the clamp tube in the active clamp flyback topology according to claim 1, wherein the method comprises the following steps: in the second step, the detection circuit detects whether the drain-source voltage of the main power tube drops to 0 within a certain time, and according to the result, the specific process of resetting the first conduction time or the second conduction time is as follows: the detection circuit detects whether the drain-source voltage of the main power tube is reduced to 0 within a short set time after the clamping tube is conducted for the first time, if not, conduction of the next period is carried out, the duration time of the first conduction of the clamping tube in the next period is increased by a certain time delay, and the time is set as the first conduction time of the next period; if the current value is decreased to 0, the difference between the first conduction time and the initial conduction time in the period, namely the time difference between the moment when the exciting current is decreased to 0 in the first conduction in the period and the initial value of the first conduction time is locked, and the time difference is set as the second conduction time.
3. The method for controlling the light-load conduction of the clamp tube in the active clamp flyback topology according to claim 1, wherein the method comprises the following steps: in the third step, the driving unit outputs two conduction control signals to the clamping tube, so that the clamping tube is conducted after the main power tube is turned off and before the main power tube is turned on next time, and the two conduction time periods are the first conduction time and the second conduction time respectively.
4. The method for controlling the light-load conduction of the clamp tube in the active clamp flyback topology according to claim 1, wherein the method comprises the following steps: in the third step, the magnitude of the negative current generated by the first conduction and the second conduction of the clamping tube is equal, and the duration time of the negative current is the same.
5. A light-load conduction control circuit of a clamp tube in an active clamp flyback topology is applied to the light-load conduction control method of the clamp tube in the active clamp flyback topology disclosed by claims 1-4, and is characterized in that: the device comprises a detection circuit, a first conduction time control module, a second conduction time control module and a driving unit.
6. The light-load conduction control circuit for the clamp tube in the active clamp flyback topology according to claim 5, wherein: the output end of the detection circuit is connected with the input end of the first conduction time control module, the output ends of the first conduction time control module and the detection circuit are connected with the input end of the second conduction time control module, and the output ends of the first conduction time control module and the second conduction time control module are connected with the input end of the driving unit.
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