CN114188380B

CN114188380B - Display panel and preparation method thereof

Info

Publication number: CN114188380B
Application number: CN202111459760.5A
Authority: CN
Inventors: 吴小玲; 曾维静
Original assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Current assignee: Shenzhen China Star Optoelectronics Semiconductor Display Technology Co Ltd
Priority date: 2021-12-02
Filing date: 2021-12-02
Publication date: 2023-05-05
Anticipated expiration: 2041-12-02
Also published as: CN114188380A

Abstract

The application discloses a display panel and a preparation method thereof, wherein the display panel is defined with a display area and a bending area; in the bending region, the display panel includes: a substrate layer; the bending metal layer is arranged on the substrate layer; the first flat layer is arranged on the bending metal layer and the substrate layer, wherein the first flat layer is provided with at least one groove for exposing the bending metal layer; the first conducting layer is arranged on the first flat layer and extends to the inner wall of the groove; the first pixel definition layer is arranged on the first conductive layer and fills the corresponding position of the groove; wherein the substrate layer, the first planarization layer, and the first pixel definition layer are all made of organic materials. The organic material is adopted to replace the existing inorganic material, so that the bending metal layer and the first conductive layer which are positioned in the bending area are coated by the organic material, thereby reducing the influence of stress and prolonging the bending life of the display panel.

Description

Display panel and preparation method thereof

Technical Field

The application relates to the technical field of display, in particular to a display panel and a preparation method thereof.

Background

Organic Light-Emitting Diode (OLED) has a wider application range due to the advantages of Light weight, self-luminescence, wide viewing angle, low driving voltage, high luminous efficiency, low power consumption, high response speed, and the like. In particular, the flexible OLED display panel has the characteristics of being bendable and easy to carry, and becomes a main field for research and development in the technical field of display.

Since the flexible OLED display panel includes a bending region where the substrate may be folded, and the bezel size may be reduced by folding the substrate at the bending region, a flexible OLED display panel having a narrow bezel may be realized.

However, as the bending degree increases, the flexible OLED display panel has a narrower frame, but in the process of bending the flexible OLED display panel, the inorganic film is easily affected by stress and may be broken, and the metal routing layer may have a risk of breaking and wire breakage after bending.

Disclosure of Invention

The invention aims to provide a display panel and a preparation method thereof, which are used for solving the technical problems of breakage and disconnection of an inorganic film and a metal wiring layer caused by the influence of stress in a bending region of the display panel.

In order to achieve the above object, the present invention provides a display panel, wherein the display panel defines a display area and a bending area; in the bending region, the display panel includes: a substrate layer; the bending metal layer is arranged on the substrate layer; the first flat layer is arranged on the bending metal layer and the substrate layer, wherein the first flat layer is provided with at least one groove for exposing the bending metal layer; the first conducting layer is arranged on the first flat layer and extends to the inner wall of the groove; the first pixel definition layer is arranged on the first conductive layer and fills the corresponding position of the groove; wherein the substrate layer, the first planarization layer, and the first pixel definition layer are all made of organic materials.

Further, the display area comprises a thin film transistor area and a capacitor area; in the display area, the display panel includes: a barrier layer disposed on the substrate layer; the shading conductive layers are arranged on the barrier layer at intervals; a buffer layer covering the light-shielding conductive layer and extending to the surface of the barrier layer; the semiconductor layer is arranged on the buffer layer, wherein the projection of the semiconductor layer on the substrate layer falls into the projection range of the semiconductor layer on the substrate layer; the insulating layer is arranged on the semiconductor layer and is positioned in the thin film transistor area; the grid electrode layer is arranged on the insulating layer and is positioned in the thin film transistor area; a dielectric layer covering the gate layer and the semiconductor layer and extending to the surface of the buffer layer; a display metal layer including a source-drain electrode layer connected to the semiconductor layer through a first via hole and a metal connection layer connected to the light-shielding conductive layer through a second via hole; a passivation layer covering the display metal layer and extending to the surface of the dielectric layer; the second flat layer is arranged on the passivation layer; the second conducting layer is connected to the source-drain electrode layer through a third through hole and extends the surface of the second flat layer; an anode layer disposed on the second flat layer; and the second pixel definition layer is arranged on the anode layer and extends to the surface of the second flat layer, and the second pixel definition layer is provided with an opening for exposing the anode layer.

Further, in the capacitor region, the projection of the metal connection layer on the substrate layer falls into the projection range of the semiconductor layer on the substrate layer to form two storage capacitors which are arranged in parallel.

Further, in the thin film transistor region, the gate layer is a front gate structure of the thin film transistor in the same thin film transistor, and is used for driving the thin film transistor to be turned on or turned off; the metal connecting layer is a back gate structure of the thin film transistor and is used for adjusting the threshold voltage of the thin film transistor.

Further, the bending metal layer and the shading conductive layer are formed in the same process step; or, the bending metal layer and the display metal layer are formed in the same process step; the first flat layer and the second flat layer are formed in the same process step; the first conductive layer and the second conductive layer are formed in the same process step; the first pixel defining layer and the second pixel defining layer are formed in the same process step.

In order to achieve the above object, the present invention further provides a method for manufacturing a display panel, where the display panel is defined with a display area and a bending area; the preparation method comprises the following steps: forming a substrate layer on a glass substrate and extending from the display region to the bending region; forming a barrier layer on the substrate layer and extending from the display region to the inflection region; forming a buffer layer on the barrier layer and extending from the display region to the bending region; forming a dielectric layer on the buffer layer and extending from the display region to the bending region; patterning the dielectric layer with a photomask such that the dielectric layer, the buffer layer and the barrier layer in the inflection region are removed and the substrate layer in the inflection region is exposed; forming a bending metal layer on the substrate layer and located in the bending area; forming a first flat layer on the bending metal layer and the substrate layer and located in the bending area; patterning the first flat layer to form at least one groove for exposing the bending metal layer; forming a first conductive layer on the first flat layer and extending to the inner wall of the groove and located in the bending region; forming a first pixel definition layer on the first conductive layer, filling the corresponding position of the groove, and being positioned in the bending region; the substrate layer, the first flat layer and the first pixel definition layer are made of organic materials.

Further, after the step of forming the barrier layer, before the step of forming the buffer layer, the method further includes: forming a shading conductive layer on the barrier layer and located in the display area; after the buffer layer forming step, before the dielectric layer forming step, further includes: forming a semiconductor layer on the buffer layer and located in the display region; wherein, the projection of the semiconductor layer on the substrate layer falls into the projection range of the semiconductor layer on the substrate layer; forming a thin film transistor region on the semiconductor layer and located in the display region; forming a grid layer on the insulating layer and positioned in a thin film transistor area of the display area; in the step of patterning the dielectric layer, the method further comprises: patterning the dielectric layer by using the photomask to form a first through hole and a second through hole; the first through hole penetrates through the surface of the semiconductor layer and is positioned in a thin film transistor area of the display area; the second through hole penetrates through the surface of the shading conductive layer and is positioned in the thin film transistor area and the capacitor area of the display area.

Further, the photomask comprises a first light transmission area, a second light transmission area and a third light transmission area, and the dielectric layer positioned in the bending area is subjected to patterning treatment through the first light transmission area so that the substrate layer is exposed; patterning the dielectric layer in the display area through the first light-transmitting area to form the first through hole; transmitting the second light-transmitting region to perform patterning treatment on the dielectric layer in the display region so as to form the second through hole; wherein the light transmittance of the third light-transmitting region is smaller than the light transmittance of the first light-transmitting region; the light transmittance of the second light transmission region is smaller than that of the third light transmission region.

Further, after the patterning step is performed on the dielectric layer, the method further includes: forming a display metal layer on the substrate layer and located in the display area, wherein the display metal layer comprises a source-drain electrode layer and a metal connecting layer, the source-drain electrode layer is connected to the semiconductor layer through a first through hole, and the metal connecting layer is connected to the shading conductive layer through a second through hole; wherein the bending metal layer and the display metal layer are formed in the same process step; forming a passivation layer on the display metal layer, extending to the surface of the dielectric layer and located in the display area; forming a second flat layer on the passivation layer and located in the display region; wherein the first planarization layer and the second planarization layer are formed in the same process step; patterning the second flat layer to form a third through hole; forming a second conductive layer in the third through hole and extending the surface of the second flat layer; wherein the first conductive layer and the second conductive layer are formed in the same process step; forming an anode layer on the second flat layer and located in the display area; forming a second pixel defining layer on the anode layer and extending to the surface of the second flat layer; wherein the first pixel definition layer and the second pixel definition layer are formed in the same process step; patterning the second pixel defining layer to form an opening, wherein the opening is used for exposing the anode layer.

In order to achieve the above object, the present invention further provides a method for manufacturing a display panel, where the display panel is defined with a display area and a bending area; the preparation method comprises the following steps: forming a substrate layer on a glass substrate and extending from the display region to the bending region; forming a bending metal layer on the substrate layer and located in the bending area; forming a first flat layer on the bending metal layer and the substrate layer and located in the bending area; patterning the first flat layer to form at least one groove for exposing the bending metal layer; forming a first conductive layer on the first flat layer and extending to the inner wall of the groove and located in the bending region; forming a first pixel definition layer on the first conductive layer, filling the corresponding position of the groove, and being positioned in the bending region; the substrate layer, the first flat layer and the first pixel definition layer are made of organic materials.

Further, after the step of forming the substrate layer, the method further includes: forming a barrier layer on the substrate layer and in the display region; forming a shading conductive layer on the barrier layer and located in the display area; wherein, the shading conductive layer and the bending metal layer are formed in the same process step; forming a buffer layer on the shading conductive layer, extending to the surface of the barrier layer and located in the display area; forming a semiconductor layer on the buffer layer and located in the display region; wherein, the projection of the semiconductor layer on the substrate layer falls into the projection range of the semiconductor layer on the substrate layer; forming an insulating layer on the semiconductor layer and located in the thin film transistor region of the display region; forming a grid layer on the insulating layer and positioned in a thin film transistor area of the display area; forming a dielectric layer on the gate layer and the semiconductor layer, extending to the surface of the buffer layer and located in the display region; patterning the dielectric layer by using the photomask to form a first through hole and a second through hole; the first through hole penetrates through the surface of the semiconductor layer and is positioned in a thin film transistor area of the display area; the second through hole penetrates through the surface of the shading conductive layer and is positioned in a thin film transistor area and a capacitor area of the display area; forming a display metal layer on the substrate layer and located in the display area, wherein the display metal layer comprises a source-drain electrode layer and a metal connecting layer, the source-drain electrode layer is connected to the semiconductor layer through a first through hole, and the metal connecting layer is connected to the shading conductive layer through a second through hole; forming a passivation layer on the display metal layer, extending to the surface of the dielectric layer and located in the display area; forming a second flat layer on the passivation layer and located in the display region; wherein the first planarization layer and the second planarization layer are formed in the same process step; patterning the second flat layer to form a third through hole; forming a second conductive layer in the third through hole and extending the surface of the second flat layer; wherein the first conductive layer and the second conductive layer are formed in the same process step; forming an anode layer on the second flat layer and located in the display area; forming a second pixel defining layer on the anode layer and extending to the surface of the second flat layer; wherein the first pixel definition layer and the second pixel definition layer are formed in the same process step; patterning the second pixel defining layer to form an opening, wherein the opening is used for exposing the anode layer.

The invention has the technical effects that the display panel and the preparation method thereof are provided, and the existing inorganic material is replaced by the organic material, so that the metal wires (the bending metal layer and the first conductive layer) positioned in the bending area are coated by the organic material, thereby reducing the influence of stress and prolonging the bending life of the display panel.

Drawings

Technical solutions and other advantageous effects of the present application will be made apparent from the following detailed description of specific embodiments of the present application with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a display panel provided in embodiment 1 of the present application.

Fig. 2 is a flowchart of a method for manufacturing a display panel according to embodiment 1 of the present application.

Fig. 3 is a schematic structural diagram of a dielectric layer formed according to embodiment 1 of the present application.

Fig. 4 is a schematic diagram of a dielectric layer patterned according to embodiment 1 of the present application.

Fig. 5 is a schematic diagram of a structure of the bent metal layer and the display metal layer provided in embodiment 1 of the present application after formation.

Fig. 6 is a schematic structural diagram of the passivation layer provided in embodiment 1 of the present application after formation.

Fig. 7 is a schematic structural diagram of the first and second planarization layers patterned according to embodiment 1 of the present application.

Fig. 8 is a schematic structural diagram of an anode layer according to embodiment 1 of the present application after formation.

Fig. 9 is a schematic structural diagram of the first and second pixel defining layers provided in embodiment 1 of the present application after formation.

Fig. 10 is a schematic structural diagram of the second pixel defining layer after patterning according to embodiment 1 of the present application.

Fig. 11 is a flowchart of a method for manufacturing a display panel according to embodiment 2 of the present application.

Fig. 12 is a schematic structural diagram of a display panel according to embodiment 2 of the present application.

The components of the drawings are identified as follows:

100. a display panel; 101. A display area;

102. a bending region; 101a, thin film transistor region;

101b, a capacitive region; 1. A substrate layer;

2. a barrier layer; 3. A light-shielding conductive layer;

4. a buffer layer; 5. A semiconductor layer;

6. an insulating layer; 7. A gate layer;

8. a dielectric layer; a PV, passivation layer;

9. bending the metal layer; 10. Displaying the metal layer;

11a, a first planarization layer; 11b, a second planar layer;

12a, a first conductive layer; 12c, a second conductive layer;

13a, a first pixel definition layer; 13b, a second pixel definition layer;

14. an anode layer; 1001. A source/drain layer;

1002. a metal connection layer; 1001a, a first through hole;

1002a, a second through hole; 120c, a third through hole;

130b, openings; 110a, grooves;

200. a photomask; 201. A first light-transmitting region;

202. a second light-transmitting region; 203. A third light-transmitting region;

300. a glass substrate.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. In the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise. In addition, the present application provides examples of various specific processes and materials, but one of ordinary skill in the art may recognize the application of other processes and/or the use of other materials.

Example 1

As shown in fig. 1, the present embodiment provides a display panel 100a, where the display panel 100a defines a display area 101 and a bending area 102.

In the bending region 102, the display panel 100a includes a substrate layer 1, a bending metal layer 9, a first planarization layer 11a, a first conductive layer 12a, and a first pixel defining layer 13a.

Specifically, the material used for the substrate layer 1 includes, but is not limited to, polyimide and organic material.

The bending metal layer 9 is disposed on the substrate layer 1, and the structure of the bending metal layer 9 includes, but is not limited to, a molybdenum aluminum molybdenum laminated structure (Mo/Al/Mo), a molybdenum titanium copper laminated structure (Mo/Ti/Cu). The bent metal layer 9 is a signal trace in the bent region 102.

The first flat layer 11a is disposed on the bent metal layer 9 and the substrate layer 1. Wherein, the first flat layer 11a is provided with at least one groove 110a for exposing the bending metal layer 9. The material used for the first planarization layer 11a is an organic material. When the display panel 100a is a top emission display screen, the thickness of the first planarization layer 11a is thicker, and the requirement on planarization is higher; when the display panel 100a is a low emission display, the first planarization layer 11a has a thinner thickness and a lower requirement for planarization.

The first conductive layer 12a is disposed on the first flat layer 11a and extends to the inner wall of the groove 110a, wherein the first conductive layer 12a is attached to the side wall and the bottom wall of the groove 110 a. The first conductive layer 12a may be formed by PVD (Physical Vapor Deposition ) process using a material of a molybdenum titanium laminate (Mo/Ti) or a single layer of metal (e.g., al). The first conductive layer 12a may be used as a terminal connection region of the display panel 100a, and may also be used as a protection layer of the bending metal layer 9 to improve the bending resistance of the metal in the bending region 102.

The first pixel defining layer 13a is disposed on the first conductive layer 12a, and completely fills the corresponding position of the recess 110 a. The material used for the first pixel defining layer 13a is an organic material.

In this embodiment, the substrate layer 1, the first planarization layer 11a, and the first pixel defining layer 13a are all made of organic materials, so that the bending metal layer 9 and the first conductive layer 12a are completely covered by the organic materials. Therefore, the metal trace formed by bending the metal layer 9 and the first conductive layer 12a is not broken due to stress. In particular, the organic material can reduce the disadvantage of cracks generated after bending the metal layer 9 and the first conductive layer 12 a.

In the present embodiment, the display region 101 includes a thin film transistor region 101a and a capacitor region 101b.

Referring to fig. 1, in a display region 101, a display panel 100a includes a barrier layer 2, a light-shielding conductive layer 3, a buffer layer 4, a semiconductor layer 5, an insulating layer 6, a gate layer 7, a dielectric layer 8, a display metal layer 10, a second planarization layer 11b, a second conductive layer 12c, an anode layer 14, and a second pixel defining layer 13b.

A barrier layer 2 is provided on the substrate layer 1, and the material used for the barrier layer 2 includes, but is not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like.

The light-shielding conductive layers 3 are disposed on the barrier layer 2 at intervals. The light-shielding conductive layer 3 may be manufactured by PVD (Physical Vapor Deposition ) process. The structure of the light shielding conductive layer 3 includes, but is not limited to, a molybdenum aluminum molybdenum laminate structure (Mo/Al/Mo), a molybdenum titanium copper laminate structure (Mo/Ti/Cu). The light shielding conductive layer 3 may serve as a signal metal trace in the capacitance region 101b.

The buffer layer 4 covers the light-shielding conductive layer 3 and extends to the surface of the barrier layer 2. The buffer layer 4 may be fabricated by a CVD (Chemical Vapor Deposition ) process. The material used for the buffer layer 4 includes, but is not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like.

The semiconductor layer 5 is provided on the buffer layer 4, which is an IGZO semiconductor layer 5, and the semiconductor layer 5 can be manufactured by a sputtering (dispenser) process. Wherein the projection of the semiconductor layer 5 onto the substrate layer 1 falls within the projection range of the semiconductor layer 5 onto the substrate layer 1. In this embodiment, the light shielding conductive layer 3 shields the channel region (i.e., the semiconductor layer 5) of the driving TFT in the thin film transistor region 101a to prevent the electrical property of the driving TFT from being affected by light.

The insulating layer 6 is provided on the semiconductor layer 5 and is located in the thin film transistor region 101a. The material used for the insulating layer 6 includes, but is not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like.

The gate layer 7 is disposed on the insulating layer 6 and located in the thin film transistor region 101a, and the gate layer 7 may be a scan signal trace. The structure of the gate layer 7 includes, but is not limited to, a molybdenum aluminum molybdenum laminate structure (Mo/Al/Mo), a molybdenum titanium copper laminate structure (Mo/Ti/Cu). Wherein the insulating layer 6 and the gate layer 7 are fabricated by a self-aligned process.

The dielectric layer 8 covers the gate layer 7 and the semiconductor layer 5 and extends to the upper surface of the buffer layer 4. The dielectric layer 8 may be fabricated by a CVD (Chemical Vapor Deposition ) process. The material used for the dielectric layer 8 includes, but is not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like.

The display metal layer 10 includes a source/drain layer 1001 and a metal connection layer 1002, the source/drain layer 1001 is connected to the semiconductor layer 5 through a first via 1001a, and the metal connection layer 1002 is connected to the light shielding conductive layer 3 through a second via 1002 a. The metal layer 10 is shown to be formed in the same process step as the bent metal layer 9, and the same material is used as the bent metal layer 9.

Further, in the thin film transistor region 101a, a thin film transistor having a double-gate structure is formed of the semiconductor layer 5, the source/drain layer 1001, the gate layer 7, and the metal connection layer 1002. In the same thin film transistor, the gate layer 7 is a front gate structure of the thin film transistor for driving the thin film transistor to be turned on or off. The metal connection layer 1002 is a back gate structure of the thin film transistor, and is used for adjusting a threshold voltage of the thin film transistor, and for adjusting brightness of the display panel 100a, so as to improve display quality of a display screen.

In the capacitor region 101b, the projection of the metal connection layer 1002 on the substrate layer 1 falls within the projection range of the semiconductor layer 5 on the substrate layer 1 to form two storage capacitors arranged in parallel. The storage capacitor is used for charging the thin film transistor.

The passivation layer PV covers the display metal layer 10 and extends to the surface of the dielectric layer 8. The passivation layer PV may be fabricated by a CVD (Chemical Vapor Deposition ) process. Materials used for passivation layer PV include, but are not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like. The passivation layer PV is used to prevent the electrical effect of the thin film transistor from being affected by the back-end process.

The second planarization layer 11b is disposed on the passivation layer PV. When the display panel 100a is a top emission display screen, the second planarization layer 11b has a thicker thickness and a higher requirement for planarization; when the display panel 100a is a low emission display screen, the thickness of the second planarization layer 11b is thin, and the requirement for planarization is low. In this embodiment, the second flat layer 11b and the first flat layer 11a are formed in the same process step, and the material used for the second flat layer 11b is the same as that of the first flat layer 11 a.

The second conductive layer 12c is connected to the source-drain layer 1001 through the third via 120c, and extends the surface of the second flat layer 11 b. The second conductive layer 12c is formed in the same process step as the first conductive layer 12a, and the material used for the second conductive layer is the same as that of the first conductive layer 12 a.

The anode layer 14 is provided on the second flat layer 11 b. The anode layer 14 may be fabricated by PVD (Physical Vapor Deposition ) processes, including but not limited to a stacked structure of oxidized ITO/Ag/ITO or a single layer of ITO.

The second pixel defining layer 13b is disposed on the anode layer 14 and extends to the upper surface of the second flat layer 11b, and the second pixel defining layer 13b is provided with an opening 130b for exposing the anode layer 14. The second pixel defining layer 13b is formed in the same process step as the first pixel defining layer 13a, and the material used for the second pixel defining layer 13b is the same as that of the first pixel defining layer 13 a.

The present embodiment provides a display panel 100a, which uses an organic material instead of the existing inorganic material, so that the metal wires (the bending metal layer 9 and the first conductive layer 12 a) located in the bending region 102 are covered by the organic material, thereby reducing the influence of stress and improving the bending life of the display panel 100 a.

As shown in fig. 2, the present embodiment further provides a method for manufacturing a display panel 100a, where the display panel 100a defines a display area 101 and a bending area 102.

In this embodiment, the manufacturing method of the display panel 100a includes the following steps S11 to S117).

S11) forming the substrate layer 1 on a glass substrate 300 and extending from the display area 101 to the bending area 102, see fig. 3.

S12) forming a barrier layer 2 on the substrate layer 1 and extending from the display region 101 to the bending region 102, see fig. 3.

Specifically, the barrier layer 2 is formed by depositing an inorganic material on the substrate layer 1, and the material used for the barrier layer 2 includes, but is not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like.

S13) a light-shielding conductive layer 3 is formed on the barrier layer 2 and located in the display area 101, see fig. 3.

Specifically, the light-shielding conductive layer 3 is prepared on the barrier layer 2 by PVD (Physical Vapor Deposition ). The structure of the light shielding conductive layer 3 includes, but is not limited to, a molybdenum aluminum molybdenum laminate structure (Mo/Al/Mo), a molybdenum titanium copper laminate structure (Mo/Ti/Cu). The light shielding conductive layer 3 may serve as a signal metal trace in the capacitance region 101 b.

S14) forming a buffer layer 4 on the light-shielding conductive layer 3 and extending from the display region 101 to the bending region 102, see fig. 3.

Specifically, the buffer layer 4 is formed by depositing an inorganic material on the barrier layer 2 by CVD (Chemical Vapor Deposition ). The material used for the buffer layer 4 includes, but is not limited to, inorganic materials such as SiOX, siNX, or Al2O 3.

S15) forming a semiconductor layer 5 on the buffer layer 4 and located in the display region 101, see fig. 3. Wherein, the projection of the semiconductor layer 5 on the substrate layer 1 falls within the projection range of the semiconductor layer 5 on the substrate layer 1.

Specifically, the semiconductor layer 5 is formed on the buffer layer 4 by a sputtering (dispenser) method. In this embodiment, the light shielding conductive layer 3 shields the channel region (i.e., the semiconductor layer 5) of the driving TFT in the thin film transistor region 101a to prevent the electrical property of the driving TFT from being affected by light.

S16) forming an insulating layer 6 on the semiconductor layer 5 and located in the thin film transistor region 101a of the display region 101, see fig. 3.

Specifically, the insulating layer 6 is fabricated by a self-aligned process. The material used for the insulating layer 6 includes, but is not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like.

S17) forming a gate layer 7 on the insulating layer 6 and located in the thin film transistor region 101a of the display region 101, see fig. 3.

Specifically, the gate layer 7 is fabricated by a self-aligned process. The structure of the gate layer 7 includes, but is not limited to, a molybdenum aluminum molybdenum laminate structure (Mo/Al/Mo), a molybdenum titanium copper laminate structure (Mo/Ti/Cu). Wherein the insulating layer 6 and the gate layer 7 are fabricated by a self-aligned process.

S18) forming a dielectric layer 8 on the buffer layer 4 and extending from the display region 101 to the bending region 102.

Specifically, the dielectric layer 8 is formed by CVD (Chemical Vapor Deposition ). The material used for the dielectric layer 8 includes, but is not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like.

S19) patterning the dielectric layer 8 using a mask 200 such that the dielectric layer 8, the buffer layer 4 and the barrier layer 2 located in the inflection region 102 are removed and the substrate layer 1 located in the inflection region 102 is exposed; and patterning the dielectric layer 8 using the mask 200 to form a first via 1001a and a second via 1002a. The first through hole 1001a penetrates to the surface of the semiconductor layer 5 and is located in the thin film transistor region 101a of the display region 101; the second via 1002a penetrates to the surface of the light-shielding conductive layer 3, and is located in the thin film transistor region 101a and the capacitor region 101b of the display region 101, as shown in fig. 1 and 4.

In this embodiment, the Mask 200 may be an HTM Mask (Half Tone Mask), a GTM Mask (Gray Tone Mask), or the like. The mask 200 includes a first light-transmitting region 201, a second light-transmitting region 202, and a third light-transmitting region 203. Specifically, the dielectric layer 8 located in the bending region 102 is patterned through the first light-transmitting region 201, so that the substrate layer 1 is exposed; patterning the dielectric layer 8 in the display area 101 through the second transparent area 202 to form the first through hole 1001a; the dielectric layer 8 in the display area 101 is patterned through the third transparent area 203 to form the second via 1002a.

Further, the light transmittance of the third light-transmitting region 203 is smaller than the light transmittance of the first light-transmitting region 201, and the light transmittance of the second light-transmitting region 202 is smaller than the light transmittance of the third light-transmitting region 203.

The transmittance of the first light-transmitting region 201, the second light-transmitting region 202 and the third light-transmitting region 203 is determined according to the material, the film thickness and the process of each film. Preferably, in the present embodiment, the light transmittance of the first light transmitting region 201 is 95 to 100%, the light transmittance of the third light transmitting region 203 is 70 to 85%, and the light transmittance of the second light transmitting region 202 is 40 to 65%.

S110) forming a display metal layer 10 and a bending metal layer 9 on the substrate layer 1, wherein the display metal layer 10 is located in the display area 101, and the bending metal layer 9 is located in the bending area 102, referring to fig. 5.

Specifically, the bent metal layer 9 and the display metal layer 10 are formed in the same process step. The display metal layer 10 includes a source-drain electrode layer 1001 and a metal connection layer 1002, the source-drain electrode layer 1001 is connected to the semiconductor layer 5 through a first via 1001a, and the metal connection layer 1002 is connected to the light-shielding conductive layer 3 through a second via 1002 a.

S111) forming a passivation layer PV on the display metal layer 10, extending to the surface of the dielectric layer 8, and located in the display area 101, see fig. 6.

Specifically, the passivation layer PV is formed by CVD (Chemical Vapor Deposition ). Materials used for passivation layer PV include, but are not limited to, siO _X Or SiN _X Or Al ₂ O ₃ And the like. The passivation layer PV is used to prevent the electrical effect of the thin film transistor from being affected by the back-end process.

S112) forming a first flat layer 11a on the folded metal layer 9 and the substrate layer 1 and located in the folded region 102; a second flat layer 11b is formed on the passivation layer PV and located in the display area 101, see fig. 7.

Specifically, the first planarization layer 11a and the second planarization layer 11b are formed in the same process step.

When the display panel 100a is a top emission display, the thicknesses of the first flat layer 11a and the second flat layer 11b are thicker, and the requirement on flatness is higher; when the display panel 100a is a low emission display, the first and second

flat layers

11a and 11b have a small thickness, and thus have a low requirement for flatness.

S113) patterning the first flat layer 11a to form at least one recess 110a for exposing the bent metal layer 9; the second flat layer 11b is patterned to form a third via 120c, see fig. 7.

S114) forming a first conductive layer 12a on the first flat layer 11a, extending to the inner wall of the groove 110a and located in the bending region 102; a second conductive layer 12c is formed in the third via 120c and extends the surface of the second flat layer 11b, see fig. 7.

Specifically, the first conductive layer 12a and the second conductive layer 12c are formed in the same process step.

S115) forming an anode layer 14 on the second flat layer 11b and located in the display area 101, see fig. 8.

Specifically, the anode layer 14 is formed by PVD (Physical Vapor Deposition ). The structure of the anode layer 14 includes, but is not limited to, a stacked structure of oxidized ITO/Ag/ITO or a single-layer ITO structure.

S116) forming a first pixel defining layer 13a on the first conductive layer 12a, filling the corresponding position of the groove 110a, and being located in the bending region 102; a second pixel defining layer 13b is formed on the anode layer 14 and extends to the surface of the second planarization layer 11b, see fig. 9.

Specifically, the first pixel defining layer 13a and the second pixel defining layer 13b are formed in the same process step. The substrate layer 1, the first planarization layer 11a, and the first pixel defining layer 13a are made of organic materials. The organic material is used to replace the existing inorganic material, so that the bending metal layer 9 and the first conductive layer 12a located in the bending region 102 are coated with the organic material, thereby reducing the influence of stress and improving the bending life of the display panel 100 a.

S117) patterning the second pixel defining layer 13b to form an opening 130b, wherein the opening 130b is used to expose the anode layer 14, referring to fig. 10.

In this embodiment, after the patterning process is performed on the second pixel defining layer 13b, other processes, such as a light emitting device and a cover plate, are further performed, which is not described herein.

Example 2

The present embodiment provides a display panel and a method for manufacturing the same, including most of the schemes of embodiment 1, which are different in that the bending metal layer and the display metal layer are formed in the same process step.

Specifically, as shown in fig. 11, the present embodiment provides a method for manufacturing a display panel 100b, where the display panel 100b defines a display area 101 and a bending area 102; the preparation method comprises the following steps S211-S217).

S21) forming the substrate layer 1 on a glass substrate 300 and extending from the display region 101 to the bending region 102, see fig. 12.

S22) forming a barrier layer 2 on the substrate layer 1 and located in the display area 101, see fig. 12.

S23) forming a light-shielding conductive layer 3 on the barrier layer 2 and located in the display area 101; wherein the shading conductive layer 3 and the bending metal layer 9 are formed in the same process step; a bent metal layer 9 is formed on the substrate layer 1 and located in the bending region 102, see fig. 12.

S24) forming a buffer layer 4 on the light-shielding conductive layer 3, extending to the surface of the barrier layer 2 and located in the display area 101, see fig. 12.

S25) forming a semiconductor layer 5 on the buffer layer 4 and located in the display region 101; wherein, the projection of the semiconductor layer 5 on the substrate layer 1 falls within the projection range of the semiconductor layer 5 on the substrate layer 1, refer to fig. 12.

S26) forming an insulating layer 6 on the semiconductor layer 5 and located in the thin film transistor region 101a of the display region 101, see fig. 12.

S27) forming a gate layer 7 on the insulating layer 6 and located in the thin film transistor region 101a of the display region 101, see fig. 12.

S28) forming a dielectric layer 8 on the gate layer 7 and the semiconductor layer 5, extending to the surface of the buffer layer 4 and located in the display region 101, see fig. 12.

S29) patterning the dielectric layer 8 using the mask to form a first via 1001a and a second via 1002a, see fig. 12. The first through hole 1001a penetrates to the surface of the semiconductor layer 5 and is located in the thin film transistor region 101a of the display region 101; the second via hole 1002a penetrates to the surface of the light-shielding conductive layer 3, and is located in the thin film transistor region 101a and the capacitor region 101b of the display region 101.

S210) forming a display metal layer 10 on the substrate layer 1 and located in the display area 101, the display metal layer 10 includes a source/drain layer 1001 and a metal connection layer 1002, the source/drain layer 1001 is connected to the semiconductor layer 5 through a first via 1001a, and the metal connection layer 1002 is connected to the light shielding conductive layer 3 through a second via 1002a, referring to fig. 12.

S211) forming a passivation layer PV on the display metal layer 10, extending to the surface of the dielectric layer 8, and located in the display area 101, see fig. 12.

S212) forming a first flat layer 11a on the folded metal layer 9 and the substrate layer 1 and located in the folded region 102; a second flat layer 11b is formed on the passivation layer PV and located in the display region 101. Wherein the first planarization layer 11a and the second planarization layer 11b are formed in the same process step.

S213) patterning the first flat layer 11a to form at least one recess 110a for exposing the bent metal layer 9; the second flat layer 11b is patterned to form a third via 120c, see fig. 12.

S214) forming a first conductive layer 12a on the first flat layer 11a and extending to the inner wall of the groove 110a, and being located in the bending region 102; a second conductive layer 12c is formed in the third via 120c and extends the surface of the second flat layer 11b, see fig. 12. Wherein the first conductive layer 12a and the second conductive layer 12c are formed in the same process step.

S215) forming an anode layer 14 on the second flat layer 11b and located in the display area 101, see fig. 12.

S216) forming a first pixel defining layer 13a on the first conductive layer 12a, filling the corresponding position of the groove 110a, and being located in the bending region 102; the substrate layer 1, the first planarization layer 11a, and the first pixel defining layer 13a are made of organic materials. A second pixel defining layer 13b is formed on the anode layer 14 and extends to the surface of the second planarization layer 11b, see fig. 12. Wherein the first pixel defining layer 13a and the second pixel defining layer 13b are formed in the same process step.

S217) patterning the second pixel defining layer 13b to form an opening 130b, wherein the opening 130b is used to expose the anode layer 14, referring to fig. 12.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The display panel and the preparation method thereof provided by the embodiment of the application are described in detail, and specific examples are applied to the description of the principle and the implementation of the application, and the description of the above embodiments is only used for helping to understand the technical scheme and the core idea of the application; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. The display panel is characterized by being defined with a display area and a bending area;

in the bending region, the display panel includes:

a substrate layer;

the bending metal layer is arranged on the substrate layer;

The first flat layer is arranged on the bending metal layer and the substrate layer, wherein the first flat layer is provided with at least one groove for exposing the bending metal layer;

the first conducting layer is arranged on the first flat layer and extends to the inner wall of the groove; and

the first pixel definition layer is arranged on the first conductive layer and fills the corresponding position of the groove;

wherein the substrate layer, the first flat layer and the first pixel definition layer are all made of organic materials;

the display area comprises a thin film transistor area and a capacitor area;

in the display area, the display panel includes:

a barrier layer disposed on the substrate layer;

the shading conductive layers are arranged on the barrier layer at intervals;

a buffer layer covering the light-shielding conductive layer and extending to the surface of the barrier layer;

the semiconductor layer is arranged on the buffer layer, wherein the projection of the semiconductor layer on the substrate layer falls into the projection range of the semiconductor layer on the substrate layer;

the insulating layer is arranged on the semiconductor layer and is positioned in the thin film transistor area;

the grid electrode layer is arranged on the insulating layer and is positioned in the thin film transistor area;

A dielectric layer covering the gate layer and the semiconductor layer and extending to the surface of the buffer layer;

a display metal layer including a source-drain electrode layer connected to the semiconductor layer through a first via hole and a metal connection layer connected to the light-shielding conductive layer through a second via hole;

a passivation layer covering the display metal layer and extending to the surface of the dielectric layer;

the second flat layer is arranged on the passivation layer;

the second conducting layer is connected to the source-drain electrode layer through a third through hole and extends the surface of the second flat layer;

an anode layer disposed on the second flat layer; and

the second pixel definition layer is arranged on the anode layer and extends to the surface of the second flat layer, and the second pixel definition layer is provided with an opening for exposing the anode layer;

in the thin film transistor region, in the same thin film transistor, the gate layer is a front gate structure of the thin film transistor and is used for driving the thin film transistor to be turned on or turned off; the metal connecting layer is a back gate structure of the thin film transistor and is used for adjusting the threshold voltage of the thin film transistor.

2. The display panel of claim 1, wherein the display panel comprises,

and in the capacitor region, the projection of the metal connecting layer on the substrate layer falls into the projection range of the semiconductor layer on the substrate layer to form two storage capacitors which are arranged in parallel.

3. The display panel of claim 1, wherein the display panel comprises,

the bending metal layer and the shading conductive layer are formed in the same process step; or, the bending metal layer and the display metal layer are formed in the same process step;

the first flat layer and the second flat layer are formed in the same process step;

the first conductive layer and the second conductive layer are formed in the same process step;

the first pixel defining layer and the second pixel defining layer are formed in the same process step.

4. A preparation method of a display panel is characterized in that the display panel is defined with a display area and a bending area; the preparation method comprises the following steps:

forming a substrate layer on a glass substrate and extending from the display region to the bending region;

forming a barrier layer on the substrate layer and extending from the display region to the inflection region;

Forming a shading conductive layer on the barrier layer and located in the display area;

forming a buffer layer on the barrier layer and extending from the display region to the bending region;

forming a semiconductor layer on the buffer layer and located in the display region; wherein, the projection of the semiconductor layer on the substrate layer falls into the projection range of the semiconductor layer on the substrate layer;

forming a thin film transistor region on the semiconductor layer and located in the display region;

forming a grid layer on the insulating layer and positioned in a thin film transistor area of the display area;

forming a dielectric layer on the buffer layer and extending from the display region to the bending region;

patterning the dielectric layer with a photomask such that the dielectric layer, the buffer layer and the barrier layer in the inflection region are removed and the substrate layer in the inflection region is exposed;

forming a display metal layer and a bending metal layer on the substrate layer; the display metal layer is positioned in the display area and comprises a source-drain electrode layer and a metal connecting layer, wherein the source-drain electrode layer is connected to the semiconductor layer through a first through hole, and the metal connecting layer is connected to the shading conductive layer through a second through hole; the bending metal layer is positioned in the bending area;

Forming a first flat layer on the bending metal layer and the substrate layer and located in the bending area;

patterning the first flat layer to form at least one groove for exposing the bending metal layer;

forming a first conductive layer on the first flat layer and extending to the inner wall of the groove and located in the bending region; patterning the dielectric layer by using the photomask to form a first through hole and a second through hole; the first through hole penetrates through the surface of the semiconductor layer and is positioned in a thin film transistor area of the display area; the second through hole penetrates through the surface of the shading conductive layer and is positioned in a thin film transistor area and a capacitor area of the display area; and

forming a first pixel definition layer on the first conductive layer, filling the corresponding position of the groove, and being positioned in the bending region; wherein the substrate layer, the first flat layer and the first pixel definition layer are made of organic materials;

5. The method for manufacturing a display panel according to claim 4, wherein,

the photomask comprises a first light-transmitting region, a second light-transmitting region and a third light-transmitting region,

patterning the dielectric layer in the bending region through the first light-transmitting region to expose the substrate layer;

patterning the dielectric layer in the display area through the second light-transmitting area to form the first through hole;

patterning the dielectric layer in the display area through the third light-transmitting area to form the second through hole;

wherein the light transmittance of the third light-transmitting region is smaller than the light transmittance of the first light-transmitting region;

the light transmittance of the second light transmission region is smaller than that of the third light transmission region.

6. The method for manufacturing a display panel according to claim 4, wherein,

after the dielectric layer is subjected to the patterning treatment step, the method further comprises the following steps:

forming a passivation layer on the display metal layer, extending to the surface of the dielectric layer and located in the display area;

forming a second flat layer on the passivation layer and located in the display region; wherein the first planarization layer and the second planarization layer are formed in the same process step;

Patterning the second flat layer to form a third through hole;

forming a second conductive layer in the third through hole and extending the surface of the second flat layer; wherein the first conductive layer and the second conductive layer are formed in the same process step;

forming an anode layer on the second flat layer and located in the display area;

forming a second pixel defining layer on the anode layer and extending to the surface of the second flat layer; wherein the first pixel definition layer and the second pixel definition layer are formed in the same process step;

patterning the second pixel defining layer to form an opening, wherein the opening is used for exposing the anode layer.

7. A preparation method of a display panel is characterized in that the display panel is defined with a display area and a bending area; the preparation method comprises the following steps:

forming a bending metal layer on the substrate layer and located in the bending area;

Forming a first conductive layer on the first flat layer and extending to the inner wall of the groove and located in the bending region; and

wherein after the step of forming the substrate layer, further comprising:

forming a barrier layer on the substrate layer and in the display region;

forming a shading conductive layer on the barrier layer and located in the display area; wherein, the shading conductive layer and the bending metal layer are formed in the same process step;

forming a buffer layer on the shading conductive layer, extending to the surface of the barrier layer and located in the display area;

forming an insulating layer on the semiconductor layer and located in the thin film transistor region of the display region;

forming a dielectric layer on the gate layer and the semiconductor layer, extending to the surface of the buffer layer and located in the display region;

patterning the dielectric layer by using a photomask to form a first through hole and a second through hole; the first through hole penetrates through the surface of the semiconductor layer and is positioned in a thin film transistor area of the display area; the second through hole penetrates through the surface of the shading conductive layer and is positioned in a thin film transistor area and a capacitor area of the display area;

forming a display metal layer on the substrate layer and located in the display area, wherein the display metal layer comprises a source-drain electrode layer and a metal connecting layer, the source-drain electrode layer is connected to the semiconductor layer through a first through hole, and the metal connecting layer is connected to the shading conductive layer through a second through hole;

Patterning the second flat layer to form a third through hole;

patterning the second pixel defining layer to form an opening, wherein the opening is used for exposing the anode layer;