CN114171518A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN114171518A CN114171518A CN202010956261.6A CN202010956261A CN114171518A CN 114171518 A CN114171518 A CN 114171518A CN 202010956261 A CN202010956261 A CN 202010956261A CN 114171518 A CN114171518 A CN 114171518A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
- H01L27/0924—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823821—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823871—Complementary field-effect transistors, e.g. CMOS interconnection or wiring or contact manufacturing related aspects
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A semiconductor structure and a forming method thereof are provided, wherein the method comprises the following steps: providing a substrate; forming a plurality of source-drain structures in the substrate, forming a plurality of gate structures, a first protection structure located on the top surface of each gate structure, a first conductive structure located between adjacent gate structures, a second protection structure located on the top surface of each first conductive structure, and an initial first side wall located between each gate structure and each first conductive structure on the substrate, wherein the initial first side wall is also located between each first protection structure and each second protection structure, the source-drain structures are located in the substrate on two sides of each gate structure, and the first conductive structures are located on the source-drain structures; etching the initial first side wall to form a first side wall and an opening, wherein the opening exposes the side wall surface of the first protection structure, the side wall surface of the second protection structure and the top surface of the first side wall; and forming a second side wall in the opening. Thus, the reliability of the formed semiconductor structure is improved.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density and higher integration. Devices are currently being widely used as the most basic semiconductor devices.
Generally, in the manufacturing process of a semiconductor device, a plug (Diffusion Contact) electrically connected to a source-drain doping layer is formed in an active region, and a plug (Gate Contact) electrically connected to a Gate is formed outside the active region, so that the semiconductor device is electrically connected to an external circuit, and at the same time, the distance between the plug electrically connected to the source-drain doping layer and the plug electrically connected to the Gate is increased, thereby reducing the risk of short circuit. On the basis, a method for forming a plug electrically connected with a grid electrode in an active region is provided, and the plug electrically connected with the grid electrode and the plug electrically connected with a source-drain doping layer are formed in the active region, so that the area occupied by a semiconductor device can be reduced, and the integration level of the semiconductor device is improved.
However, the reliability of the semiconductor structure formed by the prior art needs to be improved.
Disclosure of Invention
The invention provides a semiconductor structure and a forming method thereof, which aims to improve the reliability of the formed semiconductor structure.
To solve the above technical problem, an aspect of the present invention provides a semiconductor structure, including: a substrate; a plurality of gate structures on the substrate; the source-drain structures are positioned in the substrate at two sides of the grid structure; the first protection structure is positioned on the top surface of the grid structure; the first conductive structure is positioned between the adjacent grid structures and positioned on the source drain structure; a second protective structure on the top surface of the first conductive structure; the first side wall is positioned between the grid structure and the first conductive structure; and the second side wall is positioned on the top surface of the first side wall, and the second side wall is also positioned between the first protection structure and the second protection structure.
Optionally, the width of the top of the second sidewall is greater than the width of the first sidewall.
Optionally, on a plane perpendicular to the extending direction of the gate structure, the projection shape of the second sidewall is a trapezoid with a top width larger than a bottom width.
Optionally, on a plane perpendicular to the extending direction of the gate structure, the projection shape of the second sidewall is rectangular.
Optionally, in the trapezoid, a distance between a top edge of the first protection structure and a side wall surface of the adjacent first side wall is 1 angstrom to 30 angstrom.
Optionally, in the trapezoid, a distance between a top edge of the second protection structure and a side wall surface of the adjacent first side wall is 1 angstrom to 30 angstrom.
Correspondingly, the technical solution of the present invention further provides a method for forming the semiconductor structure, including: providing a substrate; forming a plurality of source-drain structures in the substrate, forming a plurality of gate structures, a first protection structure located on the top surface of each gate structure, a first conductive structure located between adjacent gate structures, a second protection structure located on the top surface of each first conductive structure, and an initial first side wall located between each gate structure and each first conductive structure on the substrate, wherein the initial first side wall is also located between each first protection structure and each second protection structure, the source-drain structures are located in the substrate on two sides of each gate structure, and the first conductive structures are located on the source-drain structures; etching the initial first side wall to form a first side wall and an opening, wherein the opening exposes the side wall surface of the first protection structure, the side wall surface of the second protection structure and the top surface of the first side wall; and forming a second side wall in the opening.
Optionally, the maximum width of the second sidewall is greater than the width of the first sidewall.
Optionally, the method for forming the opening further includes: and etching at least one of the side wall of the first protection structure and the side wall of the second protection structure at the same time of etching the initial first side wall or after etching the initial first side wall.
Optionally, the method further includes: before forming the first side wall, a first dielectric layer is formed on the surface of the substrate, and the first dielectric layer is also positioned on the side wall surfaces of the grid structure, the first protection structure, the first conductive structure and the second protection structure.
Optionally, the method further includes: after the second side wall is formed, etching at least part of the first protection structure, forming a first conductive opening in the first dielectric layer, wherein the bottom of the first conductive opening is exposed out of the top surface of the grid structure; and forming a second conductive structure in the first conductive opening.
Optionally, the method further includes: after forming the second side wall, etching at least part of the second protection structure, forming a second conductive opening in the first dielectric layer, wherein the bottom of the second conductive opening is exposed out of the top surface of the first conductive structure; and forming a third conductive structure in the second conductive opening.
Optionally, the method further includes: and forming a second dielectric layer on the surfaces of the first dielectric layer, the first protection structure, the second protection structure and the second side wall after the second side wall is formed.
Optionally, the material of the first protection structure includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.
Optionally, the material of the second protection structure includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.
Optionally, the material of the first sidewall includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, a low dielectric constant medium, and an air gap.
Optionally, the material of the second sidewall includes one or more of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride, and aluminum oxide.
Optionally, the material of the gate structure includes metal or polysilicon.
Optionally, the base includes a substrate and a plurality of fin structures located on the substrate, and the gate structure crosses over the fin structures.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the method for forming the semiconductor structure provided by the technical scheme of the invention, the initial first side wall is etched to form the first side wall and the opening, the side wall surface of the first protection structure, the side wall surface of the second protection structure and the top surface of the first side wall are exposed by the opening, and the second side wall is formed in the opening. On one hand, when the first protection structure and the second protection structure are etched, the first side wall can be protected by the second side wall, the loss of the first side wall is reduced, and the possibility of exposing the side wall surface of the first conductive structure or the grid structure is reduced, so that the short circuit risk between the grid structure and the first conductive structure is reduced, and the reliability of the semiconductor structure is improved. On the other hand, because the first side wall and the second side wall are formed respectively, the materials of the first side wall and the second side wall are selected more freely, and the first side wall and the second side wall can be made of different materials. Therefore, by selecting the material of the second side wall, when the first protection structure and the second protection structure are etched, the etching selection ratio between the first protection structure and the second side wall and between the second protection structure and the second side wall are respectively increased, so that the loss of the second side wall is reduced, the blocking of the second side wall in the etching process is increased, the first side wall can be better protected by the second side wall, the loss of the first side wall is reduced, the short circuit risk between the grid structure and the first conductive structure is reduced, and the reliability of the semiconductor structure is improved.
Furthermore, because the width of the top of the second side wall is greater than that of the first side wall, when the first protection structure and the second protection structure are etched, the allowance of the second side wall which can be lost is increased, so that the blocking capability of the second side wall to the etching process is improved, the first side wall is better protected, the short circuit risk between the grid structure and the first conductive structure is further reduced, and the reliability of the semiconductor structure is improved.
Drawings
FIGS. 1-2 are schematic cross-sectional views of steps in a method of forming a semiconductor structure;
FIG. 3 is a cross-sectional schematic view of a step in another method of forming a semiconductor structure;
FIGS. 4-14 are cross-sectional structural illustrations of steps in a method of forming a semiconductor structure in accordance with an embodiment of the present invention;
FIG. 15 is a cross-sectional view of a step in a method of forming a semiconductor structure in another embodiment of the invention.
Detailed Description
As mentioned in the background, the reliability of semiconductor structures still needs to be improved, and the reason for the poor reliability of semiconductor structures is described in detail below with reference to the accompanying drawings.
It should be noted that "surface" in this specification is used to describe a relative positional relationship in space, and is not limited to whether or not it is in direct contact.
Fig. 1-2 are schematic cross-sectional views of steps of a method for forming a semiconductor structure.
Referring to fig. 1, a substrate 100 is provided, the substrate 100 includes an active region a, and the substrate 100 has a plurality of mutually discrete fins (not shown); a plurality of gate structures 110 crossing the fin portions, source-drain doped regions 101 located at two sides of the gate structures 110, gate protection structures 111 located on the top surfaces of the gate structures 110, interconnect structures 120 located on the surfaces of the source-drain doped regions 101, etch stop layers 130 located between the gate structures 110 and the side wall surfaces of the interconnect structures 120, conductive protection structures 121 located on the top surfaces of the interconnect structures 120 and the top surfaces of the etch stop layers 130, and dielectric structures (not shown) surrounding the gate structures 110 are formed on the substrate 100.
Referring to fig. 2, the gate protection structure 111 on a portion of the active region a is removed to form a first plug opening (not shown), and the bottom of the first plug opening exposes the gate structure 110; removing part of the conductive protection structure 121 of the active region a to form a second plug opening 141, wherein the bottom of the second plug opening 141 is exposed out of the interconnect structure 120; a first plug (not shown) is formed within the first plug opening and a second plug (not shown) is formed within the second plug opening 141.
In the embodiment shown in fig. 1 to 2, by increasing the width of the conductive protection structure 121 (not only on the top surface of the interconnect structure 120, but also on the top surface of the etch stop layer 130), when the gate protection structure 111 is etched to form the first plug opening, the etching process is better prevented from wearing the etch stop layer 130, and the risk of short circuit between the first plug and the interconnect structure 120 is reduced.
However, on the one hand, in order to increase the width of the conductive protection structure 121, the amount of the loss of the etching stop layer 130 during etching the conductive protection structure 121 is small, and therefore, during etching the conductive protection structure 121, the etching stop layer 130 is easily worn to expose the sidewall surface of the gate structure 110 (as shown in the region B of fig. 2), thereby causing a short circuit between the second plug and the gate structure 110, that is, causing a short circuit between the interconnect structure 120 and the gate structure 110, and thus causing poor reliability of the semiconductor structure.
In order to solve the above problem, another method for forming a semiconductor structure is proposed based on the embodiments shown in fig. 1 to fig. 2, please refer to fig. 3, which increases the height of the etch stop layer 131 (the etch stop layer 131 is also located between the conductive protection structure 122 and the gate protection structure 111), so as to increase the amount of the loss of the etch stop layer 131 when the conductive protection structure 122 is etched, thereby improving the risk of short circuit between the second plug and the gate structure 110.
However, on one hand, since the material of the etch stop layer 131 may affect the electrical performance of the gate structure 120, the material selection of the etch stop layer 131 is limited, so that it is difficult to have a large etch selectivity ratio between the material of the gate protection structure 111 and the material of the etch stop layer 131 in the process of etching the gate protection structure 111; on the other hand, in order to increase the contact area between the first plug and the gate structure to reduce the contact resistance, the patterned layer for forming the first plug opening is exposed not only the gate protection structure 111 but also the etch stop layer 131, so that when the gate protection structure 111 is etched, the etch stop layer 131 is easily exposed to the sidewall surface of the interconnection structure 120 after being worn, thereby causing a short circuit between the first plug and the interconnection structure 120, that is, causing the interconnection structure 120 and the gate structure 110 to be short-circuited, and causing poor reliability of the semiconductor structure.
In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, in which an initial first sidewall is etched to form a first sidewall and an opening, the opening exposes a sidewall surface of a first protection structure, a sidewall surface of a second protection structure, and a top surface of the first sidewall, and a second sidewall is formed in the opening, thereby improving reliability of the semiconductor structure.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 4 to 14 are schematic cross-sectional views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Referring to fig. 4, a substrate is provided.
In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 located on the substrate 200 and separated from each other.
The material of the substrate 200 comprises a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In this embodiment, before the dummy gate structure is formed subsequently, an isolation dielectric layer (not shown) is formed on the surface of the substrate 200, and the isolation dielectric layer is also located on a partial side wall surface of the fin structure 201, so that the substrate 200 can be electrically insulated from other semiconductor structures, and adjacent fin structures 201 can be electrically insulated from each other.
Then, a plurality of source-drain structures are formed in the substrate, a plurality of grid structures, first protection structures located on the top surfaces of the grid structures, first conductive structures located between adjacent grid structures, second protection structures located on the top surfaces of the first conductive structures, and initial first side walls located between the grid structures and the first conductive structures are formed on the substrate, the initial first side walls are further located between the first protection structures and the second protection structures, the source-drain structures are located in the substrate on two sides of the grid structures, and the first conductive structures are located on the source-drain structures. Please refer to fig. 5 to fig. 9.
Referring to fig. 5, a plurality of source/drain structures 220 are formed in the substrate, and an initial first sidewall 230 is formed on the substrate.
In this embodiment, the method for forming the initial first sidewall spacers 230 includes: forming a plurality of dummy gate structures 210 on the surface of the substrate, wherein the dummy gate structures 210 cross over the fin structure 201; forming an initial first sidewall material layer (not shown) on the surface of the dummy gate structure 210 and the substrate surface; and etching back the initial first sidewall material layer until the top surface of the dummy gate structure 210 and the surface of the substrate are exposed, thereby forming an initial first sidewall 230.
In this embodiment, the dummy gate structure 210 can play a positioning role in the subsequent formation of a gate structure.
In other embodiments, the method for forming the initial first sidewall spacer includes: forming a plurality of grid structures on the surface of the substrate, wherein the grid structures are part of the structure of the semiconductor device; and forming an initial first side wall on the side wall surface of the grid structure.
In this embodiment, the process of forming the initial first sidewall material layer includes a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
In this embodiment, the process of etching the initial first sidewall material layer includes at least one of a dry etching process and a wet etching process.
In this embodiment, the material of the dummy gate structure 210 includes polysilicon.
In this embodiment, the method for forming the dummy gate structure 210 includes: forming a dummy gate material film (not shown) on the substrate covering the surface of the fin structure 201; and patterning the dummy gate material film until the surface of the substrate is exposed, forming a dummy gate structure 210 crossing the fin portion structure 201 on the substrate, wherein the top surface of the dummy gate structure 210 is higher than the top surface of the fin portion structure 201.
Referring to fig. 6, a plurality of source/drain structures 220 are formed in the substrate on both sides of the dummy gate structure 210.
In this embodiment, the method for forming the source/drain structure 220 includes: after the initial first side wall 230 is formed, the dummy gate structure 210 and the initial first side wall 230 are used as masks, the fin structures 201 on two sides of the dummy gate structure 210 are etched, and a plurality of source and drain openings (not shown) are formed in the fin structures 201; and forming a source-drain structure 220 in the source-drain opening by adopting an epitaxial growth process.
In this embodiment, the top surface of the source/drain structure 220 is flush with or higher than the top surface of the fin structure 201.
In other embodiments, the method for forming the source-drain structure includes: and performing ion implantation on the fin part structures on two sides of the pseudo gate structure by taking the pseudo gate structure and the initial first side wall as masks to form doped regions on two sides of the pseudo gate structure, and taking the doped regions as the source and drain structures.
In this embodiment, the process of etching the fin structures 201 on the two sides of the dummy gate structure 210 includes at least one of a dry etching process and a wet etching process.
Referring to fig. 7, after the source/drain structure 220 is formed, a first dielectric layer 240 is formed on the substrate surface.
Specifically, in this embodiment, the first dielectric layer 240 is located on the surface of the source/drain structure 220 and the surface of the isolation dielectric layer, and the first dielectric layer 240 is also located on the sidewall surface of the initial first sidewall 230.
The method for forming the first dielectric layer 240 includes: forming a first dielectric material layer (not shown) on the surface of the source-drain structure 220, the surface of the isolation dielectric layer, the top surface of the dummy gate structure 210, and the surface of the initial first sidewall 230; the first dielectric material layer is planarized until the top surface of the dummy gate structure 210 and the top surface of the initial first sidewall 230 are exposed.
In this embodiment, the process of forming the first dielectric material layer includes: a spin coating process, a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.
In this embodiment, the process of planarizing the first dielectric material layer includes: at least one of a chemical mechanical polishing process, a dry etching process, or a wet etching process.
In this embodiment, the material of the first dielectric layer 240 includes silicon oxide.
In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
With reference to fig. 7, after the first dielectric layer 240 is formed, the dummy gate structure 210 is removed to form a gate opening (not shown); an initial gate structure 250 is formed within the gate opening.
Since the initial gate structure 250 is formed in the gate opening, the first dielectric layer 240 is located on the sidewall surface of the initial gate structure 250. Correspondingly, the first dielectric layer 240 is also located on the sidewall surfaces of the subsequently formed gate structure and the first protection structure.
Specifically, in the present embodiment, the method for forming the initial gate structure 250 includes: forming a gate structure material layer (not shown) in the gate opening, on the surface of the first dielectric layer 240, and on the top surface of the initial first sidewall spacers 230; the gate structure material layer is planarized until the top surface of the initial first sidewall 230 and the surface of the first dielectric layer 240 are exposed.
The gate structure material layer includes: a gate dielectric material layer on the inner wall surface of the gate opening, the surface of the first dielectric layer 240, and the top surface of the initial first sidewall 230; the work function material layer is positioned on the surface of the gate dielectric material layer; and the gate electrode material layer is positioned on the surface of the work function material layer and is filled in the gate opening.
The process for forming the gate dielectric material layer includes an oxidation process, a deposition process, and the like, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, and the like.
The process of forming the work function material layer includes a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The process of forming the gate electrode material layer includes a metal plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The process for planarizing the gate electrode material layer, the work function material layer and the gate dielectric material layer includes a back etching process or a chemical mechanical polishing process.
Referring to fig. 8, the initial gate structure 250 is etched to form a gate structure 251 crossing the fin structure 201, and the thickness of the gate structure 251 is smaller than the depth of the gate opening in the direction perpendicular to the substrate surface; after the gate structure 251 is formed, a first protection structure 260 is formed in a gate opening at the top of the gate structure 251, the first protection structure 260 is located on the top surface of the gate structure 251, and the source and drain structures 220 are located in the substrate at two sides of the gate structure 251.
Specifically, in the present embodiment, the source/drain structures 220 are located in the fin structures 201 on two sides of the gate structure 251.
In this embodiment, the process of etching the initial gate structure 250 includes at least one of a dry etching process and a wet etching process.
In this embodiment, the gate structure 251 includes: a gate dielectric layer (not shown) on the inner wall surface of the gate opening; a work function layer (not shown) on the surface of the gate dielectric layer; a gate electrode layer (not shown) on the surface of the work function layer, the gate electrode layer filling the gate opening.
The material of the gate dielectric layer comprises a high dielectric constant material (the dielectric constant is larger than 3.9). The high dielectric constant material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
The material of the gate electrode layer includes a metal material such as: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.
The material of the work function layer comprises titanium nitride, tantalum nitride or titanium aluminum.
In other embodiments, the material of the gate structure comprises polysilicon.
In this embodiment, the method for forming the first protection structure 260 includes: forming a first protection structure material layer (not shown) in the gate opening on the top surface of the gate structure 251 and on the surface of the first dielectric layer 240; and planarizing the first protection structure material layer until the surface of the first dielectric layer 240 is exposed.
The process for forming the first protection structure material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The process for flattening the first protection structure material layer comprises a back etching process or a chemical mechanical polishing process and the like.
The first protection structure 260 is made of a different material than a subsequently formed second protection structure.
In the present embodiment, the material of the first protection structure 260 includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.
The first protection structure 260 is used for protecting the gate structure 251, so as to reduce damage of the gate structure 251 to processes such as etching in a subsequent semiconductor process, and at the same time, enable better insulation between the gate structure 251 and a conductive structure other than a first conductive structure to be formed subsequently.
Referring to fig. 9, a first conductive structure 270 is formed between adjacent gate structures 251, where the first conductive structure 270 is located on the source/drain structure 220; a second protection structure 280 is formed on the top surface of the first conductive structure 270, and the initial first sidewall 230 is located between the gate structure 251 and the first conductive structure 270, and the initial first sidewall 230 is further located between the first protection structure 260 and the second protection structure 280.
The method of forming the first conductive structure 270 includes: etching the first dielectric layer 240 between the adjacent gate structures 251, and forming a third conductive opening (not shown) in the first dielectric layer 240, wherein the bottom of the third conductive opening exposes the surface of the source drain structure 220; forming a first conductive structure material layer (not shown) in the third conductive opening, the top surface of the initial first sidewall 230, and the surface of the first protection structure 260; the first conductive structure material layer is etched back until the surface of the first conductive structure material layer is lower than the top surface of the initial first sidewall 230.
In this embodiment, the top surface of the first conductive structure 270 is lower than the top surface of the first protection structure 260, and the top surface of the first conductive structure 270 is higher than the bottom surface of the first protection structure 260.
The process of forming the first layer of conductive structure material includes: a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process, or the like, or a metal plating process such as a selective metal plating process or the like.
In this embodiment, the process of etching back the first conductive structure material layer includes at least one of a dry etching process and a wet etching process.
In this embodiment, the material of the first conductive structure 270 includes metal materials, such as: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.
The method of forming the second protection structure 280 includes: after forming the first conductive structure 270, forming a second protection structure material layer (not shown) in the third conductive opening on the top of the first conductive structure 270, and on the top surface of the initial first sidewall 230 and the surface of the first protection structure 260; the second protection structure material layer is planarized until the top surface of the initial first sidewall 230 and the top surface of the first protection structure 260 are exposed.
Since the first conductive structure 270 and the second protective structure 280 are located in the third conductive opening, the first dielectric layer 240 is also located on the sidewall surfaces of the first conductive structure 270 and the second protective structure 280.
The process of forming the second protective structure material layer includes a spin coating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The process for flattening the second protection structure material layer comprises a back etching process or a chemical mechanical grinding process and the like.
In the present embodiment, the material of the second protection structure 280 includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.
Referring to fig. 10, the initial first sidewall 230 is etched to form a first sidewall 231 and an opening 290, wherein the opening 290 exposes the sidewall surface of the first protection structure 260, the sidewall surface of the second protection structure 280 and the top surface of the first sidewall 231.
Specifically, the top surface of the first sidewall 231 is higher than the bottom surface of the first protection structure 260 and the bottom surface of the second protection structure 280.
The opening 290 provides space for the subsequent formation of the second sidewall.
As the initial first sidewall 230 is etched, the first sidewall 231 and the opening 290 are formed, the opening 290 exposes the sidewall surface of the first protection structure 260, the sidewall surface of the second protection structure 280 and the top surface of the first sidewall 231, and a second sidewall is formed in the opening 290 subsequently. On the one hand, when the first protection structure 260 and the second protection structure 280 are etched, the first sidewall 231 can be protected by the second sidewall, so that the loss of the first sidewall 231 is reduced, and the possibility of exposing the sidewall surface of the first conductive structure 270 or the gate structure 251 is reduced, thereby reducing the risk of short circuit between the gate structure 251 and the first conductive structure 270, and improving the reliability of the semiconductor structure. On the other hand, since the first side wall 231 and the second side wall are formed separately, the materials of the first side wall 231 and the second side wall are selected more freely, and the first side wall 231 and the second side wall can be made of different materials. Therefore, by selecting the material of the second sidewall, when the first protection structure 260 and the second protection structure 280 are etched, the etching selection ratios between the first protection structure 260 and the second sidewall 290 and between the second protection structure 280 and the second sidewall 290 are respectively increased, so as to reduce the loss of the second sidewall 290, increase the ability of the second sidewall 290 to block the etching process, enable the second sidewall 290 to better protect the first sidewall 231, and reduce the loss of the first sidewall 231, thereby reducing the risk of short circuit between the gate structure 251 and the first conductive structure 270, and improving the reliability of the semiconductor structure.
Moreover, since the ability of the second sidewall 290 to block the etching process is increased, the size of the first conductive opening for providing a space for the second conductive structure and the size of the second conductive opening for providing a space for the third conductive structure can be increased while ensuring the reliability of the semiconductor structure in the subsequent etching process for forming the second conductive structure and the third conductive structure, thereby increasing the process window for forming the second conductive structure and the third conductive structure, reducing the process difficulty, and simultaneously reducing the contact resistance between the second conductive structure and the gate structure 251 and the contact resistance between the third conductive structure and the first conductive structure 270, and improving the performance of the semiconductor structure.
In this embodiment, the method for forming the opening 290 further includes: at least one of the sidewalls of the first protection structure 260 and the sidewalls of the second protection structure 280 is etched at the same time or after the initial first sidewall spacers 230 are etched. Therefore, the width of the opening 290 can be further enlarged to provide a larger space for forming the second sidewall later, and further, the maximum width of at least the top of the second sidewall is greater than the width of the first sidewall 231.
Because the width of the top of the second sidewall is greater than the width of the first sidewall 231, when the first protection structure 260 and the second protection structure 280 are etched, the allowance of the second sidewall that can be lost is increased, so that the blocking capability of the second sidewall to the etching process is improved, the first sidewall 231 is better protected, the risk of short circuit between the gate structure 251 and the first conductive structure 270 is further reduced, and the reliability of the semiconductor structure is improved.
In other embodiments, the etching is not performed among the sidewalls of the first protective structure and the sidewalls of the second protective structure.
In this embodiment, the process of etching the initial first sidewall spacers 230 includes at least one of a dry etching process and a wet etching process.
In this embodiment, the process of etching at least one of the sidewall of the first protection structure 260 and the sidewall of the second protection structure 280 includes at least one of a dry etching process and a wet etching process.
In this embodiment, the material of the first sidewall spacers 231 includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, low-k dielectric, and air gap.
Referring to fig. 11, a second sidewall 291 is formed in the opening 290.
The method for forming the second sidewall 291 includes: forming a second layer of sidewall material (not shown) within the opening 290 and on top of the first protective structure 260 and the second protective structure 280; the second sidewall material layer is planarized until the top surfaces of the first protection structures 260 and the second protection structures 280 are exposed.
In this embodiment, the width of the top of the second sidewall 291 is greater than the width of the first sidewall 231.
In this embodiment, on a plane perpendicular to the extending direction of the gate structure 251, the projection shape of the second sidewall 291 is a trapezoid with a top width larger than a bottom width.
In the trapezoid, a distance a between a top edge of the first protection structure 260 and a sidewall surface of the adjacent first sidewall 231 is 1 to 30 angstroms.
In the trapezoid, a distance b between a top edge of the second protection structure 280 and a sidewall surface of the adjacent first sidewall 231 is 1 angstrom to 30 angstrom.
It should be noted that, according to the requirement for the barrier performance of the second sidewall 291, the distance a and the distance b may be equal or unequal.
In another embodiment, the second sidewall 292 (shown in fig. 15) has a rectangular projection shape on a plane perpendicular to the extending direction of the gate structure 251. In the rectangle, a distance c between a top edge of the first protection structure 260 and a side wall surface of the adjacent first sidewall 231 is 1 to 30 angstroms. In the rectangle, a distance d between a top edge of the second protection structure 280 and a side wall surface of the adjacent first side wall 231 is 1 to 30 angstroms. It should be noted that, the distance c and the distance d may be equal or unequal according to the requirement of the barrier performance of the second sidewall 292.
In this embodiment, the process of forming the second sidewall material layer includes: a spin coating process, a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.
In this embodiment, the process of planarizing the second sidewall material layer includes: at least one of a chemical mechanical polishing process, a dry etching process, or a wet etching process.
In this embodiment, the material of the second sidewall 291 includes one or more of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride, and aluminum oxide.
Referring to fig. 12, after forming the second sidewall 291, a second dielectric layer 300 is formed on the surfaces of the first dielectric layer 240, the first protection structure 260, the second protection structure 280 and the second sidewall 291.
The process for forming the second dielectric layer 300 comprises: a spin coating process, a deposition process such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process, etc.
In this embodiment, the material of the second dielectric layer 300 includes silicon oxide.
In other embodiments, the material of the second dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
On one hand, the second dielectric layer 300 protects the surface of the semiconductor structure and reduces the damage to the surface of the semiconductor structure in the subsequent etching process for forming the second conductive structure and the third conductive structure; in another aspect, support is provided for forming the second and third conductive structures.
In other embodiments, the second dielectric layer is not formed.
Referring to fig. 13, after forming the second sidewall 291, at least a portion of the first protection structure 260 is etched, a first conductive opening 310 is formed in the first dielectric layer 240, and a bottom of the first conductive opening 310 exposes a top surface of the gate structure 251; after forming the second sidewall 291, etching at least a portion of the second protection structure 280, and forming a second conductive opening 320 in the first dielectric layer 240, where the bottom of the second conductive opening 320 exposes the top surface of the first conductive structure 270.
Since the second dielectric layer 300 is formed in this embodiment, the first conductive opening 310 is also located in the second dielectric layer 300, and the second conductive opening 320 is also located in the second dielectric layer 300.
In the present embodiment, the first conductive opening 310 and the second conductive opening 320 are formed simultaneously.
The method of forming the first conductive opening 310 and the second conductive opening 320 includes: forming a conductive opening patterning layer (not shown) on the surface of the second dielectric layer 300, wherein the conductive opening patterning layer has a first opening (not shown) and a second opening (not shown), the bottom of the first opening exposes at least a portion of the surface of the second dielectric layer on the first protective structure 260, and the bottom of the second opening exposes at least a portion of the surface of the second dielectric layer on the second protective structure 280; and etching the second dielectric layer 300, the first dielectric layer 240, the first protection structure 260 and the second protection structure 280 by using the conductive opening patterning layer as a mask until the top surface of the gate structure 251 and the top surface of the first conductive structure 270 are exposed.
In this embodiment, the process of forming the first conductive opening 310 and the second conductive opening 320 includes at least one of a dry etching process or a wet etching process.
Referring to fig. 14, a second conductive structure 311 is formed in the first conductive opening 310; a third conductive structure 321 is formed within the second conductive opening 320.
The second conductive structure 311 is electrically interconnected with the gate structure 251.
The third conductive structure 321 is electrically interconnected with the first conductive structure 270.
In the present embodiment, the method of forming the second conductive structure 311 and the third conductive structure 321 includes: forming a conductive structure material layer (not shown) in the first conductive opening 310, the second conductive opening 320, and the surface of the second dielectric layer 300; and flattening the conductive structure material layer until the surface of the second dielectric layer 300 is exposed.
The process for forming the conductive structure material layer includes a metal plating process or a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
The process for flattening the conductive structure material layer comprises a back etching process or a chemical mechanical grinding process and the like.
In other embodiments, different patterned layers of conductive openings are formed on the surface of the second dielectric layer, respectively, and the first conductive opening and the second conductive opening are formed, respectively, and the second conductive structure and the third conductive structure are formed, respectively. The third conductive structure may be formed after the second conductive structure is formed, or the second conductive structure may be formed after the third conductive structure is formed. Continuing with the example of forming the third conductive structure after forming the second conductive structure, specifically, a first conductive opening patterned layer is formed on the surface of the second dielectric layer, the first conductive opening patterned layer has a first opening (not shown), and the bottom of the first opening exposes at least a portion of the surface of the second dielectric layer on the first protective structure; etching the second dielectric layer, the first dielectric layer and the first protection structure by taking the first conductive opening patterning layer as a mask until the top surface of the grid structure is exposed to form a first conductive opening; forming a second conductive structure in the first conductive opening; after forming the second conductive structure, forming a second conductive opening patterned layer on the surface of the second conductive structure and the surface of the second dielectric layer, where the second conductive opening patterned layer has a second opening (not shown), and the bottom of the second opening exposes at least part of the surface of the second dielectric layer on the second protective structure; etching the second dielectric layer 300, the first dielectric layer 240 and the second protection structure by using the second conductive opening patterning layer as a mask until the top surface of the first conductive structure 270 is exposed to form a second conductive opening; and forming a third conductive structure in the second conductive opening.
In this embodiment, the material of the second conductive structure 311 is the same as the material of the third conductive structure 321.
In other embodiments, the material of the second conductive structure 311 and the material of the third conductive structure 321 may also be different.
The material of the second conductive structure 311 includes metal materials, such as: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.
The material of the third conductive structure 321 includes metal materials, such as: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.
Accordingly, an embodiment of the present invention further provides a semiconductor structure formed by the above method, with reference to fig. 11, including: a substrate; a plurality of gate structures 251 on the substrate; a plurality of source/drain structures 220 located in the substrate at both sides of the gate structure 251; a first protection structure 260 on a top surface of the gate structure 251; the first conductive structure 270 is located between adjacent gate structures, and the first conductive structure 270 is located on the source drain structure 220; a second protective structure 280 on a top surface of the first conductive structure 270; a first sidewall 231 between the gate structure 351 and the first conductive structure 260; a second sidewall 291 on a top surface of the first sidewall 231, wherein the second sidewall 291 is further located between the first protection structure 260 and the second protection structure 280.
In this embodiment, the base includes a substrate 200 and a plurality of fin structures 201 located on the substrate 200 and separated from each other.
The material of the substrate 200 comprises a semiconductor material.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the substrate material comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group iii-v elements, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. The multielement semiconductor material composed of III-V group elements comprises InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP and the like.
In this embodiment, the material of the first sidewall spacers 231 includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, low-k dielectric, and air gap.
In this embodiment, the material of the second sidewall 291 includes one or more of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride, and aluminum oxide.
In this embodiment, the width of the top of the second sidewall 291 is greater than the width of the first sidewall 231.
In this embodiment, on a plane perpendicular to the extending direction of the gate structure 251, the projection shape of the second sidewall 291 is a trapezoid with a top width larger than a bottom width.
In the trapezoid, a distance a between a top edge of the first protection structure 260 and a sidewall surface of the adjacent first sidewall 231 is 1 to 30 angstroms.
In the trapezoid, a distance b between a top edge of the second protection structure 280 and a sidewall surface of the adjacent first sidewall 231 is 1 angstrom to 30 angstrom.
It should be noted that, according to the requirement for the barrier performance of the second sidewall 291, the distance a and the distance b may be equal or unequal.
In another embodiment, the second sidewall 292 (shown in fig. 15) has a rectangular projection shape on a plane perpendicular to the extending direction of the gate structure 251. In the rectangle, a distance c between a top edge of the first protection structure 260 and a side wall surface of the adjacent first sidewall 231 is 1 to 30 angstroms. In the rectangle, a distance d between a top edge of the second protection structure 280 and a side wall surface of the adjacent first side wall 231 is 1 to 30 angstroms. It should be noted that, the distance c and the distance d may be equal or unequal according to the requirement of the barrier performance of the second sidewall 292.
In the present embodiment, the first protection structure 260 and the second protection structure 280 are made of different materials.
In the present embodiment, the material of the first protection structure 260 includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.
In the present embodiment, the material of the second protection structure 280 includes one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.
In this embodiment, the source/drain structures 220 are located in the fin structures 201 on two sides of the gate structure 251.
In this embodiment, the top surface of the source/drain structure 220 is flush with or higher than the top surface of the fin structure 201.
In this embodiment, the gate structure 251 includes: a gate dielectric layer (not shown) on the inner wall surface of the gate opening; a work function layer (not shown) on the surface of the gate dielectric layer; a gate electrode layer (not shown) on the surface of the work function layer, the gate electrode layer filling the gate opening.
The material of the gate dielectric layer comprises a high dielectric constant material (the dielectric constant is larger than 3.9). The high dielectric constant material includes: hafnium oxide, zirconium oxide, hafnium silicon oxide, lanthanum oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, or the like.
The material of the gate electrode layer includes a metal material such as: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.
The material of the work function layer comprises titanium nitride, tantalum nitride or titanium aluminum.
In other embodiments, the material of the gate structure comprises polysilicon.
In this embodiment, the top surface of the first conductive structure 270 is lower than the top surface of the first protection structure 260, and the top surface of the first conductive structure 270 is higher than the bottom surface of the first protection structure 260.
In this embodiment, the material of the first conductive structure 270 includes metal materials, such as: one or more of tungsten, copper, tungsten, aluminum, titanium nitride and tantalum.
In this embodiment, the semiconductor structure further includes: an isolation dielectric layer (not shown) on the surface of the substrate 200, the isolation dielectric layer being further on a portion of the sidewall surface of the fin structure 201, thereby enabling electrical insulation between the substrate 200 and other semiconductor structures and between adjacent fin structures 201.
In this embodiment, the semiconductor structure further includes: a first dielectric layer 240 on the surface of the isolation dielectric layer, wherein the first dielectric layer 240 is further located on the sidewall surface of the first sidewall 231, the sidewall surface of the first protection structure 260, and the sidewall surface of the second protection structure 280.
In this embodiment, the material of the first dielectric layer 240 includes silicon oxide.
In other embodiments, the material of the first dielectric layer includes at least one of SiOCH, SiOH, and SiCN.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (19)
1. A semiconductor structure, comprising:
a substrate;
a plurality of gate structures on the substrate;
the source-drain structures are positioned in the substrate at two sides of the grid structure;
the first protection structure is positioned on the top surface of the grid structure;
the first conductive structure is positioned between the adjacent grid structures and positioned on the source drain structure;
a second protective structure on the top surface of the first conductive structure;
the first side wall is positioned between the grid structure and the first conductive structure;
and the second side wall is positioned on the top surface of the first side wall, and the second side wall is also positioned between the first protection structure and the second protection structure.
2. The semiconductor structure of claim 1, wherein a width of a top portion of the second sidewall is greater than a width of the first sidewall.
3. The semiconductor structure of claim 2, wherein the second sidewall has a trapezoidal projection shape with a top width greater than a bottom width in a plane perpendicular to the extending direction of the gate structure.
4. The semiconductor structure of claim 2, wherein a projected shape of the second sidewall is rectangular in a plane perpendicular to an extending direction of the gate structure.
5. The semiconductor structure of claim 3 or 4, wherein a distance between a top edge of the first protection structure and a side wall surface of an adjacent first side wall is 1 to 30 angstroms.
6. The semiconductor structure of claim 3 or 4, wherein a distance between a top edge of the second protection structure and a side wall surface of the adjacent first side wall is 1 to 30 angstroms.
7. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a plurality of source-drain structures in the substrate, forming a plurality of gate structures, a first protection structure located on the top surface of each gate structure, a first conductive structure located between adjacent gate structures, a second protection structure located on the top surface of each first conductive structure, and an initial first side wall located between each gate structure and each first conductive structure on the substrate, wherein the initial first side wall is also located between each first protection structure and each second protection structure, the source-drain structures are located in the substrate on two sides of each gate structure, and the first conductive structures are located on the source-drain structures;
etching the initial first side wall to form a first side wall and an opening, wherein the opening exposes the side wall surface of the first protection structure, the side wall surface of the second protection structure and the top surface of the first side wall;
and forming a second side wall in the opening.
8. The method for forming the semiconductor structure according to claim 7, wherein a maximum width of the second side wall is larger than a width of the first side wall.
9. The method of forming a semiconductor structure of claim 8, wherein the method of forming the opening further comprises: and etching at least one of the side wall of the first protection structure and the side wall of the second protection structure at the same time of etching the initial first side wall or after etching the initial first side wall.
10. The method of forming a semiconductor structure of claim 8, further comprising: before forming the first side wall, a first dielectric layer is formed on the surface of the substrate, and the first dielectric layer is also positioned on the side wall surfaces of the grid structure, the first protection structure, the first conductive structure and the second protection structure.
11. The method of forming a semiconductor structure of claim 10, further comprising: after the second side wall is formed, etching at least part of the first protection structure, forming a first conductive opening in the first dielectric layer, wherein the bottom of the first conductive opening is exposed out of the top surface of the grid structure; and forming a second conductive structure in the first conductive opening.
12. The method of forming a semiconductor structure of claim 10, further comprising: after forming the second side wall, etching at least part of the second protection structure, forming a second conductive opening in the first dielectric layer, wherein the bottom of the second conductive opening is exposed out of the top surface of the first conductive structure; and forming a third conductive structure in the second conductive opening.
13. The method of forming a semiconductor structure of claim 10, further comprising: and forming a second dielectric layer on the surfaces of the first dielectric layer, the first protection structure, the second protection structure and the second side wall after the second side wall is formed.
14. The method of claim 7, wherein the material of the first protective structure comprises one or more of silicon nitride, silicon carbo-nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide in combination.
15. The method of claim 7, wherein the material of the second protective structure comprises one or more of silicon nitride, silicon carbo-nitride, silicon oxycarbide, aluminum nitride, and aluminum oxide.
16. The method of claim 7, wherein the material of the first sidewall spacers comprises one or more of silicon nitride, silicon carbide nitride, silicon oxycarbide, silicon carbide, low dielectric constant media, and air gaps.
17. The method of claim 7, wherein the material of the second sidewall spacers comprises one or more of silicon carbide nitride, silicon oxycarbide, silicon carbide, aluminum nitride, and aluminum oxide.
18. The method of forming a semiconductor structure of claim 7, wherein a material of the gate structure comprises a metal or polysilicon.
19. The method of claim 7, wherein the base comprises a substrate and a plurality of fin structures on the substrate, and the gate structure crosses over the fin structures.
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