CN114171389A - Manufacturing method of semiconductor device, memory and storage system - Google Patents
Manufacturing method of semiconductor device, memory and storage system Download PDFInfo
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- CN114171389A CN114171389A CN202111433860.0A CN202111433860A CN114171389A CN 114171389 A CN114171389 A CN 114171389A CN 202111433860 A CN202111433860 A CN 202111433860A CN 114171389 A CN114171389 A CN 114171389A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The embodiment of the invention discloses a manufacturing method of a semiconductor device, the semiconductor device, a memory and a storage system. The method comprises the following steps: providing a first semiconductor structure and a dielectric layer covering the first semiconductor structure; the first semiconductor structure comprises a first gate structure, a first source region and a first drain region which are positioned at two opposite sides of the first gate structure; forming a sacrificial layer on the dielectric layer, wherein the surface of one side of the sacrificial layer, which is far away from the dielectric layer, is flush; forming a mask layer on the sacrificial layer, wherein the mask layer is provided with a first mask opening; and etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose part of the first gate structure, part of the first source region and part of the first drain region to be used as a first ohmic contact region of the first semiconductor structure. The embodiment of the invention can reduce the ohmic contact area of the semiconductor structure and reduce the leakage risk.
Description
Technical Field
The embodiment of the invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device, the semiconductor device, a memory and a storage system.
Background
In a semiconductor device, an ohmic contact region of a transistor (particularly, a high voltage transistor) cannot be too large, but due to the thickness of the photoresist layer, the size of an opening in the photoresist layer cannot be reduced to a target size, so that the ohmic contact region formed on the transistor through the opening in the photoresist layer cannot be reduced to a desired size, and after the ohmic contact layer is formed on the ohmic contact region, there may be a risk of leakage.
Disclosure of Invention
Embodiments of the present invention provide a method for manufacturing a semiconductor device, a memory, and a storage system, which can reduce an ohmic contact region of a semiconductor structure and reduce a risk of leakage.
The embodiment of the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a first semiconductor structure and a dielectric layer covering the first semiconductor structure; the first semiconductor structure comprises a first gate structure, a first source region and a first drain region which are positioned at two opposite sides of the first gate structure;
forming a sacrificial layer on the dielectric layer, wherein the surface of one side of the sacrificial layer, which is far away from the dielectric layer, is flush;
forming a mask layer on the sacrificial layer, wherein the mask layer is provided with a first mask opening;
and etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose part of the first gate structure, part of the first source region and part of the first drain region to be used as a first ohmic contact region of the first semiconductor structure.
Further, the mask layer comprises a photoresist layer and an antireflection layer, and the first mask opening comprises a first opening and a second opening;
the step of forming a mask layer on the sacrificial layer includes:
sequentially forming the anti-reflection layer and the photoresist layer on the sacrificial layer, wherein the photoresist layer is provided with the first opening;
forming the second opening in the antireflection layer through the first opening, the size of the second opening being smaller than the size of the first opening.
Further, the step of etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose a portion of the first gate structure, a portion of the first source region, and a portion of the first drain region includes:
forming a third opening in the sacrificial layer through the second opening, and removing the photoresist layer, wherein the size of the third opening is smaller than that of the second opening;
and etching the dielectric layer through the third opening to expose part of the first gate structure, part of the first source region and part of the first drain region.
Further, the dielectric layer comprises a stop layer covering the first semiconductor structure and an insulating layer located on the stop layer, and the sacrificial layer is located on the insulating layer;
the step of etching the dielectric layer through the third opening to expose part of the first gate structure, part of the first source region and part of the first drain region includes:
forming a fourth opening in the insulating layer through the third opening, and removing the anti-reflection layer; the fourth opening comprises a first sub-opening, a second sub-opening and a third sub-opening, wherein an orthographic projection of the first sub-opening on the first gate structure is positioned in the first gate structure, an orthographic projection of the second sub-opening on the first source region is positioned in the first source region, and an orthographic projection of the third sub-opening on the first drain region is positioned in the first drain region;
removing the sacrificial layer;
forming a fifth opening in the stop layer through the fourth opening to expose a portion of the first gate structure, a portion of the first source region, and a portion of the first drain region.
Further, the sacrificial layer includes any one of an organic underlayer and a carbon coating layer, and the anti-reflection layer includes any one of a silicon-oxygen-based hard mask layer and a silicon oxynitride layer.
Furthermore, the mask layer also comprises a second mask opening;
the method further comprises the following steps:
providing a second semiconductor structure, wherein the second semiconductor structure comprises a second grid structure, and a second source electrode area and a second drain electrode area which are positioned at two opposite sides of the second grid structure; the dielectric layer also covers the second semiconductor structure;
and etching the sacrificial layer and the dielectric layer corresponding to the second semiconductor structure through the second mask opening to expose the second semiconductor structure, so that the second gate structure, the second source region and the second drain region in the second semiconductor structure are used as a second ohmic contact region of the second semiconductor structure.
Further, the method further comprises:
and forming an ohmic contact layer on the first and second ohmic contact regions.
Further, the first semiconductor structure includes a high voltage transistor, and the second semiconductor structure includes any one of a low voltage transistor and an ultra low voltage transistor.
The present invention also provides a semiconductor device formed by the above method of manufacturing a semiconductor device, the semiconductor device including:
the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, wherein the first semiconductor structure comprises a first grid structure, and a first source electrode area and a first drain electrode area which are positioned at two opposite sides of the first grid structure; the first semiconductor structure is provided with a first ohmic contact region which covers a part of the first gate structure, a part of the first source region and a part of the first drain region;
and the ohmic contact layer is positioned on the first ohmic contact region.
The embodiment of the invention also provides a memory, which comprises a memory array structure and a peripheral structure connected with the memory array structure;
the peripheral structure includes the semiconductor device described above.
The embodiment of the invention also provides a storage system which comprises the storage and a controller connected with the storage.
The embodiment of the invention has the beneficial effects that: covering a dielectric layer on the first semiconductor structure, forming a sacrificial layer on the dielectric layer, enabling the surface of one side, away from the dielectric layer, of the sacrificial layer to be flush, forming a mask layer on the sacrificial layer, etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through a first mask opening in the mask layer, exposing a part of first grid electrode structure, a part of first source electrode area and a part of first drain electrode area to be used as an ohmic contact area of the first semiconductor structure, reducing the thickness of the mask layer by forming the sacrificial layer in the dielectric layer and the mask layer, reducing the size of the first mask opening in the mask layer, further reducing the ohmic contact area of the first semiconductor structure, and reducing the electric leakage risk after forming the ohmic contact layer on the ohmic contact area.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a semiconductor device according to some embodiments;
fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 3a to fig. 3i are schematic structural diagrams corresponding to a manufacturing method of a semiconductor device according to an embodiment of the invention;
fig. 4 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a memory according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a storage system according to an embodiment of the present invention.
Detailed Description
Specific structural and functional details disclosed herein are merely representative and are provided for purposes of describing example embodiments of the present invention. The present invention may, however, be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present invention, it is to be understood that the terms "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless otherwise specified. Furthermore, the term "comprises" and any variations thereof is intended to cover non-exclusive inclusions.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
As shown in fig. 1, in some embodiments, in order to shrink the ohmic contact region of the transistor (especially, the high voltage transistor), a dielectric layer 200a is covered on the transistor 100a, and then a photoresist layer 300a is formed on the dielectric layer 200a, wherein the photoresist layer 300a has an opening 301a therein, so that an opening 201a is etched in the dielectric layer 200a through the opening 301a to expose the ohmic contact region 101a of the transistor 100 a. However, since the gate structure 102a of the transistor 100a has a height difference with the source region 103a and the drain region 104a, the thickness of the photoresist layer 300a is large, so that the size of the opening 301a in the photoresist layer 300a cannot be reduced to a target size. The lateral etching strength of the dielectric layer 200a is larger, so that the size of the opening 201a in the dielectric layer 200a is larger than that of the opening 301a in the photoresist layer 300a, and the transistor area exposed by the opening 201a may be larger than the area where the gate structure 102a, the source region 103a and the drain region 104a are located, thereby causing the ohmic contact region 101a of the transistor 100a to be larger. After the ohmic contact layer is formed on the ohmic contact region 101a of the transistor 100a, there may be a risk of leakage.
Accordingly, the embodiment of the invention provides a manufacturing method of a semiconductor device. Fig. 2 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention.
As shown in fig. 2, the method for manufacturing a semiconductor device according to the embodiment of the present invention includes steps 101 to 104, which are as follows:
In the embodiment of the present invention, as shown in fig. 3a, the first semiconductor structure 1a may be formed on the substrate 1. The substrate 1 may be a silicon substrate, a germanium substrate, or a semiconductor substrate including other elements. Trace trivalent elements such as boron, indium, gallium, aluminum and the like can be doped into the substrate 1 to form a P-type semiconductor substrate; the substrate 1 may be doped with trace amounts of pentavalent elements such as phosphorus, antimony, arsenic, etc. to form an N-type semiconductor substrate.
A first active region (not shown) may be formed in the substrate 1, and the first active region is close to the upper surface of the substrate 1 (i.e., the surface of the substrate 1 on the side where the first semiconductor structure 1a is formed later). A P-type active region or an N-type active region may be formed in the substrate by implanting P-type doping or N-type doping into the first active region through ion Implantation (IMP). Then, by ion implantation, a specific region in the first active region of the substrate 1 may be doped to form a first source region 11a and a first drain region 12a of the first semiconductor structure 1a in the first active region of the substrate 1, the first source region 11a and the first drain region 12a are close to the upper surface of the substrate 1, and the first source region 11a and the first drain region 12a are disposed at an interval. The first source region 11a and the first drain region 12a may form a P-type doped region or an N-type doped region by implanting P-type doping or N-type doping. The doping types of the first source region 11a and the first drain region 12a are the same. If the first semiconductor structure 1a is an N-type transistor, N-type doping is implanted into the first source region 11a and the first drain region 12 a; if the first semiconductor structure 1a is a P-type transistor, P-type doping is implanted into the first source region 11a and the first drain region 12 a.
By ion implantation, a specific region in the first active region of the substrate 1 may also be doped to form a first doped region and a second doped region in the first active region of the substrate, the first doped region and the second doped region being close to the upper surface of the substrate. The first doped region and the second doped region are disposed at an interval, the first doped region is located at a side of the first source region 11a away from the first drain region 12a, and the second doped region is located at a side of the first drain region 12a away from the first source region 11 a. The first doped region and the second doped region can form a P-type doped region or an N-type doped region by implanting P-type doping or N-type doping. The doping type of the first doping area is the same as that of the second doping area. The first and second doped regions are used to pull out the first active region so that a bias voltage is externally applied to the first active region to provide different substrate bias voltages to the first semiconductor structure 1 a.
The first gate structure 13a of the first semiconductor structure 1a may be formed on the first active region between the first source region 11a and the first drain region 12a, and the first gate structure 13a and the first source region 11a and the first drain region 12a have a height difference therebetween, that is, an upper surface of the first gate structure 13a (a surface of the first gate structure 13a on a side facing away from the substrate 1) is higher than upper surfaces of the first source region 11a and the first drain region 12 a. The first gate structure 13a may include a first gate insulating layer 131a and a first gate layer 132a, the first gate insulating layer 131a being on the first active region between the first source region 11a and the first drain region 12a, the first gate layer 132a being on the first gate insulating layer 131 a. In some embodiments, as shown in fig. 3a, the first gate insulating layer 131a may also extend onto the first source region 11a and the first drain region 12a, i.e., the first gate insulating layer 131a covers the first active region, and the first gate layer 132a is located on the first gate insulating layer 131a between the first source region 11a and the first drain region 12 a. The first gate insulating layer 131a serves to isolate the first gate layer 132a from the first active region. The first gate insulating layer 131a includes, but is not limited to, silicon oxide, etc., and the first gate layer 132a includes, but is not limited to, polysilicon, etc.
The first gate structure 13a may further include a first sidewall 133a on a sidewall of the first gate layer 132 a. The first sidewall 133a may be an on (silicon oxide-silicon nitride-silicon oxide-silicon nitride) structure (not shown), that is, the first sidewall 133a may include a first silicon oxide layer on a sidewall of the first gate layer 132a, a first silicon nitride layer on a surface of the first silicon oxide layer, a second silicon oxide layer on a surface of the first silicon nitride layer, and a second silicon nitride layer on a surface of the second silicon oxide layer. The first sidewall 133a is used to protect a sidewall of the first gate layer 132a, and increase a distance between the first gate layer 132a and the first source/ drain region 11a and 12a, so as to reduce a leakage risk.
The substrate 1 may further have a first shallow trench isolation structure (not shown) on the peripheral side of the first active region. The first shallow trench isolation structure is used for isolating the first semiconductor structure from other semiconductor structures. The first shallow trench isolation structure includes, but is not limited to, silicon oxide and the like.
The dielectric layer 2 covers the surface of the first semiconductor structure 1 a. When the first gate insulating layer 131a in the first gate structure 13a is only located on the first active region between the first source region 11a and the first drain region 12a, the dielectric layer 2 covers the upper surface of the first source region 11a, the upper surface of the first drain region 12a, and the sidewall and the upper surface of the first gate structure 13 a. When the first gate insulating layer 131a in the first gate structure 13a also covers the first source region 11a and the first drain region 12a, as shown in fig. 3a, the dielectric layer 2 covers the first gate insulating layer 131a on the first source region 11a and the first drain region 12a and the sidewall and the upper surface of the first gate structure 13 a.
The dielectric layer 2 may include a stop layer 21 and an insulating layer 22, the stop layer 21 covering the surface of the first semiconductor structure 1a, and the insulating layer 22 covering the stop layer 21. The stop layer 21 is used to avoid over-etching of the subsequent insulating layer 22, thereby avoiding damage to the first source region 11a, the first drain region 12a, and the first gate structure 13 a. The stop layer 21 includes, but is not limited to, silicon oxide, etc., and the insulating layer 22 includes, but is not limited to, silicon nitride, etc.
The substrate 1 may also have a second semiconductor structure thereon. Specifically, the method further comprises:
providing a second semiconductor structure, wherein the second semiconductor structure comprises a second grid structure, and a second source electrode area and a second drain electrode area which are positioned at two opposite sides of the second grid structure; the dielectric layer also covers the second semiconductor structure.
As shown in fig. 3a, the second semiconductor structure 1b is located on the substrate 1, and the second semiconductor structure 1b is spaced apart from the first semiconductor structure 1 a. A second active region (not shown) may be formed in the substrate 1, and a second source region 11b and a second drain region 12b of the second semiconductor structure 1b may be formed in the second active region, and the second source region 11b and the second drain region 12b are spaced apart. The second active region, the second source region 11b and the second drain region 12b in the second semiconductor structure 1b are similar to the first active region, the first source region 11a and the first drain region 12a in the first semiconductor structure 1a in the formation method, and detailed description thereof is omitted.
A second gate structure 13b of the second semiconductor structure 1b may be formed on the second active region between the second source region 11b and the second drain region 12b, and the second gate structure 13b and the second source region 11b and the second drain region 12b have a height difference therebetween, that is, an upper surface of the second gate structure 13b is higher than upper surfaces of the second source region 11b and the second drain region 12 b. The second gate structure 13b may include a second gate insulating layer 131b and a second gate layer 132b, the second gate insulating layer 131b being on the second active region between the second source region 11b and the second drain region 12b, the second gate layer 132b being on the second gate insulating layer 131 b. In some embodiments, as shown in fig. 3a, the second gate insulating layer 131b may also extend onto the second source region 11b and the second drain region 12b, i.e., the second gate insulating layer 131b covers the second active region, and the second gate layer 132b is located on the second gate insulating layer 131b between the second source region 11b and the second drain region 12 b. The second gate insulating layer 131b serves to isolate the second gate layer 132b from the second active region. The second gate insulating layer 131b includes, but is not limited to, silicon oxide, etc., and the second gate layer 132b includes, but is not limited to, polysilicon, etc.
The second gate structure 13b may further include a second sidewall 133b on a sidewall of the second gate layer 132 b. The second sidewall 133b may be an ONON (silicon oxide-silicon nitride-silicon oxide-silicon nitride) structure (not shown in the figure), and the second sidewall 133b has the same structure as the first sidewall 133a, which is not described in detail herein. The second sidewall 133b is used to protect a sidewall of the second gate layer 132b, and increase a distance between the second gate layer 132b and the second source/ drain region 11b and 12b, so as to reduce a leakage risk.
The substrate 1 may further have a second shallow trench isolation structure (not shown) on the peripheral side of the second active region. The second shallow trench isolation structure is used to isolate the second semiconductor structure 1b from other semiconductor structures. The second shallow trench isolation structure includes, but is not limited to, silicon oxide and the like.
The dielectric layer 2 may also cover the surface of the second semiconductor structure 1 b. When the second gate insulating layer 131b in the second gate structure 13b is only located on the second active region between the second source region 11b and the second drain region 12b, the dielectric layer 2 also covers the upper surface of the second source region 11b, the upper surface of the second drain region 12b, and the sidewalls and the upper surface of the second gate structure 13 b. When the second gate insulating layer 131b in the second gate structure 13b also covers the second source region 11b and the second drain region 12b, as shown in fig. 3a, the dielectric layer 2 also covers the second gate insulating layer 131b on the second source region 11b and the second drain region 12b and the sidewalls and the upper surface of the second gate structure 13 b. When the dielectric layer 2 includes the stop layer 21 and the insulating layer 22, the stop layer 21 also covers the surface of the second semiconductor structure 1b, and the insulating layer 22 covers the stop layer 21.
In the embodiment of the present invention, the first semiconductor structure 1a may be a high voltage transistor, and the second semiconductor structure 1b may be a low voltage transistor or an ultra low voltage transistor. Among them, ultra low pressure, low pressure and high pressure are relative concepts. The operating voltage of the ultra low voltage transistor (i.e., the voltage applied to the gate layer in the gate structure) is relatively small and the operating voltage of the high voltage transistor is relatively large, with the operating voltage of the low voltage transistor being between the operating voltage of the ultra low voltage transistor and the operating voltage of the high voltage transistor. In the ultra-low voltage transistor, the low voltage transistor and the high voltage transistor, the active area of the high voltage transistor is the largest, the active area of the ultra-low voltage transistor is the smallest, and the size of the active area of the low voltage transistor is between the ultra-low voltage transistor and the low voltage transistor; the depth of the channel of the high-voltage transistor is the largest, the depth of the channel of the ultra-low-voltage transistor is the smallest, and the depth of the channel of the low-voltage transistor is between the high-voltage transistor and the ultra-low-voltage transistor; the thickness of the gate insulating layer in the high-voltage transistor is the largest, the thickness of the gate insulating layer in the ultra-low-voltage transistor is the smallest, and the thickness of the gate insulating layer in the low-voltage transistor is between the two. As shown in fig. 3a, the thickness of the first gate insulating layer 131a in the first semiconductor structure 1a is greater than the thickness of the second gate insulating layer 131b in the second semiconductor structure 1 b.
And 102, forming a sacrificial layer on the dielectric layer, wherein the surface of one side of the sacrificial layer, which is far away from the dielectric layer, is flush.
Since the first gate structure 13a in the first semiconductor structure 1a has a height difference with the first source region 11a and the first drain region 12a, after the first semiconductor structure 1a is covered with the dielectric layer 2, the dielectric layer 2 on the first gate structure 13a still has a height difference with the dielectric layer 2 on the first source region 11a and the first drain region 12a, a sacrificial layer needs to be formed on the dielectric layer 2, so that the surface of the sacrificial layer on the side away from the dielectric layer 2 is flush, so as to eliminate the height difference.
As shown in fig. 3b, when the dielectric layer 2 covers the surface of the first semiconductor structure 1a, the sacrificial layer 3 is deposited on the dielectric layer 2, and the height of the upper surface of the sacrificial layer 3 is greater than that of the first gate structure 13a, so as to fill up the height difference between the first gate structure 13a and the first source region 11a and the first drain region 12a in the first semiconductor structure 1a, that is, the upper surface of the sacrificial layer 3 corresponding to the first gate structure 13a is flush with the upper surfaces of the sacrificial layers 3 corresponding to the first source region 11a and the first drain region 12 a. When the dielectric layer 2 further covers the surface of the second semiconductor structure 1b, the height of the upper surface of the sacrificial layer 3 is greater than the height of the upper surface of the second gate structure 13b, so as to fill up the height difference between the second gate structure 13b and the second source region 11b and the second drain region 12b in the second semiconductor structure 1b, that is, the upper surface of the sacrificial layer 3 corresponding to the second gate structure 13b is flush with the upper surfaces of the sacrificial layers 3 corresponding to the second source region 11b and the second drain region 12 b. The sacrificial Layer 3 is made of a material with good fluidity, and the sacrificial Layer 3 includes, but is not limited to, an Organic Under Layer (ODL) and a Carbon coating Layer (Spin-On-Carbon, SOC).
Since the upper surface of the sacrificial layer 3 is flush, the mask layer does not need to fill up the height difference between the first gate structure 13a and the first source region 11a and the first drain region 12a in the first semiconductor structure 1a, that is, the thickness of the mask layer can be thinner, so that the size of the first mask opening in the mask layer can be smaller.
The mask layer may include a photoresist layer and an anti-reflective layer, and the first mask opening may include a first opening and a second opening. Specifically, the forming a mask layer on the sacrificial layer in step 103 includes:
sequentially forming the anti-reflection layer and the photoresist layer on the sacrificial layer, wherein the photoresist layer is provided with the first opening;
forming the second opening in the antireflection layer through the first opening, the size of the second opening being smaller than the size of the first opening.
As shown in fig. 3c, the anti-reflection layer 41 is formed on the sacrificial layer 3, so that the thickness of the anti-reflection layer 41 can be thin and the upper surface of the anti-reflection layer 41 is flush since the upper surface of the sacrificial layer 3 is flush. Then, a photoresist layer 42 is formed on the anti-reflection layer 41, and since the upper surface of the anti-reflection layer 41 is level, the thickness of the photoresist layer 42 may be thin, and the thickness of the photoresist layer 42 is less than that of the photoresist layer 300a in fig. 1. When the sacrificial layer 3 is an organic underlayer, the anti-reflection layer 41 may be a silicon-on-silicon Hard Mask (SHB); when the sacrificial layer 3 is a carbon coating, the anti-reflection layer 41 may be a silicon oxynitride layer (SiON). The antireflective layer 41 and the photoresist layer 42 constitute a mask layer 4.
The photoresist layer 42 has a first opening 43 corresponding to the position of the first semiconductor structure 1 a. The first opening 43 may include three sub-openings corresponding to the positions of the first source region 11a, the first drain region 12a and the first gate layer 132a, and all the three sub-openings penetrate through the photoresist layer 42. Since the thickness of the photoresist layer 42 is thin, the size of the first opening 43 (i.e., the size of the three sub-openings) can be small, and the size of the first opening 43 is smaller than the size of the opening 301a in the photoresist layer 300a in fig. 1. The size of the first opening 43 refers to the lateral length of the first opening 43, and the lateral direction refers to the direction parallel to the upper surface of the substrate 1.
When the substrate 1 further has the second semiconductor structure 1b, the photoresist layer 42 further has a sixth opening 45 corresponding to the position of the second semiconductor structure 1b, and the sixth opening 45 penetrates through the photoresist layer 42. The orthogonal projection of the sixth opening 45 on the substrate 1 completely covers the second semiconductor structure 1 b.
Then, as shown in fig. 3d, the anti-reflection layer 41 is etched through the first opening 43 in the photoresist layer 42 to form a second opening 44 in the anti-reflection layer 41 corresponding to the position of the first semiconductor structure 1 a. Since the first opening 43 in the photoresist layer 42 includes three sub-openings, the second opening 44 in the photoresist layer 42 includes three sub-openings, and the three sub-openings in the first opening 43 correspond to and communicate with the three sub-openings in the second opening 44 one by one, that is, the three sub-openings in the second opening 44 correspond to the positions of the first source region 11a, the first drain region 12a, and the first gate layer 132a, respectively, and the three sub-openings in the second opening 44 all penetrate through the anti-reflection layer 41. The size of the second openings 44 may be smaller than the size of the first openings 43, i.e. the size of each sub-opening in the second openings 44 is smaller than the size of its corresponding sub-opening in the first openings 43. The sidewalls of the second opening 44 may be inclined, i.e., the bottom (the end of the second opening 44 close to the sacrificial layer 3) of the second opening 44 may be smaller than the top (the end of the second opening 44 close to the photoresist layer 42). The size of the second opening 44 may refer to the size of the bottom of the second opening 44, i.e., the lateral length of the bottom of the second opening 44. The first opening 43 and the second opening 44 together constitute a first mask opening of the mask layer 4.
In this embodiment, the anti-reflection layer 41 is disposed, so that the photolithography effect can be improved, the size of the second opening 44 is smaller than that of the first opening 43, and the size of the first opening 43 is smaller than that of the opening 301a in the photoresist layer 300a in fig. 1, so as to further reduce the size of the opening, which is beneficial to subsequently reduce the ohmic contact region of the first semiconductor structure 1 a.
When forming the second opening 44 in the anti-reflection layer 41, the corresponding anti-reflection layer 41 on the second semiconductor structure 1b may also be etched through the sixth opening 45 in the photoresist layer 42 to form a seventh opening 46 in the anti-reflection layer 41, and an orthographic projection of the seventh opening 46 on the substrate 1 completely covers the second active region to expose the corresponding sacrificial layer 3 on the second semiconductor structure 1 b. The sixth opening 45 and the seventh opening 46 together constitute a second mask opening of the mask layer 4.
And 104, etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose part of the first gate structure, part of the first source region and part of the first drain region to be used as a first ohmic contact region of the first semiconductor structure.
Through the first mask opening, the sacrificial layer 3 may be etched first, and then the dielectric layer 2 may be etched to expose the ohmic contact region of the first semiconductor structure 1 a. Due to the reduced size of the first mask opening, the ohmic contact region of the first semiconductor structure 1a is reduced, i.e., the ohmic contact region of the first semiconductor structure 1a is smaller than the regions where the first source region 11a, the first drain region 12a and the first gate layer 132a are located.
Specifically, the etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening in step 104 to expose a portion of the first gate structure, a portion of the first source region, and a portion of the first drain region includes:
forming a third opening in the sacrificial layer through the second opening, and removing the photoresist layer, wherein the size of the third opening is smaller than that of the second opening;
and etching the dielectric layer through the third opening to expose part of the first gate structure, part of the first source region and part of the first drain region.
When the mask layer 4 further has a second mask opening, the method further includes:
and etching the sacrificial layer and the dielectric layer corresponding to the second semiconductor structure through the second mask opening to expose the second semiconductor structure, so that the second gate structure, the second source region and the second drain region in the second semiconductor structure are used as a second ohmic contact region of the second semiconductor structure.
As shown in fig. 3e, the sacrificial layer 3 is etched through the second opening 44 in the anti-reflection layer 41 to form the third opening 30 in the sacrificial layer 3 corresponding to the position of the first semiconductor structure 1 a. Since the second opening 44 in the anti-reflection layer 41 includes three sub-openings, the third opening 30 in the sacrificial layer 3 includes three sub-openings, and the three sub-openings in the third opening 30 correspond to and communicate with the three sub-openings in the second opening 44 one by one, that is, the three sub-openings in the third opening 30 correspond to the positions of the first source region 11a, the first drain region 12a, and the first gate layer 132a, respectively, and the three sub-openings in the third opening 30 all penetrate through the sacrificial layer 3. The size of the third opening 30 may be smaller than the size of the second opening 44, i.e. the size of each sub-opening in the third opening 30 is smaller than the size of its corresponding sub-opening in the second opening 44. The sidewalls of the third opening 30 may be inclined, that is, the size of the bottom of the third opening 30 (the end of the third opening 30 facing away from the anti-reflection layer 41) may be smaller than the size of the top (the end of the third opening 30 close to the anti-reflection layer 41). The size of the third opening 30 may refer to the size of the bottom of the third opening 30, i.e., the lateral length of the bottom of the third opening 30.
In this embodiment, by providing the sacrificial layer 3, the thickness of the mask layer 4 can be reduced, and further the size of the first mask opening is reduced, the size of the third opening 30 is smaller than that of the second opening 44, the size of the second opening 44 is smaller than that of the first opening 43, and the size of the first opening 43 is smaller than that of the opening 301a in the photoresist layer 300a in fig. 1, so as to further reduce the size of the opening, which is beneficial to subsequently reduce the ohmic contact region of the first semiconductor structure 1 a. In addition, in order to ensure that the size of the third opening 30 in the sacrificial layer 3 is more controllable, the sacrificial layer 3 in this embodiment may be a carbon coating.
When the third opening 30 is formed in the sacrificial layer 3, the sacrificial layer 3 corresponding to the second semiconductor structure 1b may be etched through the second mask opening, so as to completely remove the sacrificial layer 3 corresponding to the second semiconductor structure 1b and expose the dielectric layer 2 corresponding to the second semiconductor structure 1 b.
Because the material of the sacrificial layer 3 is similar to that of the photoresist layer 42, when the sacrificial layer 3 is etched, the photoresist layer 42 can be simultaneously etched to remove the photoresist layer 42, so that the manufacturing process is simplified, and the influence on the subsequent etching of the dielectric layer 2 caused by the overlarge overall thickness of the photoresist layer 42, the anti-reflection layer 41 and the sacrificial layer 3 is avoided.
When the dielectric layer 2 includes the stop layer 21 and the insulating layer 22, the step of etching the dielectric layer through the third opening to expose a part of the first gate structure, a part of the first source region and a part of the first drain region includes:
forming a fourth opening in the insulating layer through the third opening, and removing the anti-reflection layer; the fourth opening comprises a first sub-opening, a second sub-opening and a third sub-opening, wherein an orthographic projection of the first sub-opening on the first gate structure is positioned in the first gate structure, an orthographic projection of the second sub-opening on the first source region is positioned in the first source region, and an orthographic projection of the third sub-opening on the first drain region is positioned in the first drain region;
removing the sacrificial layer;
forming a fifth opening in the stop layer through the fourth opening to expose a portion of the first gate structure, a portion of the first source region, and a portion of the first drain region.
As shown in fig. 3f, the insulating layer 22 is etched through the third opening 30 in the sacrificial layer 3 to form a fourth opening 220 in the insulating layer 22 corresponding to the position of the first semiconductor structure 1 a. Since the third opening 30 in the sacrificial layer 3 includes three sub-openings, the fourth opening 220 in the insulating layer 22 includes three sub-openings, i.e., the first sub-opening 221, the second sub-opening 222, and the third sub-opening 223. The first sub-opening 221, the second sub-opening 222 and the third sub-opening 223 are in one-to-one correspondence with and communicate with three sub-openings in the sacrificial layer 3, that is, the first sub-opening 221 corresponds to a position of the first gate structure 13a, the second sub-opening 222 corresponds to a position of the first source region 11a, and the third sub-opening 223 corresponds to a position of the first drain region 12 a.
When the fourth opening 220 is formed in the insulating layer 22, the corresponding insulating layer 22 on the second semiconductor structure 1b may be further etched to completely remove the corresponding insulating layer 22 on the second semiconductor structure 1b (including the second source region 11b, the second drain region 12b, and the insulating layer 22 corresponding to the sidewall and the upper surface of the second gate structure 13 b), and expose the stop layer 21 on the second semiconductor structure 1 b.
Since the insulating layer 22 corresponding to the sidewall of the second gate structure 13b needs to be removed, the lateral etching strength of the insulating layer 22 is increased, so that the size of the fourth opening 220 in the insulating layer 22 may be larger than the bottom size of the third opening 30, but the size of the fourth opening 220 is still smaller than the size of the opening 201a in the dielectric layer 200a in fig. 1 because the bottom size of the third opening 30 is smaller. An orthographic projection of the first sub-opening 221 on the first gate structure 13a is located in the first gate layer 132a, an orthographic projection of the second sub-opening 222 on the first source region 11a is located in the first source region 11a, and an orthographic projection of the third sub-opening 223 on the first drain region 12a is located in the first drain region 12 a.
Since the antireflection layer 41 is made of a material similar to that of the insulating layer 22, when the insulating layer 22 is etched, the antireflection layer 41 can be etched at the same time, and the antireflection layer 41 is removed, so that the manufacturing process is simplified. Since the insulating layer 22 is thin, in order to avoid the antireflection layer 41 remaining after the etching of the insulating layer 22 is completed and affecting the etching of the subsequent sacrificial layer 3, the antireflection layer 41 in this embodiment may adopt a silicon-based hard mask layer to ensure that the antireflection layer 41 can be completely removed.
After removing the anti-reflection layer 41, the sacrificial layer 3 is etched to remove the sacrificial layer 3, as shown in fig. 3 g.
Then, as shown in fig. 3h, the stop layer 21 is etched through the fourth opening 220 in the insulating layer 22 to form a fifth opening 210 in the stop layer 21 corresponding to the position of the first semiconductor structure 1 a. Since the fourth opening 220 includes the first sub-opening 221, the second sub-opening 222 and the third sub-opening 223, the fifth opening 210 in the stop layer 21 includes three sub-openings, and the three sub-openings in the fifth opening 210 correspond to and communicate with the first sub-opening 221, the second sub-opening 222 and the third sub-opening 223 one by one, that is, the three sub-openings in the fifth opening 210 correspond to the positions of the first source region 11a, the first drain region 12a and the first gate layer 132a, respectively, and the three sub-openings in the fifth opening 210 all penetrate through the stop layer 21. The size of the fifth opening 210 is the same as that of the fourth opening 220, so that an orthographic projection of the fifth opening 210 on the first source region 11a, the first drain region 12a and the first gate layer 132a is located within the first source region 11a, the first drain region 12a and the first gate layer 132 a.
When the first gate insulating layer 131a in the first semiconductor structure 1a is located only on the first active region between the first source region 11a and the first drain region 12a, the fifth opening 210 may expose a portion of an upper surface of the first source region 11a, a portion of an upper surface of the first drain region 12a, and a portion of an upper surface of the first gate layer 132 a. The exposed upper surface of the first source region 11a, the exposed upper surface of the first drain region 12a, and the exposed upper surface of the first gate layer 132a form a first ohmic contact region 15a of the first semiconductor structure 1a, i.e., the first ohmic contact region 15a does not exceed the area where the first source region 11a, the first drain region 12a, and the first gate layer 132a are located, so as to reduce the ohmic contact region of the first semiconductor structure 1 a.
When the first gate insulating layer 131a in the first semiconductor structure 1a also covers the first source region 11a and the first drain region 12a, the fifth opening 210 may expose a portion of the upper surface of the first gate layer 132a and a portion of the first gate insulating layer 131a on the first source region 11a and the first drain region 12 a. Etching of a portion of the first gate insulating layer 131a on the first source region 11a and the first drain region 12a is continued through the fifth opening 210 to expose a portion of the upper surface of the first source region 11a and a portion of the upper surface of the first drain region 12 a. The exposed upper surface of the first source region 11a, the upper surface of the first drain region 12a, and the upper surface of the first gate layer 132a constitute the first ohmic contact region 15a of the first semiconductor structure 1a, so that the first ohmic contact region 15a of the first semiconductor structure 1a can be reduced.
When forming the fifth opening 210 in the stop layer 21, the stop layer 21 on the second semiconductor structure 1b may also be etched to completely remove the stop layer 21 (including the stop layer 21 on the sidewalls and the upper surface of the second source region 11b, the second drain region 12b, and the second gate structure 13 b) on the second semiconductor structure 1 b.
When the second gate insulating layer 131b in the second semiconductor structure 1b is only located on the second active region between the second source region 11b and the second drain region 12b, the stop layer 21 on the second semiconductor structure 1b is removed to completely expose the second semiconductor structure 1b, i.e., expose all of the upper surfaces of the second source region 11b, the second drain region 12b and the second gate layer 132 b. The entire upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b constitute the second ohmic contact region 15b of the second semiconductor structure 1 b.
When the second gate insulating layer 131b in the second semiconductor structure 1b also covers the second source region 11b and the second drain region 12b, the stop layer 21 on the second semiconductor structure 1b is removed, and the entire upper surface of the second gate layer 132b and the second gate insulating layer 131b on the second source region 11b and the second drain region 12b are exposed. The second gate insulating layer 131b on the second source region 11b and the second drain region 12b is continuously etched, and the second gate insulating layer 131b on the second source region 11b and the second drain region 12b is completely removed to expose the entire upper surfaces of the second source region 11b and the second drain region 12 b. The entire upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b constitute the second ohmic contact region 15b of the second semiconductor structure 1 b.
Further, the method further comprises:
and forming an ohmic contact layer on the first and second ohmic contact regions.
As shown in fig. 3i, after the first ohmic contact region 15a of the first semiconductor structure 1a and the second ohmic contact region 15b of the second semiconductor structure 1b are formed, the remaining insulating layer 22 may be removed. Then, the ohmic contact layer 5 is formed on the first ohmic contact region 15a of the first semiconductor structure 1a and the second ohmic contact region 15b of the second semiconductor structure 1 b. The ohmic contact layer 5 covers a portion of the upper surface of the first source region 11a, a portion of the upper surface of the first drain region 12a, and a portion of the upper surface of the first gate layer 132a in the first semiconductor structure 1 a. The first semiconductor structure is a high voltage transistor, and the working voltage of the high voltage transistor is large, so that the distance between the first source region 11a and the first drain region 12a and the first gate structure 13a is too small, the first ohmic contact region 15a is reduced in this embodiment, and the coverage area of the ohmic contact layer 5 on the first semiconductor structure 1a is further reduced, and the risk of leakage of the first semiconductor structure 1a can be reduced. The ohmic contact layer 5 also covers the entire upper surface of the second source region 11b, the entire upper surface of the second drain region 12b, and the entire upper surface of the second gate layer 132b in the second semiconductor structure 1 b. The second semiconductor structure 1b is a low voltage transistor or an ultra low voltage transistor, and the operating voltage thereof is low, so that the ohmic contact layer 5 can completely cover the upper surfaces of the second source region 11b, the second drain region 12b and the second gate layer 132b, and the electrical performance of the second semiconductor structure 1b is not affected.
After the ohmic contact layer 5 is formed, a plurality of contact structures (not shown) may be further formed on the ohmic contact layer 5, and the plurality of contact structures are respectively connected to the first source region 11a, the first drain region 12a, the first gate layer 132a, the second source region 11b, the second drain region 12b, and the second gate layer 132b through the ohmic contact layer 5. The ohmic contact layer 5 serves to reduce contact resistance of the source, drain and gate layers with the corresponding contact structure. The ohmic contact layer 5 forms ohmic contact with the source region, the drain region and the gate layer, so that the voltage drop at the contact part is small enough when voltage is applied to the source region, the drain region and the gate layer, and the influence on the electrical property of the device is reduced. The material of the ohmic contact layer 5 may be nickel silicide NiSi.
According to the manufacturing method of the semiconductor device, the dielectric layer can be covered on the first semiconductor structure, the sacrificial layer is formed on the dielectric layer, the surface of one side, away from the dielectric layer, of the sacrificial layer is flush, the mask layer is formed on the sacrificial layer, the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure are etched through the first mask opening in the mask layer, part of the first grid structure, part of the first source electrode region and part of the first drain electrode region are exposed and serve as the ohmic contact region of the first semiconductor structure, therefore, the thickness of the mask layer is reduced by forming the sacrificial layer in the dielectric layer and the mask layer, the size of the first mask opening in the mask layer is reduced, the ohmic contact region of the first semiconductor structure is further reduced, and the electric leakage risk is reduced after the ohmic contact layer is formed on the ohmic contact region.
Correspondingly, the embodiment of the invention also provides a semiconductor device which is formed by the manufacturing method of the semiconductor device in the embodiment.
As shown in fig. 4, the semiconductor device provided by the embodiment of the present invention includes a substrate 1, a first semiconductor structure 1a, and an ohmic contact layer 5.
The first semiconductor structure 1a includes a first source region 11a, a first drain region 12a, and a first gate structure 13 a. The substrate 1 includes a first active region (not shown), in which a first source region 11a and a first drain region 12a are located, and the first source region 11a and the first drain region 12a are spaced apart. The first gate structure 13a is located on the first active region between the first source region 11a and the first drain region 12a, such that the first gate structure 13a has a height difference with the first source region 11a and the first drain region 12a, i.e., an upper surface of the first gate structure 13a is higher than upper surfaces of the first source region 11a and the first drain region 12 a.
The first gate structure 13a may include a first gate insulating layer 131a and a first gate layer 132a, the first gate insulating layer 131a being on the first active region between the first source region 11a and the first drain region 12a, the first gate layer 132a being on the first gate insulating layer 131 a. The first gate insulating layer 131a serves to isolate the first gate layer 132a from the first active region. The first gate insulating layer 131a includes, but is not limited to, silicon oxide, etc., and the first gate layer 132a includes, but is not limited to, polysilicon, etc.
The first gate structure 13a may further include a first sidewall 133a on a sidewall of the first gate layer 132 a. The first sidewall spacers 133a may be of ONON (silicon oxide-silicon nitride-silicon oxide-silicon nitride) structure (not shown). The first sidewall 133a is used to protect a sidewall of the first gate layer 132a, and increase a distance between the first gate layer 132a and the first source/ drain region 11a and 12a, so as to reduce a leakage risk.
The first semiconductor structure 1a has a first ohmic contact region 15a, and the first ohmic contact region 15a covers a portion of the first source region 11a, a portion of the first drain region 12a, and a portion of the first gate structure 13 a. Specifically, the first ohmic contact region 15a covers a portion of the upper surface of the first source region 11a, a portion of the upper surface of the first drain region 12a, and a portion of the upper surface of the first gate layer 132 a.
The ohmic contact layer 5 is on the first ohmic contact region 15a, i.e., the ohmic contact layer 5 covers a portion of the upper surface of the first source region 11a, a portion of the upper surface of the first drain region 12a, and a portion of the upper surface of the first gate layer 132a, so as to reduce the risk of leakage of the first semiconductor structure 1 a. The ohmic contact layer 5 further has contact structures (not shown) corresponding to the first source region 11a, the first drain region 12a and the first gate layer 132a, respectively, and the ohmic contact layer 5 is used for reducing contact resistance between the first source region 11a, the first drain region 12a and the first gate layer 132a and the corresponding contact structures. The ohmic contact layer 5 forms an ohmic contact with the first source region 11a, the first drain region 12a, and the first gate layer 132a, so that a voltage drop at the contact is sufficiently small when a voltage is applied to the first source region 11a, the first drain region 12a, and the first gate layer 132a, reducing an influence on electrical properties of the device. The material of the ohmic contact layer 5 may be nickel silicide NiSi.
The semiconductor device may further include a stop layer 21, the stop layer 21 covering a non-ohmic contact region of the first semiconductor structure 1a, the non-ohmic contact region of the first semiconductor structure 1a referring to a region of the first semiconductor structure 1a other than the first ohmic contact region 15 a.
In some embodiments, as shown in fig. 3i, the first gate insulating layer 131a may also extend to the non-ohmic contact regions of the first source region 11a and the first drain region 12a, and the first gate insulating layer 131a on the first source region 11a and the first drain region 12a is located between the substrate 1 and the stop layer 21. The non-ohmic contact regions of the first source region 11a and the first drain region 12a refer to other regions of the first source region 11a and the first drain region 12a except for the first ohmic contact region 15 a.
The semiconductor device may further include a second semiconductor structure 1b, the second semiconductor structure 1b including a second source region 11b, a second drain region 12b, and a second gate structure 13 b. The substrate 1 includes a second active region (not shown), in which the second source region 11b and the second drain region 12b are located, and the second source region 11b and the second drain region 12b are spaced apart. The second gate structure 13b is located on the second active region between the second source region 11b and the second drain region 12b, such that the second gate structure 13b has a height difference with the second source region 11b and the second drain region 12b, i.e., the upper surface of the second gate structure 13b is higher than the upper surfaces of the second source region 11b and the second drain region 12 b.
The second gate structure 13b may include a second gate insulating layer 131b and a second gate layer 132b, the second gate insulating layer 131b being on the second active region between the second source region 11b and the second drain region 12b, the second gate layer 132b being on the second gate insulating layer 131 b. The second gate insulating layer 131b serves to isolate the second gate layer 132b from the second active region. The second gate insulating layer 131b includes, but is not limited to, silicon oxide, etc., and the second gate layer 132b includes, but is not limited to, polysilicon, etc.
The second gate structure 13b may further include a second sidewall 133b on a sidewall of the second gate layer 132 b. The second sidewall spacers 133b may be of ONON (silicon oxide-silicon nitride-silicon oxide-silicon nitride) structure (not shown in the figure). The second sidewall 133b is used to protect a sidewall of the second gate layer 132b, and increase a distance between the second gate layer 132b and the second source/ drain region 11b and 12b, so as to reduce a leakage risk.
The second semiconductor structure 1b has a second ohmic contact region 15b, and the second ohmic contact region 15b covers the entire upper surface of the second source region 11b, the entire upper surface of the second drain region 12b, and the entire upper surface of the second gate layer 132 b.
The ohmic contact layer 5 is also positioned on the second ohmic contact region 15b, i.e., the ohmic contact layer 5 also covers the entire upper surface of the second source region 11b, the entire upper surface of the second drain region 12b, and the entire upper surface of the second gate layer 132 b. The ohmic contact layer 5 further has contact structures (not shown) corresponding to the second source region 11b, the second drain region 12b and the second gate layer 132b, respectively, and the ohmic contact layer 5 is used for reducing contact resistances between the second source region 11b, the second drain region 12b and the second gate layer 132b and the corresponding contact structures. The ohmic contact layer 5 forms an ohmic contact with the second source region 11b, the second drain region 12b, and the second gate layer 132b, so that a voltage drop at the contact is sufficiently small when a voltage is applied to the second source region 11b, the second drain region 12b, and the second gate layer 132b, reducing an influence on electrical properties of the device.
The first semiconductor structure 1a may be a high voltage transistor, and the working voltage of the high voltage transistor is large, so that the distance between the first source region 11a and the first drain region 12a and the first gate structure 13a is too small, the embodiment reduces the first ohmic contact region 15a, further reduces the coverage area of the ohmic contact layer 5 on the first semiconductor structure 1a, and can reduce the risk of leakage of the first semiconductor structure 1 a. The second semiconductor structure 1b may be a low voltage transistor or an ultra low voltage transistor, and the operating voltage is low, so that the ohmic contact layer 5 may completely cover the upper surfaces of the second source region 11b, the second drain region 12b, and the second gate layer 132b, and the electrical performance of the second semiconductor structure 1b may not be affected.
According to the semiconductor device provided by the embodiment of the invention, the ohmic contact layer can only cover part of the first source region, part of the first drain region and part of the first gate structure in the first semiconductor structure, so that the covering area of the ohmic contact layer is reduced, and the leakage risk of the first semiconductor structure is reduced.
Fig. 5 is a schematic structural diagram of a memory according to an embodiment of the present invention.
As shown in fig. 5, the memory includes a memory array structure 100 and a peripheral structure 200. The memory array structure 100 may be a non-volatile memory array structure, for example, the memory array structure 100 may be a NAND flash memory, a NOR flash memory, or the like. The peripheral structure 200 may include devices such as CMOS (complementary metal oxide semiconductor), SRAM (static random access memory), DRAM (dynamic random access memory), FPGA (field programmable gate array), CPU (central processing unit), Xpoint chip, and the like.
Specifically, the peripheral structure 200 may be located on the memory array structure 100, and the peripheral structure 200 is connected to the memory array structure 100. The peripheral structure 200 may include the semiconductor devices in the above embodiments, and will not be described in detail herein.
The memory array structure 100 and the peripheral structure 200 may also adopt other architecture forms, for example, the peripheral structure 200 is located below the memory array structure 100, i.e., a puc (peripheral under core array) architecture, or the peripheral structure 200 and the memory array structure 100 are arranged in parallel, i.e., a pnc (peripheral under core array) architecture, and the like, which is not limited herein.
The memory provided by the embodiment of the invention can reduce the electric leakage risk of the peripheral structure in the memory.
Fig. 6 is a schematic structural diagram of a storage system according to an embodiment of the present invention.
As shown in fig. 6, the embodiment of the present invention further provides a memory system, which includes a memory 300 and a controller 400, wherein the memory 300 is electrically connected to the controller 400, and the controller 400 is used for controlling the memory 300 to store data. The memory 300 is the memory in the above embodiments, and is not described in detail herein. The controller 400 may be a controller well known to those skilled in the art and will not be described in detail herein.
The storage system can be applied to terminal products such as computers, televisions, set top boxes, vehicles and the like.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (11)
1. A method for manufacturing a semiconductor device, comprising:
providing a first semiconductor structure and a dielectric layer covering the first semiconductor structure; the first semiconductor structure comprises a first gate structure, a first source region and a first drain region which are positioned at two opposite sides of the first gate structure;
forming a sacrificial layer on the dielectric layer, wherein the surface of one side of the sacrificial layer, which is far away from the dielectric layer, is flush;
forming a mask layer on the sacrificial layer, wherein the mask layer is provided with a first mask opening;
and etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose part of the first gate structure, part of the first source region and part of the first drain region to be used as a first ohmic contact region of the first semiconductor structure.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the mask layer includes a photoresist layer and an antireflection layer, and the first mask opening includes a first opening and a second opening;
the step of forming a mask layer on the sacrificial layer includes:
sequentially forming the anti-reflection layer and the photoresist layer on the sacrificial layer, wherein the photoresist layer is provided with the first opening;
forming the second opening in the antireflection layer through the first opening, the size of the second opening being smaller than the size of the first opening.
3. The method of claim 2, wherein the step of etching the sacrificial layer and the dielectric layer corresponding to the first semiconductor structure through the first mask opening to expose a portion of the first gate structure, a portion of the first source region and a portion of the first drain region comprises:
forming a third opening in the sacrificial layer through the second opening, and removing the photoresist layer, wherein the size of the third opening is smaller than that of the second opening;
and etching the dielectric layer through the third opening to expose part of the first gate structure, part of the first source region and part of the first drain region.
4. The method of manufacturing a semiconductor device according to claim 3, wherein the dielectric layer includes a stop layer covering the first semiconductor structure, and an insulating layer on the stop layer, and the sacrificial layer is on the insulating layer;
the step of etching the dielectric layer through the third opening to expose the part of the first gate structure, the part of the first source region and the part of the first drain region includes:
forming a fourth opening in the insulating layer through the third opening, and removing the anti-reflection layer; the fourth opening comprises a first sub-opening, a second sub-opening and a third sub-opening, wherein an orthographic projection of the first sub-opening on the first gate structure is positioned in the first gate structure, an orthographic projection of the second sub-opening on the first source region is positioned in the first source region, and an orthographic projection of the third sub-opening on the first drain region is positioned in the first drain region;
removing the sacrificial layer;
forming a fifth opening in the stop layer through the fourth opening to expose the portion of the first gate structure, the portion of the first source region, and the portion of the first drain region.
5. The method for manufacturing a semiconductor device according to claim 2, wherein the sacrificial layer includes any one of an organic underlayer and a carbon coating layer, and the antireflection layer includes any one of a silicon oxide-based hard mask layer and a silicon oxynitride layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein the mask layer further includes a second mask opening;
the method further comprises the following steps:
providing a second semiconductor structure, wherein the second semiconductor structure comprises a second grid structure, and a second source electrode area and a second drain electrode area which are positioned at two opposite sides of the second grid structure; the dielectric layer also covers the second semiconductor structure;
and etching the sacrificial layer and the dielectric layer corresponding to the second semiconductor structure through the second mask opening to expose the second semiconductor structure, so that the second gate structure, the second source region and the second drain region in the second semiconductor structure are used as a second ohmic contact region of the second semiconductor structure.
7. The method for manufacturing a semiconductor device according to claim 6, wherein the method further comprises:
and forming an ohmic contact layer on the first and second ohmic contact regions.
8. The method for manufacturing a semiconductor device according to claim 6, wherein the first semiconductor structure comprises a high-voltage transistor, and the second semiconductor structure comprises any one of a low-voltage transistor and an ultra-low-voltage transistor.
9. A semiconductor device formed by the method of manufacturing a semiconductor device according to any one of claims 1 to 8, comprising:
the semiconductor device comprises a first semiconductor structure, a second semiconductor structure and a third semiconductor structure, wherein the first semiconductor structure comprises a first grid structure, and a first source electrode area and a first drain electrode area which are positioned at two opposite sides of the first grid structure; the first semiconductor structure is provided with a first ohmic contact region which covers a part of the first gate structure, a part of the first source region and a part of the first drain region;
and the ohmic contact layer is positioned on the first ohmic contact region.
10. A memory comprises a memory array structure and a peripheral structure connected with the memory array structure;
the peripheral structure comprises a semiconductor device as claimed in any one of claims 9.
11. A memory system comprising the memory of claim 10, and a controller coupled to the memory.
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