CN114157291A - Phase interpolator insensitive to parasitics - Google Patents

Phase interpolator insensitive to parasitics Download PDF

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Publication number
CN114157291A
CN114157291A CN202111499160.1A CN202111499160A CN114157291A CN 114157291 A CN114157291 A CN 114157291A CN 202111499160 A CN202111499160 A CN 202111499160A CN 114157291 A CN114157291 A CN 114157291A
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China
Prior art keywords
phase
circuit
switch
charging
clock
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CN202111499160.1A
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Chinese (zh)
Inventor
刘军华
姜皓云
王栋
廖怀林
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Peking University
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Peking University
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Abstract

The invention discloses a phase interpolator insensitive to parasitic coupling, which relates to the technical field of circuit design and adopts a charge charging type phase interpolation structure. The phase interpolator comprises a plurality of phase interpolation units, each phase interpolation unit provides fixed current, a complementary charging control switch is adopted and is controlled by a non-overlapping clock, the influence of parasitic effect on the performance of the phase interpolator can be effectively avoided, and the linearity is obviously improved.

Description

Phase interpolator insensitive to parasitics
Technical Field
The invention relates to the technical field of circuit design, in particular to a phase interpolator insensitive to parasitic coupling.
Background
A phase interpolator is a widely used rf integrated circuit module for generating digitally controlled phases, often used in phase locked loops, polar and differential digital transmitters, clock data recovery and phased array systems. The linearity of the phase interpolator is very important and can affect the phase noise and spurious levels of the phase locked loop, the error vector magnitude of the digital transmitter, the data rate of clock data recovery and the angular resolution of the phased array system.
There are two common configurations for a phase interpolator, one is a vector summation configuration and the other is a charge-charging configuration. The vector-sum phase interpolator superimposes two signals with a fixed phase difference, and the output phase depends on the amplitude ratio of the two signals, as shown in fig. 1A. The vector summation structure is in principle systematic in error and sensitive to harmonics of the signal, so that linearity tends to be poor. Ming-Shuan Chen et al have used Harmonic suppression techniques to improve the linearity of the vector summation structure, but the linearity remains low (M.Chen, A.A.Hafez and C.K.Yang, "A0.1-1.5 GHz 8-bit inverse-Based Digital-to-Phase Converter Using Harmonic Rejection," in IEEE Journal of Solid-State Circuits, vol.48, No.11, pp.2681-2692, Nov.2013.).
The charge-charging phase interpolator charges two currents controlled by digital signals into a shared capacitor, and the phase of the output depends on the size ratio of the two currents, as shown in fig. 1B. When inputting the clock
Figure BDA0003402088560000011
After the rising edge of (3) arrives, the current source IAStarting to charge the capacitor C; when the clock is input
Figure BDA0003402088560000012
After the rising edge of (3) arrives, the current source IBAnd the current source IAThe capacitors C are charged together. The sum of the currents of two current sources in a general charge-charging phase interpolator is fixed, so that the voltage V of the upper plate of the charging capacitorCDepends on the division of the current between the two current sources. Compared with the vector addition structure, the charge charging structure has no systematic error and is not influenced by harmonic waves. However, with the development of CMOS technology, the operating frequency of the rf integrated circuit is gradually increased, and the phase interpolator also tends to operate at higher frequency. The parasitic capacitance is close to the charging capacitance, and the phase of the phase interpolator is seriously deteriorated by the existence of the parasitic effect.
The published patent CN103516353A discloses a circuit for generating clock signal, which has the disadvantage that the switch switching is controlled by the selection of current source, the MOS transistor of the current mirror will enter the non-linear region when the switch is turned off, and the S thereofdischThe switch is only a discharge switch, and the problem of linearity deterioration caused by node parasitic capacitance cannot be solved.
In summary, a technique is needed to avoid the linearity degradation caused by phase interpolator parasitics.
Disclosure of Invention
The invention aims to provide a phase interpolator insensitive to parasitic, which adopts a charge charging type phase interpolation structure. The phase interpolator comprises a plurality of phase interpolation units, each phase interpolation unit provides fixed current, adopts a complementary charging control switch and is controlled by a non-overlapping clock, can effectively avoid the influence of parasitic effect on the performance of the phase interpolator, obviously improves the linearity, and is suitable for scenes such as an all-digital phase-locked loop, a digital transmitter, a clock data recovery circuit and the like.
In order to achieve the purpose, the invention adopts the following technical scheme:
a phase interpolator insensitive to parasitics comprises one or more phase interpolation units connected in parallel, and a charging capacitor in circuit connection with the phase difference unit; each phase difference value unit is provided with a charging circuit, a grounding circuit and a clock circuit; the charging circuit is used for transmitting current of a current source to charge the charging capacitor, and a switch S is arranged on the charging circuit1(ii) a The other end of the grounding circuit opposite to the grounding end is connected with the charging circuit, and the grounding circuit is provided with a switch S2(ii) a The clock circuit is used for receiving an input two-phase clock
Figure BDA0003402088560000021
And
Figure BDA0003402088560000022
as two control signals, one for controlling the switch S1Another of said control signals for controlling said switch S2At said switch S1And S2The clock circuit in between is provided with a phase inverter.
Preferably, the current mirror of the phase interpolation unit is of a common-gate structure.
Preferably, the two-phase clock
Figure BDA0003402088560000023
And
Figure BDA0003402088560000024
are respectively controlled by a pair of control codes D0And
Figure BDA0003402088560000025
control, said control code D0And
Figure BDA0003402088560000026
the value is 0 or 1, and the values are opposite; the switch S1Control signal of
Figure BDA0003402088560000027
The switch S2Control signal of
Figure BDA0003402088560000028
Of opposite sign
Figure BDA0003402088560000029
Preferably, the two-phase clock
Figure BDA00034020885600000210
And
Figure BDA00034020885600000211
is less than or equal to 90 deg.
Preferably, the two-phase clock
Figure BDA00034020885600000212
And
Figure BDA00034020885600000213
generated by a signal divider circuit and a delay locked loop circuit.
The invention achieves the following positive effects:
1) the linearity is good: the invention adopts a charge charging type structure with better linearity in the aspect of architecture, and further solves the problem of linearity deterioration caused by parasitic effect. The current mirror in the power supply can not change in working state, so that the MOS tube of the current mirror can work in a saturation region constantly, the MOS tube of the current mirror can not enter a non-linear region when a switch is switched off, and the power supply has better linearity. By means of said switch S2The voltage of the output node of the current source is kept to be 0 when the current source is in a non-charging state, so that the charges on the parasitic capacitor of the node are discharged, and the problem of reduced linearity caused by charge sharing at the beginning of charging is solved. In addition, the invention also uses non-overlapping clock control, solves the problem of charge leakage and further improves the linearity.
2) The working speed is fast: the switching of the switch is controlled on the selection of the clock, the speed is high, and the working frequency of the phase interpolator can be improved; the invention solves the problem of linearity deterioration caused by parasitic capacitance, thus reducing the capacitance value requirement of the charging capacitor, and the charging and discharging speed can be faster, thus the invention can work at higher frequency.
3) The working bandwidth is large: the phase interpolator can work under a large bandwidth, and only the switch is needed to switch the charging capacitor to control the charging and discharging time under different working frequencies.
4) The applicability is strong: the high-linearity phase interpolator can be applied to a full-period digital time converter, an all-digital phase-locked loop, a clock data recovery circuit and the like, and has a wide application range.
Drawings
FIG. 1A is a schematic diagram of a conventional vector-sum phase interpolator;
FIG. 1B is a schematic diagram of a conventional charge-charging phase interpolator;
FIG. 2A is a phase interpolator basic schematic diagram that is not sensitive to parasitics;
FIG. 2B is a schematic diagram of an improved parasitically insensitive phase interpolator of the present invention;
FIG. 3 is a circuit block diagram of a parasitically insensitive phase interpolator in accordance with an embodiment of the present invention;
FIG. 4 is a block diagram of a bias circuit for a phase interpolator in accordance with an embodiment of the present invention;
fig. 5 is a graph of the linearity simulation result and the test result of the phase interpolator according to the embodiment of the present invention.
Detailed Description
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
As shown in fig. 2A, a charge-based charge-charging phase interpolator that is not sensitive to parasitics has a large parasitic capacitance C at the output node of the current sourceAAnd CB. Switch S1And S2Controlling a current source IAAnd IBCharging a charging capacitor C, the time delay of the output being dependent on the current source IAAnd IBThe ratio of (a) to (b). In this process, the parasitic capacitance CAAnd CBWill share charge with the charging capacitor C, however due to the parasitic capacitor CAAnd CBThe charge stored in the memory is determined by the integral of the current during the non-charging time, and has no linear relation with the control code, so the charge sharing process can cause the deterioration of the linearity. In the present invention, two additional switches S are used3And S4Controlling said switch S during charging1And S2Before closing, the parasitic capacitance C is connectedAAnd CBThe charge on the capacitor is completely discharged, so that charge sharing is avoided, and the linearity can be improved. In this configuration, there are also two factors that cause the linearity to deteriorate: one is the linearity degradation due to clock overlap, where the charge on the charging capacitor C passes through S1-S3And S2-S4Two paths leak; the other is a second clock signal of the phase interpolator
Figure BDA0003402088560000031
When the rising edge arrivesSaid charging capacitance C and said parasitic capacitance CAWill be connected with the parasitic capacitance CBThe charge sharing is performed, so that the charging waveform has an overcharge phenomenon, which may exceed the logic threshold of the subsequent inverter, resulting in a small delay time and introduction of nonlinearity.
Based on the above analysis, the present invention proposes an improved phase interpolator that is not sensitive to parasitics, as shown in fig. 2B. The phase interpolator is composed of N phase interpolation units, and each phase interpolation unit is different from an input two-phase clock in a mode of directly switching charging current through a switch
Figure BDA0003402088560000041
And
Figure BDA0003402088560000042
to select one of the signals
Figure BDA0003402088560000043
To control the switch S1Thereby controlling the current source I in the phase interpolation unit0And charging the charging capacitor C. Wherein the two-phase clock
Figure BDA0003402088560000044
And
Figure BDA0003402088560000045
are respectively controlled by a pair of control codes D0And
Figure BDA0003402088560000046
control, said control code D0And
Figure BDA0003402088560000047
the value is 0 or 1, and the values are opposite; the switch S1Control signal of
Figure BDA0003402088560000048
The switch S2Control signal of
Figure BDA0003402088560000049
Of opposite sign
Figure BDA00034020885600000410
Let D of the N phase interpolation units select the clock
Figure BDA00034020885600000411
As said switch S1Control signal of
Figure BDA00034020885600000412
Thus, the current source I in FIG. 1BAAnd IBThe corresponding current may be equivalent to:
IA＝(N-D)I0,IB＝DI0
it can be seen that the total charging current is fixed, equal to the current source I of the phase interpolation unit0N times. In this manner, the parasitic capacitance C in FIG. 1BAAnd CBEquivalently, the parasitic capacitance C is uniformly distributed in each phase interpolation unitAAnd CBCan be equivalent to:
CA＝(N-D)C0,CB＝DC0
wherein C is0Is the capacitance value of the parasitic capacitance in each phase interpolation unit, so that the charging process satisfies the following formula:
Figure BDA00034020885600000413
wherein VCBAnd VCARespectively at the clock
Figure BDA00034020885600000414
Before and after the rising edge of the capacitor C, the voltage of the upper plate of the charging capacitor C is shown by a formula, and the overcharge phenomenon does not exist in the charging process. In each of the phase interpolation unitsOff S2The effect of discharging the charges on the parasitic capacitor is achieved, and the charge sharing of the parasitic capacitor is avoided. In addition, at the switch S1And S2An extra inverter is used in the method, so that the problem of linearity deterioration caused by clock overlapping can be avoided.
An embodiment of the present invention provides a 9-bit parasitic-insensitive phase interpolator operating at 0.5-2.4GHz based on a standard CMOS process, and fig. 3 is a circuit structure of the phase interpolator. The input of the phase interpolator is connected to two adjacent phase signals of an eight-phase clock, i.e. the phase difference of the input signals is 45 °. And the output end of the phase interpolator is connected with the upper polar plate of the charging capacitor and outputs the upper polar plate to the phase inverter as output buffer. The phase interpolator of this embodiment consists of 71 phase interpolator units that are not sensitive to parasitics, of which 63 of the phase interpolator units have eight times the charging current of the other 8 phase interpolator units. The upper 6 bits and the lower 3 bits are both thermometer code control, and binary code control is adopted between the thermometer code control and the thermometer code control, and the coding mode is the result of compromise between precision and area power consumption overhead. The current mirror of the phase interpolation unit selects a common-gate structure, provides enough output impedance, and can ensure that the voltage rise along with the charging process does not cause obvious change of current. Voltage offset V of the phase interpolation unitX1、VX2And VBGenerated using the bias circuit of fig. 4. In addition, the charging capacitor C in FIG. 31(capacitor array) and resistor array R in FIG. 4BIn order to adapt the phase interpolator to a larger range of frequencies.
The specific circuit operation flow of the phase interpolator during working is as follows:
1. determining the working frequency of the phase interpolator, and selecting the appropriate charging capacitor C1And the capacitance value of the resistor array RBThe resistance value of (c).
2. An eight-phase clock signal is generated and used as an input signal to the phase interpolator. The eight-phase clock signal may be generated by a signal divider, a delay locked loop, or the like. In fact, the phase difference between the two input signals of the phase interpolator can be ensured to work normally as long as the phase difference is less than or equal to 90 °.
3. Determining the output phase of the phase interpolator, and selecting the control code D [65:0 ] of the phase interpolator according to the required output phase]A plurality of said phase interpolation units will be commonly coupled to said charging capacitor C1And charging is carried out.
4. Charging the capacitor C1Voltage signal V onC1Through the inverter output.
Fig. 5 shows simulation results and test results of the phase interpolator insensitive to the parasitics according to the embodiment of the present invention, where the simulation results show that the maximum phase error is 0.11 °, and the test results show that the maximum phase error is 0.18 °, which shows very high linearity.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (5)

1. A phase interpolator insensitive to parasitics, comprising one or more phase interpolation units connected in parallel, and a charging capacitor in circuit connection with said phase difference unit; each phase difference value unit is provided with a charging circuit, a grounding circuit and a clock circuit; the charging circuit is used for transmitting current of a current source to charge the charging capacitor, and a switch S is arranged on the charging circuit1(ii) a The other end of the grounding circuit opposite to the grounding end is connected with the charging circuit, and the grounding circuit is provided with a switch S2(ii) a The clock circuit is used for receiving an input two-phase clock
Figure FDA0003402088550000011
And
Figure FDA0003402088550000012
as two control signals, one for controlling the switch S1Another of said control signals for controlling said switch S2At said switch S1And S2The clock circuit in between is provided with a phase inverter.
2. The parasitically insensitive phase interpolator of claim 1, wherein the current mirror of the phase interpolation unit is a common-gate structure.
3. The parasitically insensitive phase interpolator of claim 1, wherein the two-phase clock
Figure FDA0003402088550000013
And
Figure FDA0003402088550000014
are respectively controlled by a pair of control codes D0And
Figure FDA0003402088550000015
control, said control code D0And
Figure FDA0003402088550000016
the value is 0 or 1, and the values are opposite; the switch S1Control signal of
Figure FDA0003402088550000017
The switch S2Control signal of
Figure FDA0003402088550000018
Of opposite sign
Figure FDA0003402088550000019
4. The parasitically insensitive phase of claim 1A bit interpolator, characterized in that the two-phase clock
Figure FDA00034020885500000110
And
Figure FDA00034020885500000111
is less than or equal to 90 deg.
5. The parasitically insensitive phase interpolator of claim 1, wherein the two-phase clock
Figure FDA00034020885500000112
And
Figure FDA00034020885500000113
generated by a signal divider circuit and a delay locked loop circuit.
CN202111499160.1A 2021-12-09 2021-12-09 Phase interpolator insensitive to parasitics Pending CN114157291A (en)

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Application Number Priority Date Filing Date Title
CN202111499160.1A CN114157291A (en) 2021-12-09 2021-12-09 Phase interpolator insensitive to parasitics

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