CN114157166B - Circuit for improving field intensity of diffraction optical waveguide exposure electron beam - Google Patents

Circuit for improving field intensity of diffraction optical waveguide exposure electron beam Download PDF

Info

Publication number
CN114157166B
CN114157166B CN202111511562.9A CN202111511562A CN114157166B CN 114157166 B CN114157166 B CN 114157166B CN 202111511562 A CN202111511562 A CN 202111511562A CN 114157166 B CN114157166 B CN 114157166B
Authority
CN
China
Prior art keywords
voltage
electrically connected
pin
pins
grounded
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111511562.9A
Other languages
Chinese (zh)
Other versions
CN114157166A (en
Inventor
王海时
李珂
陈开鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dragon Totem Technology Hefei Co ltd
Original Assignee
Chengdu University of Information Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chengdu University of Information Technology filed Critical Chengdu University of Information Technology
Priority to CN202111511562.9A priority Critical patent/CN114157166B/en
Publication of CN114157166A publication Critical patent/CN114157166A/en
Application granted granted Critical
Publication of CN114157166B publication Critical patent/CN114157166B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/337—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only in push-pull configuration
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/44—Circuits or arrangements for compensating for electromagnetic interference in converters or inverters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • H02M3/33515—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with digital control

Abstract

The invention relates to the technical field of optical waveguides, and discloses a circuit for improving the field intensity of a diffraction optical waveguide exposure electron beam, which comprises a low-voltage conversion module and a high-voltage parallel module which are electrically connected in sequence, wherein the input end of the low-voltage conversion module is a pin connected with a low-voltage signal, the output end of the low-voltage conversion module is a pin for outputting an N-path medium-voltage signal, the high-voltage parallel module comprises N high-voltage sub-modules which are mutually connected in parallel, the output end of the Gao Yazi module is a pin for outputting a 10KV-25KV high-voltage signal, and a time delay module is connected between every two adjacent high-voltage sub-modules; wherein the voltage of the low-voltage signal is 18V-36V, the voltage of the medium-voltage signal is 390V-410V, N is an integer, and N is more than or equal to 2. The invention solves the problems of poor field intensity improving effect, poor exposure effect and the like in the prior art.

Description

Circuit for improving field intensity of diffraction optical waveguide exposure electron beam
Technical Field
The invention relates to the technical field of optical waveguides, in particular to a circuit for improving the field intensity of a diffraction optical waveguide exposure electron beam.
Background
The existing floating gate needs to be engraved on the surface of the optical waveguide by exposure electron beams, so that the field intensity of the electron beam playfield directly affects the engraving depth and the engraving area, the existing technology adopts single-channel high-voltage conversion, namely, medium voltage is converted into high-voltage pulse through a high-voltage pulse transformer, and a voltage doubling circuit is carried to realize high-voltage direct current output, so that the transverse acceleration field intensity and the longitudinal scanning field intensity are provided for the electron beam playfield.
However, due to the constraint relation between the turn ratio of the single high-voltage pulse converter and the magnetic core, after the magnetic loss and the eddy current are considered, when the magnetic loss and the eddy current are larger, a certain volume can only realize the conversion of smaller power, the smaller power limits the field intensity, the working depth of the electron beam and the transverse scanning amplitude are smaller, when the optical waveguide floating gate with a certain area is manufactured, a workbench is required to realize the operation of realizing the qualified depth through multiple steps of scanning and multiple repeated electron beam exposure engraving, and lower precision and yield are further brought.
The prior art comprises the following steps: poor field intensity improving effect, thereby causing the problem of poor exposure and engraving effect.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a circuit for improving the field intensity of a diffraction optical waveguide exposure electron beam, and solves the problems of poor field intensity improving effect, poor exposure effect and the like in the prior art.
The invention solves the problems by adopting the following technical scheme:
the circuit for improving the field intensity of the diffraction optical waveguide exposure electron beam comprises a low-voltage conversion module and a high-voltage parallel connection module which are electrically connected in sequence, wherein the input end of the low-voltage conversion module is a pin connected with a low-voltage signal, the output end of the low-voltage conversion module is a pin for outputting N paths of medium-voltage signals, the high-voltage parallel connection module comprises N high-voltage sub-modules which are mutually connected in parallel, the output end of the Gao Yazi module is a pin for outputting 10KV-25KV high-voltage signals, and a delay module is connected between every two adjacent high-voltage sub-modules; wherein the voltage of the low-voltage signal is 18V-36V, the voltage of the medium-voltage signal is 390V-410V, N is an integer, and N is more than or equal to 2.
As a preferable technical scheme, the input end of the low-voltage conversion module is a 24V voltage input pin, and the pin of the medium-voltage signal is a 400V output pin.
As a preferred solution, n=2, and the two high-voltage sub-modules are respectively denoted as a first high-voltage sub-module and a second high-voltage sub-module.
As a preferable technical scheme, the high-voltage power supply further comprises a wiring terminal Header2, wherein the first high-voltage sub-module comprises a high-voltage package 1, a high-voltage package C13, a high-voltage package C14, a high-voltage package C15, a high-voltage package C16, a high-voltage package C19, a high-voltage package C34, a high-voltage package C35, a high-voltage package C38, a high-voltage package R39, a high-voltage package R41, a high-voltage package R42, a high-voltage package N-channel enhancement MOS transistor Q10, a high-voltage package diode D1 and a high-voltage package fuse F2, the second high-voltage sub-module comprises a high-voltage package x 2, a high-voltage package C22, a high-voltage package C23, a high-voltage package C24, a high-voltage package C25, a high-voltage package C26, a high-voltage package R50, a high-voltage package R51, a high-voltage package R52, a high-voltage package R53, a high-voltage package R54, a high-voltage package R55, a high-voltage package N-channel enhancement type MOS transistor Q13, a high-voltage package D3, a high-voltage fuse F3, pins 1, 14, 13 and F2 of the first path of medium-voltage signal output ends are electrically connected in sequence, D poles of pins 2 and Q10 of the first path of medium-voltage signal output ends are electrically connected in sequence, and nodes, 16 and ground between the C14 and the C13 are electrically connected in sequence; * Pins 2, R35, C15 of 1, pins 1 and C14 of 1 are electrically connected, and cathodes of pins 2, D2 of 1 are electrically connected, and an anode of D2 is grounded; the other end of the secondary winding of the T4 is grounded, one end of the secondary winding of the T4 is connected with a node between the R39 and one end of the secondary winding of the T4, the other end of the R41 is grounded, one end of the C19 is connected with a node between the R39 and one end of the secondary winding of the T4, the other end of the C19 is grounded, one end of the R42 is connected with a node between the g pole of the Q10 and the R39, the other end of the R42 is grounded, one ends of driving signals PWM-DRIVE1 and R38 are electrically connected, the other end of the R38 and the b pole of the Q9 are electrically connected, the C poles of the Q9, the R34 and the 5V power input ends are electrically connected, the e pole of the Q9 and one end of the primary winding of the T4 are electrically connected, the other end of the R38 and the b pole of the Q11 are electrically connected, the e pole of the Q11 is connected with a node between the e pole of the Q9 and one end of the primary winding of the T4, and the C pole of the primary winding of the Q11 is grounded, and the other end of the primary winding of the T4 is grounded; * The anodes of the pins 3 and VD1 of the power supply are electrically connected, the cathode of the VD1 is connected with the cathode of the VD2, the anode of the VD2 is connected with the pin 3 of the X2, and the node between the cathode of the VD1 and the cathode of the VD2 is connected with the pin 1 of the Header 2; * Pin 4 of 1 connects to pin 4 of 2, and the node between pin 4 of 1 and pin 4 of 2 connects to pin 2 of Header 2; * Pins 1, C23, C22 and F3 of the 2 circuit medium voltage signal output ends are electrically connected in sequence, d poles of pins 2 and Q13 of the 2 circuit medium voltage signal output ends are electrically connected, and nodes, C25 and ground between the C23 and the C22 circuit medium voltage signal output ends are electrically connected in sequence; * Pins 2, R51, C24 of 2, pins 1 and C23 of 2 are electrically connected, the cathodes of pins 2, D3 of 2 are electrically connected, and the anode of D3 is grounded; the g pole of Q13, one end of the secondary winding of R53, T5 is electrically connected, the other end of the secondary winding of T5 is grounded, one end of R54 is connected with a node between one end of the secondary winding of R53 and T5, the other end of R54 is grounded, one end of C26 is connected with a node between one end of the secondary winding of R53 and T5, the other end of C26 is grounded, one end of R55 is connected with a node between the g pole of Q13 and R53, the other end of R55 is grounded, the driving signal PWM-DRIVE2 pin, one end of R52 is electrically connected, the other end of R52 and the b pole of Q12 are electrically connected, the C pole of Q12, the R50 and 5V power input ends are electrically connected, the e pole of Q12 and one end of the primary winding of T5 are electrically connected, the other end of R52 and the b pole of Q14 are electrically connected with a node between the e pole of Q12 and one end of the primary winding of T5, the C pole of Q14 is grounded, and the other end of the primary winding of T5 is grounded; the high-voltage package is of the type HS-05-200, and the high-voltage package is of the type 1 and the type 2.
As a preferable technical scheme, the circuit further comprises a chip inverter INV1, an inverter INV2, an inverter INV3, an exclusive-OR gate XOR1, a chip U2, a chip U3, a chip U4, and PWM-DRIVE1 output pins of the chips U3, INV1, INV2, XOR1, INV3, U2, and U4 are electrically connected in sequence, the PWM-DRIVE1 output pin of the U3 is also electrically connected with U2, and a node between INV2 and XOR1 is electrically connected with U4; the models of U2 and U4 are ET3157, the model of U3 is NE555, the models of INV1, INV2 and INV3 are SN74LVC1G04, and the model of XOR1 is SN74LVC1G86.
As a preferable technical scheme, the circuit comprises C17, C18, R30, R32 and R36, wherein a pin 1 of U3 is grounded, a pin 2 of U3 is connected with a pin 6 of U3, pins 3 and C17 of U3 and PWM-DRIVE1 output ends are sequentially electrically connected, a pin 4 of U3 is connected with a 5V power input end, pins 5 and C18 of U3 are sequentially electrically connected with ground, a 5V power input end, R30, R32, R36 and ground are sequentially electrically connected, a pin 6 of U3 is connected with a node between R32 and R36, and a pin 7 of U3 is connected with a node between R30 and R32.
As a preferable technical scheme, the circuit comprises R31, R33, R37, R40, R43, R44, R45, R46, R47, R48, R49, C20 and C21, pins 1, 2 and 1 of INV1 are suspended, pins 2, 2 and 2 of INV2 are grounded, pins 5, 5 and 5 of INV1 and 2 are connected with a 5V power input end, PWM-DRIVE1 output pins, R49 and 3 of INV1 are sequentially and electrically connected, pins 4, R47, R48 and 3 of INV1 are sequentially and electrically connected, nodes between R47 and R48, C21 and ground are sequentially and electrically connected, pins 4, R45, R46 and 3 of INV1 are electrically connected, nodes between R45 and R46 are sequentially and electrically connected, and nodes between R45 and R46 are sequentially and electrically connected with pins 4 of U4; pins 1, R43 and PWM-DRIVE1 of the XOR1 are sequentially electrically connected, pin 2 of the XOR1 is grounded, pin 5 of the XOR1 is connected with a 5V power input end, pins 4, R44 and 3 of the XOR1 are sequentially electrically connected, pins 4, R31 and 1 of U2 of the INV3 are sequentially electrically connected, pins 2, R33, R37 and 1 of U4 of the INV3 are sequentially electrically connected, pin 3 of U2 is grounded, pin 5 of U2 is suspended, pin 6 of U2 is connected with a 5V power input end, pins 2 and R40 of U4 and a driving signal PWM-DRIVE2 pin are sequentially electrically connected, pin 3 of U4 is grounded, pin 5 of U4 is suspended, and pin 6 of U4 is connected with a 5V power input end.
As a preferable technical scheme, the low-voltage conversion module comprises a chip U1, a slide rheostat VR1, R2, R4, R6, R11, R15, R18, R20, R21, R23, C1, C2, C3, C4, C10, and a pin 1 of U1, a pin 4 of C4, R15, and a pin 3 of U1 are electrically connected in sequence; pin 2 of U1 connects terminal 2 of VR1, terminal 3 of VR1 is grounded, terminal 2, R4, ground of VR1 are electrically connected sequentially, terminal 2, C1, ground of VR1 are electrically connected sequentially to terminal 1, R2, R6, pin 15 of U1 are electrically connected sequentially; pins 4, R20 and ground of U1 are sequentially and electrically connected, and nodes among pins 4, R11, R2 and R6 of U1 are sequentially and electrically connected, and nodes among pins 4, C2, R2 and R6 of U1 are sequentially and electrically connected; pins 5, C10 and ground of U1 are electrically connected in sequence, and pins 6, R21 and ground of U1 are electrically connected in sequence; pin 7 of U1 is grounded; the power input ends of pins 8, R23 and 12V of the U1 are electrically connected in sequence; pin 9 of U1 is grounded; pin 10 of U1 is grounded; the power input ends of pins 11, R18 and 12V of U1 are electrically connected in sequence; pin 12 of U1 is connected with 12V power input end; pins 13, C3 and ground of U1 are electrically connected in sequence; pin 14 of U1 is connected with pin 13 of U1, pin 14 of U1 is connected with a node between R2 and R6, and pin 16 of U1 is grounded; wherein, the model of the chip U1 is TL494.
Compared with the prior art, the invention has the following beneficial effects:
(1) The invention adopts N high-voltage sub-modules which are connected in parallel to improve the power and further improve the field intensity of an electron beam playground area, thereby improving the ground carving depth in the floating gate manufacturing process, reducing the stepping times of a workbench and improving the precision and the yield;
(2) The push-pull structure with the 24V conversion of 400V is adopted, and has the advantages of small volume, high power density, wide adaptability of input voltage and ensured safety by power isolation of front and rear stages;
(3) The high-voltage module adopts a high-voltage package integrated with the voltage doubling module, so that the volume and electromagnetic interference are effectively reduced, compared with the traditional high-voltage conversion, the lumped parameter size is reduced, and the stability is improved;
(4) The isolation driving and capacitance series voltage dividing scheme is adopted, the safety is improved by the isolation driving, the interference is reduced, and the capacitance series connection provides instant high-current pulse for the energy supply of the high-voltage package, so that the power is improved;
(5) The digital logic gate structure is adopted, so that phase shifting processing of signals and generation of parallel driving signals are effectively realized, electromagnetic interference in a high-voltage environment is greatly reduced, and stability and anti-interference performance are improved while functions are realized;
(6) The low-voltage conversion is convenient to realize by adopting a simple circuit structure, and the reliability is high.
Drawings
FIG. 1 is a schematic diagram of a low voltage conversion module according to the present invention;
FIG. 2 is a second schematic diagram of the low voltage conversion module according to the present invention;
FIG. 3 is a third schematic diagram of the low voltage conversion module according to the present invention;
FIG. 4 is a schematic diagram of a low voltage conversion module according to the present invention;
FIG. 5 is a schematic diagram of a high voltage parallel module according to the present invention;
FIG. 6 is a second schematic diagram of the high voltage parallel module of the present invention;
FIG. 7 is one of the partial enlarged views of FIG. 6;
FIG. 8 is a second enlarged view of a portion of FIG. 6;
FIG. 9 is a third schematic diagram of the high voltage parallel module of the present invention;
FIG. 10 is one of the partial enlarged views of FIG. 9;
FIG. 11 is a second enlarged view of a portion of FIG. 9;
FIG. 12 is a schematic diagram of a power isolation module according to the present invention;
FIG. 13 is one of the partial enlarged views of FIG. 12;
FIG. 14 is a second enlarged view of a portion of FIG. 12;
FIG. 15 is a second schematic diagram of a power isolation module according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but embodiments of the present invention are not limited thereto.
Example 1
As shown in fig. 1 to 15, a circuit for improving the field intensity of a diffraction optical waveguide exposure electron beam comprises a low-voltage conversion module and a high-voltage parallel connection module which are electrically connected in sequence, wherein the input end of the low-voltage conversion module is a pin connected with a low-voltage signal, the output end of the low-voltage conversion module is a pin for outputting an N-path medium-voltage signal, the high-voltage parallel connection module comprises N high-voltage sub-modules which are mutually connected in parallel, the output end of the Gao Yazi module is a pin for outputting a 10KV-25KV high-voltage signal, and a delay module is connected between every two adjacent high-voltage sub-modules; wherein the voltage of the low-voltage signal is 18V-36V, the voltage of the medium-voltage signal is 390V-410V, N is an integer, and N is more than or equal to 2.
The invention adopts N high-voltage sub-modules which are connected in parallel to improve the power and further improve the field intensity of an electron beam playground area, thereby improving the ground carving depth in the floating gate manufacturing process, reducing the stepping times of a workbench and improving the precision and the yield.
As a preferable technical scheme, the input end of the low-voltage conversion module is a 24V voltage input pin, and the pin of the medium-voltage signal is a 400V output pin.
The push-pull structure with the 24V conversion of 400V has the advantages of small volume, high power density, wide adaptability of input voltage and ensured safety by power isolation of front and rear stages.
As a preferred solution, n=2, and the two high-voltage sub-modules are respectively denoted as a first high-voltage sub-module and a second high-voltage sub-module.
The high-voltage module adopts the high-voltage package integrated with the voltage doubling module, so that the volume and electromagnetic interference are effectively reduced, compared with the traditional high-voltage conversion, the lumped parameter size is reduced, and the stability is improved.
As a preferable technical scheme, the high-voltage power supply further comprises a wiring terminal Header2, wherein the first high-voltage sub-module comprises a high-voltage package 1, a high-voltage package C13, a high-voltage package C14, a high-voltage package C15, a high-voltage package C16, a high-voltage package C19, a high-voltage package C34, a high-voltage package C35, a high-voltage package C38, a high-voltage package R39, a high-voltage package R41, a high-voltage package R42, a high-voltage package N-channel enhancement MOS transistor Q10, a high-voltage package diode D1 and a high-voltage package fuse F2, the second high-voltage sub-module comprises a high-voltage package x 2, a high-voltage package C22, a high-voltage package C23, a high-voltage package C24, a high-voltage package C25, a high-voltage package C26, a high-voltage package R50, a high-voltage package R51, a high-voltage package R52, a high-voltage package R53, a high-voltage package R54, a high-voltage package R55, a high-voltage package N-channel enhancement type MOS transistor Q13, a high-voltage package D3, a high-voltage fuse F3, pins 1, 14, 13 and F2 of the first path of medium-voltage signal output ends are electrically connected in sequence, D poles of pins 2 and Q10 of the first path of medium-voltage signal output ends are electrically connected in sequence, and nodes, 16 and ground between the C14 and the C13 are electrically connected in sequence; * Pins 2, R35, C15 of 1, pins 1 and C14 of 1 are electrically connected, and cathodes of pins 2, D2 of 1 are electrically connected, and an anode of D2 is grounded; the other end of the secondary winding of the T4 is grounded, one end of the secondary winding of the T4 is connected with a node between the R39 and one end of the secondary winding of the T4, the other end of the R41 is grounded, one end of the C19 is connected with a node between the R39 and one end of the secondary winding of the T4, the other end of the C19 is grounded, one end of the R42 is connected with a node between the g pole of the Q10 and the R39, the other end of the R42 is grounded, one ends of driving signals PWM-DRIVE1 and R38 are electrically connected, the other end of the R38 and the b pole of the Q9 are electrically connected, the C poles of the Q9, the R34 and the 5V power input ends are electrically connected, the e pole of the Q9 and one end of the primary winding of the T4 are electrically connected, the other end of the R38 and the b pole of the Q11 are electrically connected, the e pole of the Q11 is connected with a node between the e pole of the Q9 and one end of the primary winding of the T4, and the C pole of the primary winding of the Q11 is grounded, and the other end of the primary winding of the T4 is grounded; * The anodes of the pins 3 and VD1 of the power supply are electrically connected, the cathode of the VD1 is connected with the cathode of the VD2, the anode of the VD2 is connected with the pin 3 of the X2, and the node between the cathode of the VD1 and the cathode of the VD2 is connected with the pin 1 of the Header 2; * Pin 4 of 1 connects to pin 4 of 2, and the node between pin 4 of 1 and pin 4 of 2 connects to pin 2 of Header 2; * Pins 1, C23, C22 and F3 of the 2 circuit medium voltage signal output ends are electrically connected in sequence, d poles of pins 2 and Q13 of the 2 circuit medium voltage signal output ends are electrically connected, and nodes, C25 and ground between the C23 and the C22 circuit medium voltage signal output ends are electrically connected in sequence; * Pins 2, R51, C24 of 2, pins 1 and C23 of 2 are electrically connected, the cathodes of pins 2, D3 of 2 are electrically connected, and the anode of D3 is grounded; the g pole of Q13, one end of the secondary winding of R53, T5 is electrically connected, the other end of the secondary winding of T5 is grounded, one end of R54 is connected with a node between one end of the secondary winding of R53 and T5, the other end of R54 is grounded, one end of C26 is connected with a node between one end of the secondary winding of R53 and T5, the other end of C26 is grounded, one end of R55 is connected with a node between the g pole of Q13 and R53, the other end of R55 is grounded, the driving signal PWM-DRIVE2 pin, one end of R52 is electrically connected, the other end of R52 and the b pole of Q12 are electrically connected, the C pole of Q12, the R50 and 5V power input ends are electrically connected, the e pole of Q12 and one end of the primary winding of T5 are electrically connected, the other end of R52 and the b pole of Q14 are electrically connected with a node between the e pole of Q12 and one end of the primary winding of T5, the C pole of Q14 is grounded, and the other end of the primary winding of T5 is grounded; the high-voltage package is of the type HS-05-200, and the high-voltage package is of the type 1 and the type 2.
The part adopts an isolation driving and capacitive series voltage division scheme, the isolation driving improves the safety, reduces the interference, and the capacitive series provides instantaneous high-current pulse for the energy supply of the high-voltage package, thereby being beneficial to the power improvement.
As a preferable technical scheme, the circuit further comprises a chip inverter INV1, an inverter INV2, an inverter INV3, an exclusive-OR gate XOR1, a chip U2, a chip U3, a chip U4, and PWM-DRIVE1 output pins of the chips U3, INV1, INV2, XOR1, INV3, U2, and U4 are electrically connected in sequence, the PWM-DRIVE1 output pin of the U3 is also electrically connected with U2, and a node between INV2 and XOR1 is electrically connected with U4; the models of U2 and U4 are ET3157, the model of U3 is NE555, the models of INV1, INV2 and INV3 are SN74LVC1G04, and the model of XOR1 is SN74LVC1G86.
The digital logic gate structure is adopted in the part, so that phase shift processing of signals and generation of parallel driving signals are effectively realized, electromagnetic interference in a high-voltage environment is greatly reduced, and stability and anti-interference performance are improved while functions are realized.
As a preferable technical scheme, the circuit comprises C17, C18, R30, R32 and R36, wherein a pin 1 of U3 is grounded, a pin 2 of U3 is connected with a pin 6 of U3, pins 3 and C17 of U3 and PWM-DRIVE1 output ends are sequentially electrically connected, a pin 4 of U3 is connected with a 5V power input end, pins 5 and C18 of U3 are sequentially electrically connected with ground, a 5V power input end, R30, R32, R36 and ground are sequentially electrically connected, a pin 6 of U3 is connected with a node between R32 and R36, and a pin 7 of U3 is connected with a node between R30 and R32.
Such a circuit configuration is easy to build.
As a preferable technical scheme, the circuit comprises R31, R33, R37, R40, R43, R44, R45, R46, R47, R48, R49, C20 and C21, pins 1, 2 and 1 of INV1 are suspended, pins 2, 2 and 2 of INV2 are grounded, pins 5, 5 and 5 of INV1 and 2 are connected with a 5V power input end, PWM-DRIVE1 output pins, R49 and 3 of INV1 are sequentially and electrically connected, pins 4, R47, R48 and 3 of INV1 are sequentially and electrically connected, nodes between R47 and R48, C21 and ground are sequentially and electrically connected, pins 4, R45, R46 and 3 of INV1 are electrically connected, nodes between R45 and R46 are sequentially and electrically connected, and nodes between R45 and R46 are sequentially and electrically connected with pins 4 of U4; pins 1, R43 and PWM-DRIVE1 of the XOR1 are sequentially electrically connected, pin 2 of the XOR1 is grounded, pin 5 of the XOR1 is connected with a 5V power input end, pins 4, R44 and 3 of the XOR1 are sequentially electrically connected, pins 4, R31 and 1 of U2 of the INV3 are sequentially electrically connected, pins 2, R33, R37 and 1 of U4 of the INV3 are sequentially electrically connected, pin 3 of U2 is grounded, pin 5 of U2 is suspended, pin 6 of U2 is connected with a 5V power input end, pins 2 and R40 of U4 and a driving signal PWM-DRIVE2 pin are sequentially electrically connected, pin 3 of U4 is grounded, pin 5 of U4 is suspended, and pin 6 of U4 is connected with a 5V power input end.
The digital logic gate structure is adopted in the part, so that phase shift processing of signals and generation of parallel driving signals are effectively realized, electromagnetic interference in a high-voltage environment is greatly reduced, and stability and anti-interference performance are improved while functions are realized.
As a preferable technical scheme, the low-voltage conversion module comprises a chip U1, a slide rheostat VR1, R2, R4, R6, R11, R15, R18, R20, R21, R23, C1, C2, C3, C4, C10, and a pin 1 of U1, a pin 4 of C4, R15, and a pin 3 of U1 are electrically connected in sequence; pin 2 of U1 connects terminal 2 of VR1, terminal 3 of VR1 is grounded, terminal 2, R4, ground of VR1 are electrically connected sequentially, terminal 2, C1, ground of VR1 are electrically connected sequentially to terminal 1, R2, R6, pin 15 of U1 are electrically connected sequentially; pins 4, R20 and ground of U1 are sequentially and electrically connected, and nodes among pins 4, R11, R2 and R6 of U1 are sequentially and electrically connected, and nodes among pins 4, C2, R2 and R6 of U1 are sequentially and electrically connected; pins 5, C10 and ground of U1 are electrically connected in sequence, and pins 6, R21 and ground of U1 are electrically connected in sequence; pin 7 of U1 is grounded; the power input ends of pins 8, R23 and 12V of the U1 are electrically connected in sequence; pin 9 of U1 is grounded; pin 10 of U1 is grounded; the power input ends of pins 11, R18 and 12V of U1 are electrically connected in sequence; pin 12 of U1 is connected with 12V power input end; pins 13, C3 and ground of U1 are electrically connected in sequence; pin 14 of U1 is connected with pin 13 of U1, pin 14 of U1 is connected with a node between R2 and R6, and pin 16 of U1 is grounded; wherein, the model of the chip U1 is TL494.
This facilitates low-voltage conversion with a simple circuit configuration and high reliability.
Example 2
As shown in fig. 1 to 15, as a further optimization of embodiment 1, this embodiment includes all the technical features of embodiment 1, and in addition, this embodiment further includes the following technical features:
the technology for improving the field intensity of the electron beam playfield in the floating gate manufacturing process of the current diffractive optical waveguide provides a high-voltage power parallel connection technology, and two or even a plurality of high-voltage converters with the same specification are output in parallel connection to improve the power, so that the field intensity of the electron beam playfield is improved, the ground carving depth in the floating gate manufacturing process is improved, the stepping times of a workbench are reduced, and the precision and the yield are improved.
The first part is a low-voltage conversion part, and the main function is to convert 24V direct current into 400V direct current and supply power for the high-voltage package.
The PWM generator comprises a PWM generating circuit taking U1 (TL 494) as a core, wherein the U1 is in a push-pull working mode in the generator part, namely, two paths of generated PWM1 and PWM2 driving waveforms are in a complementary mode, then the two paths of driving waveforms are respectively sent into corresponding totem pole driving, the totem pole driving is mainly used for pushing a driving transformer, driving signals are transmitted to the next stage through the transformer, electric isolation is realized, the safety is ensured, the waveforms obtained through the transformation of the driving transformer are PWMA/PWMB respectively, the waveforms are sent into a push-pull topology, the voltage is increased to 400V through the push-pull transformer, and then 400V direct current is obtained through rectification and filtering. The output voltage is fed back to U1 (TL 494) linearly through optocoupler isolation, so that the duty ratio of PWM1 and PWM2 is controlled, and output stability is realized.
Push-pull portion: the 24V input end is an F1 fuse, and Q2 and Q3 are in parallel connection; q6 and Q7 are connected in parallel for improving power, conversion is realized through a push-pull transformer (T2), and 400V direct current (OUT-400) is obtained through six thousand and capacitive filtering. The IC1 (optocoupler) realizes photoelectric isolation of front and back stages, so that the electric connection between the output and the control system is isolated, three-stage isolation of the control side, the input side and the output side is realized, and the safety is ensured.
The second part is a high-voltage parallel part, which comprises the generation, the processing and the power parallel of the driving signals, and in order to realize the parallel connection of the high-voltage converters with the same specification under the specific high-voltage condition, the control strategy is to slightly shorten the high-level time of the driving signals of the subordinate (second) high-voltage converters than the high-level time of the driving signals of the main (first) high-voltage converters, reduce the high-voltage impulse of the two converters and realize the purpose of parallel connection.
The driving signal is generated, because the frequency of the driving signal is not high, U3 (NE 555) is used as a signal source, the generated PWM signal is PWM_DRIVE1, the signal is delayed by two-stage (or multi-stage) inverters to obtain a delayed signal PWM_DRIVE1_DELAY, the signal and the PWM_DRIVE1 are simultaneously sent to an exclusive OR circuit (formed by an exclusive OR gate and an inverter) to realize exclusive OR logic operation, the obtained signal is sent to two serially connected analog switches, when the PWM_DRIVE1 and the PWM_DRIVE1_DELAY are both in high level, the conduction is realized, the obtained signal is PWM_DEIVE2, at the moment, the output states of the PWM_DEIVE1 and the PWM_DEIVE2 meet the designed driving requirement, the two signals are respectively sent to a totem for driving, the isolation conversion is realized, then the high voltage of 10KV-25 can be obtained through high-voltage package driving, the inverter chip is 74LVC1G04, the exclusive OR gate chip is 74LVC1G 3157, and the analog switch is the ET.
In the high voltage converting section, the high voltage packet drive is an LC drive. The high-voltage package is not limited to the laser high-voltage package, and may be an assembly of a high-voltage transformer and a voltage doubler circuit.
The output ends of the two high-voltage converters are connected in parallel through the high-voltage silicon stacks, so that output current and power are improved, and the high-voltage silicon stacks are used for preventing current flowing backwards due to faults and guaranteeing safety.
The third part is a power isolation conversion part. The part is a standard flyback circuit, the main control chip is UC2844, the part is used for realizing the conversion of 24V direct current into 12V direct current and the electric isolation of input and output, and the 5V direct current is used for realizing the conversion of 12V direct current into 5V direct current by using a linear voltage stabilizing chip 7805.
The invention has the following characteristics:
1. low voltage conversion
The 24V low-voltage input is adopted, the voltage compatibility and stability are mainly considered, the instability and messiness of a 220V mains supply are considered, and stable output is not facilitated, so that the stable 24V direct current input is used, and the stability and the cleanliness of an input power supply are ensured. 400V medium-voltage conversion is realized by adopting push-pull topology, and the effects of small volume and high power can be achieved.
The push-pull boosting scheme of low-voltage conversion and the flyback scheme of power supply isolation are both the prior art and are not repeated.
2. High voltage conversion
In the high-voltage parallel connection, the high-voltage impulse is mainly caused by asynchronous output of parallel output ends, and further, equipment is damaged due to too high stress, so that the high pulse of the parallel module is creatively in a state of being contained and contained in a control strategy, the phase difference time is shorter, the output high-voltage impulse can be reduced, the working time of the high-voltage silicon stack at the output side is reduced, and the efficiency is improved.
The high-voltage power is connected in parallel, and mainly depends on the characteristics of driving signals among different modules. The connection and method of this part are necessary.
The high-voltage conversion circuit of the high-voltage parallel connection part is mainly used for driving the conversion realized by the high-voltage package, and a capacitive series voltage division and resonance method is used at the high-voltage conversion circuit, so that the safety is improved unlike the current direct driving method.
3. Isolated power supply
The system comprises low-voltage input, medium-voltage conversion and high-voltage output, and the existence of three voltages can lead to stray interference at a low-potential end and serious safety accidents, so that a power supply and a control part are isolated electrically, the input voltage and the power supply of a control signal, the medium voltage and the output high voltage are isolated from each other, the isolation means mainly comprise a high-frequency isolation transformer, an optical coupler is used in a loop, the electrical isolation of different parts is realized, and the safety of the system is ensured.
According to the invention, the high-voltage output power is increased, so that the field intensity of the electron beam playground area is increased, the operation depth of the electron beam in the longitudinal field area and the scanning range of the transverse field area are increased, the stepping times and the repetition times of the workbench are reduced, and the precision and the yield are increased.
As described above, the present invention can be preferably implemented.
The foregoing description of the preferred embodiment of the invention is not intended to limit the invention in any way, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the invention.

Claims (5)

1. The circuit for improving the field intensity of the diffraction optical waveguide exposure electron beam is characterized by comprising a low-voltage conversion module and a high-voltage parallel connection module which are electrically connected in sequence, wherein the input end of the low-voltage conversion module is a pin connected with a low-voltage signal, the output end of the low-voltage conversion module is a pin for outputting an N-path medium-voltage signal, the high-voltage parallel connection module comprises N high-voltage sub-modules which are mutually connected in parallel, the output end of the Gao Yazi module is a pin for outputting a 10KV-25KV high-voltage signal, and a delay module is connected between every two adjacent high-voltage sub-modules; the voltage of the low-voltage signal is 18V-36V, the voltage of the medium-voltage signal is 390V-410V, and N=2;
the input end of the low-voltage conversion module is a 24V voltage input pin, and the pin of the medium-voltage signal is a 400V output pin;
the two high-voltage sub-modules are respectively marked as a first high-voltage sub-module and a second Gao Yazi module;
the high-voltage power supply circuit comprises a first high-voltage submodule and a second high-voltage submodule, wherein the first high-voltage submodule comprises a high-voltage packet 1, a capacitor C13, a capacitor C14, a resistor C15, a capacitor C16, a resistor C19, a resistor R34, a resistor R35, a resistor R38, a resistor R39, a resistor R41, a resistor R42, an N-channel enhancement type MOS transistor Q10, a diode D1, a fuse F2, an NPN triode Q9, a PNP triode Q11, a transformer T4 and a diode VD1, the second high-voltage submodule comprises a high-voltage packet 2, a capacitor C22, a capacitor C23, a capacitor C24, a capacitor C25, a capacitor C26, a resistor R50, a resistor R51, a resistor R52, a resistor R53, a resistor R54, a resistor R55, an N-channel enhancement type MOS transistor Q13, a diode D3, a fuse F3, a NPN triode Q12, a PNP triode Q14, a transformer T5 and a diode VD2, pins 1, a capacitor C14, a capacitor C13 and a first path signal output end are sequentially electrically connected, a pin 2 of the high-voltage packet 1, a capacitor D14, a capacitor D10 and a capacitor D14 are sequentially connected, and a medium-voltage node C16 are sequentially connected; pins 2, R35 and C15 of the high-voltage packet 1 and nodes between pins 1 and C14 of the high-voltage packet 1 are electrically connected, cathodes of pins 2 and D2 of the high-voltage packet 1 are electrically connected, and an anode of D2 is grounded; the other end of the secondary winding of the T4 is grounded, one end of the secondary winding of the T4 is connected with a node between the R39 and one end of the secondary winding of the T4, the other end of the R41 is grounded, one end of the C19 is connected with a node between the R39 and one end of the secondary winding of the T4, the other end of the C19 is grounded, one end of the R42 is connected with a node between the g pole of the Q10 and the R39, the other end of the R42 is grounded, one ends of driving signals PWM-DRIVE1 and R38 are electrically connected, the other end of the R38 and the b pole of the Q9 are electrically connected, the C poles of the Q9, the R34 and the 5V power input ends are electrically connected, the e pole of the Q9 and one end of the primary winding of the T4 are electrically connected, the other end of the R38 and the b pole of the Q11 are electrically connected, the e pole of the Q11 is connected with a node between the e pole of the Q9 and one end of the primary winding of the T4, and the C pole of the primary winding of the Q11 is grounded, and the other end of the primary winding of the T4 is grounded; the anodes of pins 3 and VD1 of the high-voltage packet are electrically connected, the cathode of the VD1 is connected with the cathode of the VD2, the anode of the VD2 is connected with pin 3 of the high-voltage packet 2, and the node between the cathode of the VD1 and the cathode of the VD2 is connected with pin 1 of the Header 2; pin 4 of high voltage packet 1 is connected with pin 4 of high voltage packet 2, and node between pin 4 of high voltage packet 1 and pin 4 of high voltage packet 2 is connected with pin 2 of Header 2; pins 1, C23, C22 and F3 of the high-voltage packet x 2 and the second path of medium-voltage signal output ends are sequentially and electrically connected, d poles of pins 2 and Q13 of the high-voltage packet x 2 are electrically connected, and nodes between C23 and C22, C25 and ground are sequentially and electrically connected; pins 2, R51 and C24 of the high-voltage packet x 2 and nodes between pins 1 and C23 of the high-voltage packet x 2 are electrically connected, cathodes of pins 2 and D3 of the high-voltage packet x 2 are electrically connected, and an anode of D3 is grounded; the g pole of Q13, one end of the secondary winding of R53, T5 is electrically connected, the other end of the secondary winding of T5 is grounded, one end of R54 is connected with a node between one end of the secondary winding of R53 and T5, the other end of R54 is grounded, one end of C26 is connected with a node between one end of the secondary winding of R53 and T5, the other end of C26 is grounded, one end of R55 is connected with a node between the g pole of Q13 and R53, the other end of R55 is grounded, the driving signal PWM-DRIVE2 pin, one end of R52 is electrically connected, the other end of R52 and the b pole of Q12 are electrically connected, the C pole of Q12, the R50 and 5V power input ends are electrically connected, the e pole of Q12 and one end of the primary winding of T5 are electrically connected, the other end of R52 and the b pole of Q14 are electrically connected with a node between the e pole of Q12 and one end of the primary winding of T5, the C pole of Q14 is grounded, and the other end of the primary winding of T5 is grounded; the high-voltage package is of the type HS-05-200, and the high-voltage package is of the type 1 and the type 2.
2. The circuit for increasing the field strength of a diffracted optical waveguide exposure electron beam according to claim 1, wherein the high voltage parallel module comprises a chip inverter INV1, an inverter INV2, an inverter INV3, an exclusive or gate XOR1, a chip U2, a chip U3, a chip U4, a PWM-DRIVE1 output pin of U3, INV1, INV2, XOR1, INV3, U2, U4 electrically connected in sequence, a PWM-DRIVE1 output pin of U3 further electrically connected to U2, a node between INV2 and XOR1 electrically connected to U4; the models of U2 and U4 are ET3157, the model of U3 is NE555, the models of INV1, INV2 and INV3 are SN74LVC1G04, and the model of XOR1 is SN74LVC1G86.
3. The circuit for increasing the field strength of a diffracted optical waveguide exposure electron beam according to claim 2, wherein the high voltage parallel module comprises capacitors C17, C18, resistors R30, R32, R36, pin 1 of U3 is grounded, pin 2 of U3 is connected to pin 6 of U3, pins 3, C17, PWM-DRIVE1 output of U3 are electrically connected in sequence, pin 4 of U3 is connected to a 5V power input, pins 5, C18, ground of U3 are electrically connected in sequence, a 5V power input, R30, R32, R36, ground are electrically connected in sequence, pin 6 of U3 is connected to a node between R32 and R36, and pin 7 of U3 is connected to a node between R30 and R32.
4. The circuit for increasing the field strength of a diffracted optical waveguide exposure electron beam according to claim 3, wherein the high-voltage parallel module comprises resistors R31, R33, R37, R40, R43, R44, R45, R46, R47, R48, R49, capacitors C20, C21, pins 1, 1 of INV2, and 1 of INV3 of INV1 are suspended, pins 2, and 2 of INV2 are grounded, pins 5, and 5 of INV1 are connected to a 5V power input, pins PWM-DRIVE1 output, R49, and 3 of INV1 are electrically connected in sequence, pins 4, R47, R48, and 3 of INV2 are electrically connected in sequence, a node between R47 and R48, C21, and ground are electrically connected in sequence, pins 4, R45, R46, and 3 of XOR1 are electrically connected in sequence, a node between R45 and R46, C20, and a node between R45 and a node between R46 is electrically connected in sequence; pins 1, R43 and PWM-DRIVE1 of the XOR1 are sequentially electrically connected, pin 2 of the XOR1 is grounded, pin 5 of the XOR1 is connected with a 5V power input end, pins 4, R44 and 3 of the XOR1 are sequentially electrically connected, pins 4, R31 and 1 of U2 of the INV3 are sequentially electrically connected, pins 2, R33, R37 and 1 of U4 of the INV3 are sequentially electrically connected, pin 3 of U2 is grounded, pin 5 of U2 is suspended, pin 6 of U2 is connected with a 5V power input end, pins 2 and R40 of U4 and a driving signal PWM-DRIVE2 pin are sequentially electrically connected, pin 3 of U4 is grounded, pin 5 of U4 is suspended, and pin 6 of U4 is connected with a 5V power input end.
5. The circuit for increasing field intensity of a diffracted light waveguide exposure electron beam of claim 4 wherein the low voltage conversion module comprises a chip U1, a slide varistor VR1, resistors R2, R4, R6, R11, R15, R18, R20, R21, R23. The capacitors C1, C2, C3, C4 and C10, and the pins 1, C4, R15 and 3 of the U1 are electrically connected in sequence; pin 2 of U1 connects terminal 2 of VR1, terminal 3 of VR1 is grounded, terminal 2, R4, ground of VR1 are electrically connected sequentially, terminal 2, C1, ground of VR1 are electrically connected sequentially, terminal 1, R2, R6 of VR1, pin 15 of U1 are electrically connected sequentially; pins 4, R20 and ground of U1 are sequentially and electrically connected, and nodes among pins 4, R11, R2 and R6 of U1 are sequentially and electrically connected, and nodes among pins 4, C2, R2 and R6 of U1 are sequentially and electrically connected; pins 5, C10 and ground of U1 are electrically connected in sequence, and pins 6, R21 and ground of U1 are electrically connected in sequence; pin 7 of U1 is grounded; the power input ends of pins 8, R23 and 12V of the U1 are electrically connected in sequence; pin 9 of U1 is grounded; pin 10 of U1 is grounded; the power input ends of pins 11, R18 and 12V of U1 are electrically connected in sequence; pin 12 of U1 is connected with 12V power input end ； Pins 13, C3 and ground of U1 are electrically connected in sequence; pin 14 of U1 is connected with pin 13 of U1, pin 14 of U1 is connected with a node between R2 and R6, and pin 16 of U1 is grounded; wherein, the model of the chip U1 is TL494.
CN202111511562.9A 2021-12-06 2021-12-06 Circuit for improving field intensity of diffraction optical waveguide exposure electron beam Active CN114157166B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111511562.9A CN114157166B (en) 2021-12-06 2021-12-06 Circuit for improving field intensity of diffraction optical waveguide exposure electron beam

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111511562.9A CN114157166B (en) 2021-12-06 2021-12-06 Circuit for improving field intensity of diffraction optical waveguide exposure electron beam

Publications (2)

Publication Number Publication Date
CN114157166A CN114157166A (en) 2022-03-08
CN114157166B true CN114157166B (en) 2023-06-09

Family

ID=80450684

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111511562.9A Active CN114157166B (en) 2021-12-06 2021-12-06 Circuit for improving field intensity of diffraction optical waveguide exposure electron beam

Country Status (1)

Country Link
CN (1) CN114157166B (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101312330A (en) * 2008-05-09 2008-11-26 合肥雷科电子科技有限公司 High voltage power source of resonant transformer
CN101510732A (en) * 2009-04-03 2009-08-19 桂林狮达机电技术工程有限公司 Control method for electron beam punching machine acceleration high-voltage power supply and power supply device

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04140068A (en) * 1990-09-30 1992-05-14 Toshiba Lighting & Technol Corp Power source circuit
FR2728121B1 (en) * 1994-12-07 1997-01-31 Commissariat Energie Atomique CONTROL DEVICE FOR A HIGH-CURRENT INSULATED GRID SWITCH, AND PULSE SWITCH COMPRISING SUCH A DEVICE
JP2001006894A (en) * 1999-06-21 2001-01-12 Denso Corp High-pressure discharge lamp device for automobile
CN100530925C (en) * 2006-09-22 2009-08-19 群康科技(深圳)有限公司 Multi-channel DC voltage stabilization output circuit
CN101071975A (en) * 2007-04-06 2007-11-14 华中科技大学 Dual three-level phase-shift high-voltage high-power frequency transformer
CN101075783B (en) * 2007-06-01 2010-05-26 武汉大学 Three-phase medium-frequency DC high-voltage power supply for ESP
CN102237800B (en) * 2010-04-28 2014-06-25 中国科学院电子学研究所 Forestage energy-accumulating alternative feed type high-voltage transformer suitable for broad pulse load
CN102497038A (en) * 2011-11-28 2012-06-13 中国人民解放军徐州空军学院 Multi-winding double-salient-pole generator and output transformation and control device
AT512780B1 (en) * 2012-06-13 2013-11-15 Fronius Int Gmbh Switching power supply and inverter and strand monitoring with such a switching power supply
CN206611346U (en) * 2017-03-10 2017-11-03 西安恒飞电子科技有限公司 A kind of distributed high-power high-voltage power supply
CN107910893B (en) * 2017-11-22 2020-05-22 国网山东省电力公司电力科学研究院 User-oriented multi-type distributed power supply integration networking system and control method
CN209389756U (en) * 2018-11-30 2019-09-13 比亚迪股份有限公司 Electric car and electric car fill distribution assembly
CN214069652U (en) * 2021-01-08 2021-08-27 深圳市昔诺达科技有限公司 Quick charger of smart machine

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101312330A (en) * 2008-05-09 2008-11-26 合肥雷科电子科技有限公司 High voltage power source of resonant transformer
CN101510732A (en) * 2009-04-03 2009-08-19 桂林狮达机电技术工程有限公司 Control method for electron beam punching machine acceleration high-voltage power supply and power supply device

Also Published As

Publication number Publication date
CN114157166A (en) 2022-03-08

Similar Documents

Publication Publication Date Title
CN108683347B (en) Seven-level inverter topological structure based on voltage doubling circuit and seven-level inverter
CN209982336U (en) Three-level Boost converter and photovoltaic system
CN114157166B (en) Circuit for improving field intensity of diffraction optical waveguide exposure electron beam
CN106452026A (en) Dual-isolated IGBT driving circuit and realization method therefor
JP7397976B2 (en) Interface circuits, strings and systems applied to power line communications
CN110113012A (en) A kind of circuit topology and method improving linear power amplifier efficiency
WO2021258935A1 (en) High-buck modular direct-current power supply
CN213937863U (en) Synchronous driving circuit of array type silicon controlled high-voltage large-current pulse switch
JPH08172772A (en) Transistor driving floating power supply
CN112735932B (en) Digital control pulse modulation circuit for traveling wave tube
CN113078832A (en) High-voltage pulse modulation power supply for klystron and klystron system
CN216437038U (en) Optical waveguide exposure power boosting circuit with isolation function
KR101230862B1 (en) Inverter apparatus for driving multilevel with a single input source
CN113193760A (en) Power electronic transformer with energy storage device
TW202127781A (en) Novel tt control zvs power inversion circuits
CN212909461U (en) Drive circuit structure of multichannel PWM output
CN215268215U (en) High-speed pulse modulation circuit applied to high-power solid-state amplifier
CN211266771U (en) Single-drive power tube series connection type seabed high-voltage direct current converter
CN220457143U (en) Multi-unit synchronous driving circuit
CN218335983U (en) Trigger circuit for coupling drive signal of current transformer
CN108988618A (en) The synchronous drive circuit with overcurrent protection and negative voltage bias based on Magnetic isolation
CN102916606A (en) Novel AC pulse power supply device
CN219999229U (en) Flyback transformer parallel circuit
CN211321219U (en) Resonance isolation booster circuit
CN220273660U (en) Signal switching circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
TA01 Transfer of patent application right

Effective date of registration: 20230511

Address after: No.24, Xuefu Road Section 1, Southwest Airport Economic Development Zone, Shuangliu District, Chengdu, Sichuan 610225

Applicant after: CHENGDU University OF INFORMATION TECHNOLOGY

Address before: 610000 No. 2006 West Yuan Road, Chengdu high tech Zone (West District), Sichuan

Applicant before: University of Electronic Science and Technology of China

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right

Effective date of registration: 20231219

Address after: 230000 floor 1, building 2, phase I, e-commerce Park, Jinggang Road, Shushan Economic Development Zone, Hefei City, Anhui Province

Patentee after: Dragon totem Technology (Hefei) Co.,Ltd.

Address before: No.24, Xuefu Road Section 1, Southwest Airport Economic Development Zone, Shuangliu District, Chengdu, Sichuan 610225

Patentee before: CHENGDU University OF INFORMATION TECHNOLOGY

TR01 Transfer of patent right