CN108683347B - Seven-level inverter topology and seven-level inverter based on voltage doubler circuit - Google Patents

Abstract

The invention discloses a seven-level inverter topological structure based on a voltage doubling circuit, which comprises a Boost main circuit, a full-bridge single-phase inverter main circuit and an auxiliary circuit(ii) a The Boost main circuit comprises an inductor L₁Diode D₁A first switch tube S₁The full-bridge single-phase inverter main circuit comprises a tenth switching tube S₁₀The eleventh switch tube S₁₁The twelfth switch tube S₁₂Thirteenth switch tube S₁₃(ii) a A seven-level inverter is also disclosed. The seven-level inverter is realized by effectively adjusting the bus by controlling the switching-on of the switching tube. Compared with the traditional seven-level inverter, the topological structure uses fewer switching tubes, the voltage gain can reach 30 times of steady-state gain, and the seven-level inverter is suitable for inverters with low-voltage (photovoltaic, super-capacitor and the like) input; the voltage stress of part of the switch tubes is reduced, the switching loss of the switch tubes is reduced, and the system reliability is improved.

Description

Seven-level inverter topology and seven-level inverter based on voltage doubler circuit

technical field

The invention belongs to the technical field of power electronic converters, and in particular relates to a seven-level inverter topology structure based on a voltage doubling circuit and a seven-level inverter.

Background technique

With the increase of the voltage and capacity requirements of the actual system, the traditional converter can no longer meet the actual demand. If the two-level converter is used in high-voltage and large-capacity applications, it will appear: the voltage and current of the converter are seriously distorted, the increase in switching times makes the voltage conversion rate too large, and the surge voltage will increase the loss of the switching tube and reduce the system efficiency.

The multi-level converter has the advantages of easy realization of high voltage and large capacity, low voltage of the switch tube, many output levels, and small output voltage harmonics. Multilevel inverter topologies mainly include diode clamp, flying capacitor and cascade. The number of diodes in a diode-clamped multi-level inverter increases sharply with the increase of the number of levels; the voltage at the midpoint of the DC bus above three levels is difficult to balance; affected by the dispersion and stray parameters of the clamping diodes, The voltage experienced by each clamp diode is not uniform. The number of capacitors of a flying capacitor type multilevel inverter increases sharply with the increase of the number of levels. Cascaded multi-level inverters require an independent DC power supply, or use a multi-winding phase-shifting transformer, which is bulky and costly.

SUMMARY OF THE INVENTION

In view of this, the main purpose of the present invention is to provide a seven-level inverter topology and a seven-level inverter based on a voltage doubling circuit.

In order to achieve the above object, the technical scheme of the present invention is achieved in this way:

The embodiment of the present invention improves a seven-level inverter topology structure based on a voltage doubler circuit, which includes a Boost boost main circuit, a full-bridge single-phase inverter main circuit, and an auxiliary circuit; the Boost boost main circuit includes an inductor L ₁ , diode D ₁ , first switch S ₁ , the full-bridge single-phase inverter main circuit includes a tenth switch S ₁₀ , an eleventh switch S ₁₁ , a twelfth switch S ₁₂ , and a tenth switch S 10 . Three switches S ₁₃ , the auxiliary circuit includes a second switch S ₂ , a third switch S ₃ , a fourth switch S ₄ , a fifth switch S ₅ , a sixth switch S ₆ , and a seventh switch S ₇ , the eighth switch S ₈ , the ninth switch S ₉ , the first capacitor C ₁ , the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ , the positive pole of the bus voltage passes through the inductor L ₁ in sequence , diode D ₁ , fifth switch tube S ₅ , seventh switch tube S ₇ , eighth switch tube S ₈ , twelfth switch tube S ₁₂ , and thirteenth switch tube S ₁₃ are connected to the negative pole of the bus voltage. The first capacitor C ₁ is connected in parallel between the positive and negative poles of the bus voltage and one end is connected between the positive pole of the bus voltage and the inductor L ₁ , and the series-connected second switch tube S ₂ and the second capacitor C ₂ are connected in parallel with the bus voltage Between the positive and negative poles of the bus voltage and _one end is connected between the diode D1 and the _fifth switch tube S5, the series connected _third capacitor C3 and the _fourth switch tube S4 are connected in parallel between the positive and negative poles of the bus voltage and One end is connected between the _fifth switch tube S5 and the _seventh switch tube S7, the fourth capacitor _C4 and the ninth switch tube _S9 connected in series are connected in parallel between the positive and negative poles of the bus voltage, and one end is connected to the first Between the eighth switch tube _S8 and the twelfth switch tube _S12 , the _tenth switch tube S10 and the _eleventh switch tube S11 connected in series are connected in parallel between the positive and negative poles of the bus voltage and one end is connected to the eighth switch tube S10. between the switch tube _S8 and the twelfth switch tube _S12 ; the two ends of the _third switch tube S3 are respectively connected between the _second switch tube S2 and the _second capacitor C2, and the _third capacitor C3 and the _fourth switch S4, one end of the sixth switch _S6 is connected between the _fifth switch S5 and the _seventh switch S7, and the other end is connected to the fourth capacitor _C4 and the ninth between the switch tubes _S9 ; the voltage output terminal is connected between the tenth switch tube _S10 and the _eleventh switch tube S11, and between the twelfth switch tube _S12 and the thirteenth switch tube _S13 ; the The common connection point of the diode D ₁ , the second switch tube S ₂ , and the fifth switch tube S ₅ is also directly connected to the common connection point of the eighth switch tube S ₈ and the fourth capacitor C ₄ through one path.

In the above solution, the first working state of the seven-level inverter topology structure based on the voltage doubling circuit: the _first switch S1 is turned on, and the bus voltage V _in stores energy in the inductor L1 _; tenth The switch tube _S10 and the twelfth switch tube _S12 are turned on, and the output voltage U _ab is 0; the energy of the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ remains unchanged;

The second working state: the first switch S ₁ is turned off, the bus voltage V _in and the inductor L ₁ simultaneously provide energy to the full-bridge single-phase inverter main circuit; the second switch S ₂ and the fourth switch S _4. The fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the ninth switch S ₉ are turned on; the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C _4. The voltages at both ends of the parallel connection are fully charged to V _boost , and the bus voltage is equal to V _boost at this time; the _tenth switch S10 and the thirteenth switch _S13 are turned on, and the output voltage is V _boost ;

The third working state: the third switch tube S ₃ , the fifth switch tube S ₅ , the seventh switch tube S ₇ , the eighth switch tube S ₈ , and the tenth switch tube S ₁₀ are turned on; the second capacitor _C2 and the _third capacitor C3 are connected in series while the fourth capacitor _C4 is disconnected, the bus voltage is equal to 2*V _boost ; the _tenth switch S10 and the thirteenth switch _S13 are turned on, and the output voltage is 2* V _boost ;

The fourth working state: the third switch tube S ₃ , the fifth switch tube S ₅ , and the sixth switch tube S ₆ are turned on; the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ In series connection, the bus voltage is equal to 3*V _boost ; the _tenth switch S10 and the thirteenth switch _S13 are turned on, and the output voltage is 3*V _boost .

The fifth working state: the _first switch S1 is turned on, the bus voltage V _in stores energy in the inductor L1 _; the eleventh switch _S11 and the thirteenth switch _S13 are turned on, and the output voltage U _ab is 0; the energy of the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ remains unchanged;

The sixth working state: the first switch S ₁ is turned off, the bus voltage V _in and the inductor L ₁ simultaneously provide energy to the full-bridge single-phase inverter main circuit; the second switch S ₂ and the fourth switch The tube S ₄ , the fifth switch tube S ₅ , the seventh switch tube S ₇ , the eighth switch tube S ₈ , and the ninth switch tube S ₉ are turned on. The voltages at both ends of the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ are connected in parallel to be fully charged to V _boost , and the bus voltage is equal to V _boost at this time. The switches _S11 and _S12 are turned on, and the output voltage is -V _boost ;

The seventh working state: the third switch S ₃ , the fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the tenth switch S ₁₀ are turned on. The second capacitor C ₂ and the third capacitor C ₃ are connected in series while the fourth capacitor C ₄ is disconnected, and the bus voltage is equal to 2*V _boost ; the eleventh switch _S11 and the twelfth switch _S12 are turned on , the output voltage is -2*V _boost ;

The eighth working state: the third switch S ₃ , the fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the tenth switch S ₁₀ are turned on. The second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ are connected in series, and the bus voltage is equal to 3*V _boost ; the eleventh switch _S11 and the twelfth switch _S12 are turned on, and output The voltage is -3*V _boost .

In the above scheme, the first working state and the fifth working state represent the state when the output is 0, the second working state and the sixth working state represent the state when the output is ±1, and the third working state. Together with the eighth working state representing the state when the output is ±2, the fourth working state and the seventh working state representing the state when the output is ±3, a power frequency AC cycle is formed.

An embodiment of the present invention further provides a seven-level inverter, including a DC power supply, and further comprising: the seven-level inverter topology structure based on a voltage doubling circuit according to any one of the above solutions, wherein the DC power supply has a topological structure. The positive and negative levels are respectively connected to the positive and negative poles of the bus voltage.

In the above solution, it also includes: a controller that generates a trigger pulse to control the on-off of each switch tube in the seven-level inverter topology structure, and realizes the seven-level inverter through the combination of on and off of different switch tubes. Different working states of the topology.

In the above solution, a plurality of the seven-level inverter topology structures are included, and the circuits of the multiple seven-level inverter topology structures are combined to form a multi-phase inverter.

Compared with the prior art, the beneficial effects of the present invention:

The invention realizes the seven-level inverter by effectively adjusting the bus bar by controlling the opening of the switch tube. Compared with the traditional seven-level inverter, this topology uses fewer switches, and the voltage gain can reach 30 times the steady-state gain, which is suitable for inverters with low voltage (photovoltaic, super capacitor, etc.) input; The voltage stress of some switching tubes is reduced, the switching loss of the switching tubes is reduced, and the system reliability is improved.

Description of drawings

1 is a schematic diagram of a topology structure of a seven-level inverter based on a voltage doubler circuit according to an embodiment of the present invention;

FIG. 2 is a control principle diagram of a topology structure of a seven-level inverter based on a voltage doubler circuit according to an embodiment of the present invention;

3 is an output waveform diagram of a full-bridge single-phase inverter main circuit in a seven-level inverter topology structure based on a voltage doubler circuit according to an embodiment of the present invention;

4 is a schematic diagram of a first working state of a seven-level inverter topology structure based on a voltage doubler circuit according to an embodiment of the present invention;

5 is a schematic diagram of a second working state of a seven-level inverter topology structure based on a voltage doubler circuit according to an embodiment of the present invention;

6 is a schematic diagram of a third working state of a seven-level inverter topology structure based on a voltage doubling circuit according to an embodiment of the present invention;

7 is a schematic diagram of a fourth working state of a seven-level inverter topology structure based on a voltage doubling circuit according to an embodiment of the present invention;

8 is a schematic diagram of a fifth working state of a seven-level inverter topology structure based on a voltage doubling circuit according to an embodiment of the present invention;

9 is a schematic diagram of a sixth working state of a seven-level inverter topology structure based on a voltage doubler circuit according to an embodiment of the present invention;

10 is a schematic diagram of a seventh working state of a seven-level inverter topology structure based on a voltage doubling circuit according to an embodiment of the present invention;

11 is a schematic diagram of an eighth working state of a seven-level inverter topology structure based on a voltage doubler circuit according to an embodiment of the present invention;

Figure 12 is a logic diagram of the PWM generation of the main switch;

Fig. 13 is the simulation waveform of each switch tube PWM signal of the logic circuit;

Figure 14 shows the simulation results.

Detailed ways

In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention.

An embodiment of the present invention provides a seven-level inverter topology structure based on a voltage doubling circuit, as shown in FIG. 1 , which includes a Boost boost main circuit, a full-bridge single-phase inverter main circuit, and an auxiliary circuit; the Boost The boost main circuit includes an inductor L ₁ , a diode D ₁ , and a first switch S ₁ , and the full-bridge single-phase inverter main circuit includes a tenth switch S ₁₀ , an eleventh switch S ₁₁ , and a twelfth switch The auxiliary circuit includes a _{second switch S 2 ,} a third switch S ₃ , a fourth switch S ₄ , a _{fifth switch S 5 ,} and a sixth switch S _6. The seventh switch S ₇ , the eighth switch S ₈ , the ninth switch S ₉ , the first capacitor C ₁ , the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ . The positive pole is connected to the bus bar sequentially through the inductor L ₁ , the diode D ₁ , the fifth switch tube S ₅ , the seventh switch tube S ₇ , the eighth switch tube S ₈ , the twelfth switch tube S ₁₂ , and the thirteenth switch tube S ₁₃ . The negative pole of the voltage, the first capacitor C ₁ is connected in parallel between the positive and negative poles of the bus voltage and one end is connected between the positive pole of the bus voltage and the inductor L ₁ , the series connected second switch tube S ₂ , the second capacitor _C2 is connected in parallel between the positive and negative poles of the bus voltage and _one end is connected between the diode D1 and the _fifth switch S5, the series connected _third capacitor C3 and the _fourth switch S4 are connected in parallel with the bus voltage Between the positive and negative poles and one end is connected between the _fifth switch tube S5 and the _seventh switch tube S7, the fourth capacitor _C4 and the ninth switch tube _S9 connected in series are connected in parallel between the positive and negative poles of the bus voltage. and one end is connected between the eighth switch tube _S8 and the _twelfth switch tube S12, the _tenth switch tube S10 and the _eleventh switch tube S11 connected in series are connected in parallel between the positive and negative poles of the bus voltage And one end is connected between the eighth switch tube _S8 and the twelfth switch tube _S12 ; the two ends of the _third switch tube S3 are respectively connected between the _second switch tube S2 and the _second capacitor C2, And between the _third capacitor C3 and the _fourth switch S4, one end of the sixth switch _S6 is connected between the _fifth switch S5 and the _seventh switch S7, and the other end is connected to the fourth Between the capacitor _C4 and the ninth switch _S9 ; the voltage output terminal is connected between the tenth switch _S10 and the _eleventh switch S11, and between the twelfth switch _S12 and the thirteenth switch S ₁₃ ; the common connection point of the diode D ₁ , the second switch tube S ₂ , and the fifth switch tube S ₅ is also directly connected to the common connection point of the eighth switch tube S ₈ and the fourth capacitor C ₄ through one path.

When the system is in steady state, the output voltage is determined by the modulation ratio Ma of the system. The output voltage Vab has seven operating states: 3V _{boost t} , 2V _boost , V _boost , 0, -3V _{boost t} , -2V _boost , -V _boost . The voltage V _boost is the output of the front-end Boost circuit. Where V_boost=V_in*1/(1-D), D is the duty cycle of the boost boost circuit; therefore, the maximum output voltage of the full-bridge inverter is 3*(1-D) times the input DC voltage, 1>D> 0.

As shown in Figure ₁ , the output voltage of the inverter can be directly determined by the duty cycle of the switch S1 in the Boost circuit. Assuming that the SPWM modulation ratio of the inverter is _Ma , the inverter output voltage V _out-max can be obtained by formula 1.

Therefore, when Ma is _a constant, the maximum value of the output voltage of the inverter can be directly achieved by adjusting the duty cycle of the Boost circuit. The system control method is shown in Figure 2.

The relationship between the switching state of the switch and the output voltage is shown in Table 1, in which the Boost boost circuit can work independently.

Table 1. Relationship between switch state and output voltage

As shown in Table 1: The seven-level inverter of this system is completed by alternate transformation of seven states, and the output waveform of the H-bridge (that is, the full-bridge single-phase inverter main circuit) is shown in Figure 3.

As shown in Figure 3: When the working state of the positive half-cycle switch tube is ABBA, the output voltage level of the H-bridge is +1, when the working state is BCCB, the output voltage level of the H-bridge is +2, and when the working state is CDCD, the output voltage of the H-bridge Level is +3. When the output voltage level in the negative half cycle is -1, -2, -3, the working states of the switch tubes are EFFE, FGGF and GHGH respectively. Its output can obtain a complete sinusoidal alternating current through the LC filter circuit.

The different level states of the present invention are mainly completed by switch tubes S ₂ -S ₉ and capacitors C ₂ , C ₃ and C ₄ ; the series-parallel structure of capacitors can be changed by changing the on-state of the switch tubes to realize the function of changing the bus voltage. Figure 4 shows the working principle of the circuit in each of the seven states. The first working state and the fifth working state represent the state when the output is 0, the second working state and the sixth working state represent the state when the output is ±1, the third working state and the eighth state The working state indicates the state when the output is ±2, the fourth working state and the seventh working state indicate the state when the output is ±3, which together form a power frequency AC cycle.

As shown in FIG. 4 , the first working state of the seven-level inverter topology structure based on the voltage doubling circuit: the _first switch S1 is turned on, and the bus voltage V _in stores energy in the inductor L1 _; The _tenth switch S10 and the twelfth switch _S12 are turned on, and the output voltage U _ab is 0; the energy of the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ remains unchanged;

As shown in FIG. 5, the second working state: the _first switch S1 is turned off, the bus voltage V _in and the inductor L1 simultaneously provide energy to the full _- bridge single-phase inverter main circuit; the _second switch S2 , the fourth switch S ₄ , the fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the ninth switch S ₉ are turned on; the second capacitor C ₂ and the third capacitor C _3. The voltage at both ends of the fourth capacitor _C4 in parallel is filled to V _boost , and the bus voltage is equal to V _boost ; the _tenth switch S10 and the thirteenth switch _S13 are turned on, and the output voltage is V _boost ;

As shown in FIG. 6 , the third working state: the third switch S ₃ , the fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the tenth switch S ₁₀ are turned on ; the second capacitor C ₂ and the third capacitor C ₃ are connected in series while the fourth capacitor C ₄ is disconnected, and the bus voltage is equal to 2*V _boost ; the _tenth switch S10 and the thirteenth switch _S13 are turned on , the output voltage is 2*V _boost ;

As shown in FIG. 7 , the fourth working state: the third switch S ₃ , the fifth switch S ₅ , and the sixth switch S ₆ are turned on; the second capacitor C ₂ and the third capacitor C ₃ The fourth capacitor _C4 is connected in series, and the bus voltage is equal to 3*V _boost ; the _tenth switch S10 and the thirteenth switch _S13 are turned on, and the output voltage is 3*V _boost .

As shown in FIG. 8 , the fifth working state: the _first switch S1 is turned on, and the bus voltage V _in stores energy in the inductor L1 _; the eleventh switch _S11 and the thirteenth switch S ₁₃ is turned on, and the output voltage U _ab is 0; the energy of the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ remains unchanged;

As shown in FIG. 9, the sixth working state: the _first switch S1 is turned off, the bus voltage V _in and the inductance L1 simultaneously provide energy to the full _- bridge single-phase inverter main circuit; the second switch S ₂ , the fourth switch S ₄ , the fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the ninth switch S ₉ are turned on. The voltages at both ends of the second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ are connected in parallel to be fully charged to V _boost , and the bus voltage is equal to V _boost at this time. The switches _S11 and _S12 are turned on, and the output voltage is -V _boost ;

As shown in FIG. 10 , the seventh working state: the third switch S ₃ , the fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the tenth switch S ₁₀ are turned on . The second capacitor C ₂ and the third capacitor C ₃ are connected in series while the fourth capacitor C ₄ is disconnected, and the bus voltage is equal to 2*V _boost ; the eleventh switch _S11 and the twelfth switch _S12 are turned on , the output voltage is -2*V _boost ;

As shown in FIG. 11 , the eighth working state: the third switch S ₃ , the fifth switch S ₅ , the seventh switch S ₇ , the eighth switch S ₈ , and the tenth switch S ₁₀ are turned on . The second capacitor C ₂ , the third capacitor C ₃ , and the fourth capacitor C ₄ are connected in series, and the bus voltage is equal to 3*V _boost ; the eleventh switch _S11 and the twelfth switch _S12 are turned on, and output The voltage is -3*V _boost .

In order to verify the feasibility of the system, the PSIM is used to build a main circuit simulation model to verify the present invention, and a reasonable logic analysis sequence is designed according to the above working states.

The high-frequency carrier signal is a triangular wave, and its frequency directly controls the chopping frequency of the switching tube. The high frequency chopped signal is the same square wave as the carrier signal with a 50% duty cycle. Figure 13 shows the simulation waveform of the PWM signal of each switch tube through the above logic circuit.

The main topology is shown in Figure 1, and its circuit simulation parameters are shown in Table 2.

Table 2 Circuit Simulation Parameters

Through the design circuit parameters shown in Table 2, the simulation results are shown in Figure 14. The output voltage of the H bridge is completed alternately by seven states, and the load voltage is smoothed by the LC filter circuit.

The voltages at the terminals of capacitors C2, C3 and C4 used for voltage doubling are less oscillated. In order to reduce the voltage oscillation of the capacitor terminal, the switching frequency can be appropriately increased, and at the same time, the switching frequency can be increased to reduce the capacitance and inductance value, and the size can be reduced to increase the power density of the system. The voltage stress of the switch tube is shown in Table 3.

Table 3 Voltage stress of switch tube

As shown in Table 3, the voltage stress of each switch tube is shown. Compared with the traditional multi-level inverter, the topology structure reduces the voltage stress of some switching tubes, so it can effectively reduce the switching loss, reduce the system loss and increase the stability of the system.

Embodiments of the present invention further provide a seven-level inverter, including a DC power supply, and further comprising: the seven-level inverter topology structure based on a voltage doubling circuit as described in the above solution, the positive voltage of the DC power supply is The flat and negative levels are respectively connected to the positive and negative poles of the bus voltage.

The seven-level inverter further includes: a controller that generates a trigger pulse to control the on-off of each switch tube in the seven-level inverter topology structure, and realizes the seven-level inverter through the combination of on and off of different switch tubes. Different working states of the level inversion topology.

Further, a plurality of the seven-level inverter topology structures are included, and the circuits of the multiple seven-level inverter topology structures are combined to form a multi-phase inverter.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (2)

1. A seven-level inverter topological structure based on a voltage doubling circuit is characterized by comprising a Boost mainThe circuit comprises a full-bridge single-phase inverter main circuit and an auxiliary circuit; the Boost main circuit comprises an inductor L₁Diode D₁A first switch tube S₁The full-bridge single-phase inverter main circuit comprises a tenth switching tube S₁₀The eleventh switch tube S₁₁The twelfth switch tube S₁₂Thirteenth switch tube S₁₃The auxiliary circuit comprises a second switch tube S₂A third switch tube S₃And a fourth switching tube S₄The fifth switch tube S₅The sixth switching tube S₆Seventh switching tube S₇The eighth switching tube S₈The ninth switch tube S₉A first capacitor C₁A second capacitor C₂A third capacitor C₃A fourth capacitor C₄The positive pole of the input voltage passes through an inductor L in sequence₁Diode D₁The fifth switch tube S₅Seventh switching tube S₇The eighth switching tube S₈The twelfth switch tube S₁₂Thirteenth switch tube S₁₃Connected to the negative pole of the input voltage, and the first capacitor C₁Connected in parallel between the positive and negative poles of the input voltage and having one end connected to the positive pole of the input voltage and the inductor L₁A second switch tube S₂A second capacitor C₂One end of the series circuit is connected to a diode D₁And a fifth switching tube S₅The other end of the switch is connected with the negative pole of the input voltage; third capacitor C₃And a fourth switching tube S₄One end of the series circuit is connected with the fifth switch tube S₅And a seventh switching tube S₇The other end of the switch is connected with the negative pole of the input voltage; fourth capacitor C₄The ninth switch tube S₉One end of the series circuit is connected to the eighth switching tube S₈And a twelfth switching tube S₁₂The other end of the switch is connected with the negative pole of the input voltage; tenth switching tube S₁₀The eleventh switch tube S₁₁One end of the series circuit is connected to the eighth switching tube S₈And a twelfth switching tube S₁₂The other end of the switch is connected with the negative pole of the input voltage; the third switch tube S₃Are respectively connected with a second switch tube S₂And a second capacitorC₂And a third capacitance C₃And a fourth switching tube S₄In the sixth switching tube S₆Is connected to a fifth switching tube S₅And a seventh switching tube S₇Another end is connected to a fourth capacitor C₄And a ninth switching tube S₉To (c) to (d); the voltage output end is connected with a tenth switch tube S₁₀And an eleventh switching tube S₁₁And a twelfth switching tube S₁₂And a thirteenth switching tube S₁₃To (c) to (d); the diode D₁A second switch tube S₂The fifth switch tube S₅The common junction is also directly connected with an eighth switching tube S₈A fourth capacitor C₄A common junction;

the first working state of the seven-level inverter topology based on the voltage doubling circuit is as follows: the first switch tube S₁On, input voltage V_inTo the inductance L₁Storing energy; tenth switching tube S₁₀And a twelfth switching tube S₁₂Conducting and outputting voltage U_abIs 0; the second capacitor C₂A third capacitor C₃A fourth capacitor C₄The energy remains unchanged;

the second working state: first switch tube S₁Off, input voltage V_inAnd an inductance L₁Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S₂And a fourth switching tube S₄The fifth switch tube S₅Seventh switching tube S₇The eighth switching tube S₈The ninth switch tube S₉Conducting; the second capacitor C₂A third capacitor C₃A fourth capacitor C₄Parallel connection, both ends of which are charged to V_boost(ii) a The tenth switching tube S₁₀And a thirteenth switching tube S₁₃Is conducted and has an output voltage of V_boost；

The third working state: the third switch tube S₃The fifth switch tube S₅Seventh switching tube S₇The eighth switching tube S₈Conducting; the second capacitor C₂A third capacitor C₃A fourth capacitor C connected in series₄Off, bus voltageEqual to 2V_boost(ii) a The tenth switching tube S₁₀And a thirteenth switching tube S₁₃On and output voltage of 2V_boost；

The fourth working state: the third switch tube S₃The sixth switching tube S₆Conducting; the second capacitor C₂A third capacitor C₃A fourth capacitor C₄Connected in series with an input voltage equal to 3 x V_boost(ii) a The tenth switching tube S₁₀And a thirteenth switching tube S₁₃Conducting and the output voltage is 3V_boost；

The fifth working state: the first switch tube S₁On, input voltage V_inTo the inductance L₁Storing energy; the eleventh switch tube S₁₁And a thirteenth switching tube S₁₃Conducting and outputting voltage U_abIs 0; the second capacitor C₂A third capacitor C₃A fourth capacitor C₄The energy remains unchanged;

the sixth working state: the first switch tube S₁Off, input voltage V_inAnd an inductance L₁Meanwhile, energy is provided for the full-bridge single-phase inverter main circuit; the second switch tube S₂And a fourth switching tube S₄The fifth switch tube S₅Seventh switching tube S₇The eighth switching tube S₈The ninth switch tube S₉Conducting; the second capacitor C₂A third capacitor C₃A fourth capacitor C₄Parallel connection, both ends of which are charged to V_boostWhen the bus voltage is equal to V_boost(ii) a Switch S₁₁And S₁₂Is conducted and has an output voltage of-V_boost；

The seventh working state: the third switch tube S₃The fifth switch tube S₅Seventh switching tube S₇The eighth switching tube S₈Conducting; the second capacitor C₂A third capacitor C₃A fourth capacitor C connected in series₄Disconnected and the bus voltage is equal to 2V_boost(ii) a The eleventh switch tube S₁₁And a twelfth switching tube S₁₂Is conducted and the output voltage is-2V_boost；

The eighth operating state: the third switch tube S₃The sixth switching tube S₆Conducting; the second capacitor C₂A third capacitor C₃A fourth capacitor C₄Connected in series with an input voltage equal to 3 x V_boost(ii) a The eleventh switch tube S₁₁And a twelfth switching tube S₁₂Is conducted and the output voltage is-3V_boost。

2. The seven-level inverter topology based on voltage doubling circuit according to claim 1, wherein the first and fifth operating states represent a state when the output is 0, the second and sixth operating states represent an output of ± V_boostThe time, third and eighth operating states represent an output of ± 2 × V_boostThe time, fourth and seventh operating states represent an output of ± 3 × V_boostThe time states, which together form a power frequency ac cycle.

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