CN114156382A - Quantum well structure, LED chip and manufacturing method - Google Patents

Quantum well structure, LED chip and manufacturing method Download PDF

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Publication number
CN114156382A
CN114156382A CN202111462290.8A CN202111462290A CN114156382A CN 114156382 A CN114156382 A CN 114156382A CN 202111462290 A CN202111462290 A CN 202111462290A CN 114156382 A CN114156382 A CN 114156382A
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layer
quantum well
well structure
substrate
layers
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聂虎臣
崔晓慧
霍丽艳
刘兆
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Jiangxi Qianzhao Photoelectric Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26—Materials of the light emitting region
    • H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
    • H01L33/32—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen
    • H01L33/325—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table containing nitrogen characterised by the doping materials

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Abstract

The invention provides a quantum well structure, an LED chip and a manufacturing method thereof, wherein the quantum well structure comprises a plurality of quantum well laminated layers, and the quantum well laminated layers comprise InyGa1‑yN layer, superlattice treatment layer including InN layer and In layer, and GaN layerxGa1‑xAnd N layers. Due to InN layer, and InxGa1‑xThe mobility of In the N layer is higher, and In of the quantum well structure can be effectively compensatedyGa1‑yInN vacancy decomposed by heating In the N layer, repairing InyGa1‑yLattice defects of the N layer while improving InyGa1‑ySegregation and enrichment phenomena of In the N layer enable the In component to be distributedUniform, provides a good and clear interface for the subsequent GaN growth, and reduces InyGa1‑yThe N layer and the GaN layer generate stress due to lattice mismatch, so that wavelength uniformity and internal quantum efficiency are improved.

Description

Quantum well structure, LED chip and manufacturing method
Technical Field
The invention relates to the technical field of LEDs (light emitting diodes), in particular to a quantum well structure, an LED chip and a manufacturing method.
Background
Light Emitting Diodes (LEDs) are a new type of semiconductor solid state light source, and their superior performance raises a new wave in the field of lighting. Especially, mini-LED has become a hot point of domestic and foreign scientific research at present because of smaller particles, finer display effect and higher brightness compared with the traditional LED.
With the technological progress and the improvement of the process level, the mini-LED also makes a great breakthrough in the aspects of luminous efficiency, epitaxial growth technology and the like, but compared with the traditional LED, the mini-LED still has some problems to be solved urgently, for example, the mini-LED has a particularly high requirement on the uniformity of the epitaxial wavelength, which is one of the important factors restricting the development of the mini-LED technology at present.
At present, the quantum well structure can be applied to a mini-LED to improve the wavelength uniformity and brightness of an epitaxial wafer. But due to the conventional multi-layer quantum well InyGa1-yIn superlattice structure of N layer and GaN layeryGa1-yThe InN thermal stability of the N layer is low, and InN vacancy which is decomposed by heat is easily caused, so that In is intensifiedyGa1-ySegregation and enrichment of In the N layer, which results In the multi-layer quantum wellyGa1-yThe stress between heterojunction materials in the superlattice structures of the N layer and the GaN layer is not uniform, so that the problems of poor wavelength uniformity, reduced internal quantum efficiency and the like are caused.
Disclosure of Invention
In view of the above, to solve the above problems, the present invention provides a quantum well structure, an LED chip and a manufacturing method, and the technical solution is as follows:
a quantum well structure, the quantum well structure comprising:
the quantum well lamination is sequentially stacked in a first direction;
any one of the quantum well stacks includes In sequentially stacked In the first directionyGa1-yN layer, superlattice treatment layer, anda GaN layer, wherein the value range of y is 0.16-0.2;
the first direction is perpendicular to the InyGa1-yN layer is In the plane, and consists of the InyGa1-yThe N layer points to the GaN layer;
the superlattice treatment layer comprises a plurality of crystal lattice lamination layers which are sequentially stacked in the first direction;
any one of the lattice stacks includes InN layers and In sequentially stacked In the first directionxGa1-xAnd N layers, wherein the value range of x is 0.16-0.2.
Preferably, in the quantum well structure described above, the superlattice treatment layer comprises 2 to 5 lattice stacks.
Preferably, in the quantum well structure, the InN layer has a thickness in a range of 0.1nm to 0.4 nm.
Preferably, In the quantum well structure described above, the InxGa1-xThe thickness of the N layer ranges from 0.1nm to 0.4 nm.
Preferably, In the quantum well structure described above, the InyGa1-yThe thickness of the N layer ranges from 1.5nm to 4 nm.
Preferably, in the quantum well structure, the thickness of the GaN layer is in a range of 10nm to 12 nm.
Preferably, in the above quantum well structure, the quantum well structure further includes:
a stress release layer;
the stress relieving layer comprises a plurality of shallow well layers which are arranged in a stacking mode in the first direction;
any one of the shallow well layers includes an InGaN layer and a GaN layer sequentially stacked in the first direction.
Preferably, in the quantum well structure, the stress relieving layer includes at least one of the shallow well layers.
An LED chip, the chip comprising:
a substrate;
a quantum well structure located on one side of the substrate;
the quantum well structure is the quantum well structure described in any one of the above;
the buffer layer, the U-shaped gallium nitride layer and the N-shaped semiconductor layer are positioned between the substrate and the quantum well structure and are sequentially stacked in the second direction;
wherein the second direction is perpendicular to the plane of the substrate and is directed to the quantum well structure by the substrate;
and the P-type gallium nitride layer is positioned on one side of the quantum well structure, which is far away from the substrate.
A manufacturing method of an LED chip is used for manufacturing the LED chip, and comprises the following steps:
providing the substrate;
sequentially forming a buffer layer, a U-shaped gallium nitride layer and an N-shaped semiconductor layer on the substrate along the second direction;
forming a quantum well structure on one side of the N-type semiconductor layer, which is far away from the substrate; the quantum well structure is the quantum well structure described in any one of the above;
and forming a P-type gallium nitride layer on one side of the quantum well structure, which is far away from the substrate.
Compared with the prior art, the invention has the following beneficial effects:
the invention provides a quantum well structure, which comprises a plurality of quantum well laminated layers, wherein the quantum well laminated layers comprise InyGa1-yN layer, superlattice treatment layer including InN layer and In layer, and GaN layerxGa1-xAnd N layers. Due to InN layer, and InxGa1-xThe mobility of In the N layer is higher, and the quantum well structure In can be effectively compensatedyGa1-yInN vacancy decomposed by heating In the N layer, repairing InyGa1-yLattice defects of the N layer while improving InyGa1-yThe segregation and enrichment phenomena of In the N layer enable the In components to be distributed uniformly, and a good-quality and clear interface is provided for subsequent GaN growth. After the In composition and the overall lattice quality are both improved, InyGa1-yN layers andstress generated by lattice mismatch of the GaN layer is correspondingly reduced, so that the separation degree of space wave functions of electrons and holes caused by quantum stark effect is reduced, and wavelength uniformity and internal quantum efficiency are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic partial structure diagram of a quantum well structure according to an embodiment of the present invention;
fig. 2 is a schematic partial structure diagram of a quantum well structure according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a quantum well structure according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an LED chip according to an embodiment of the present invention;
fig. 5 is a schematic flow chart of a method for manufacturing an LED chip according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Based on the description In the background, In the course of the invention creation of the present application, the inventors found that the conventional multilayer quantum well structure is directly formed of InyGa1-yThe N layer and the GaN layer are formed, and due to the difference of lattice constants of the two materials, a polarization field is generated, so that energy band bending and internal stress are causedMeanwhile, due to the poor thermal stability of the InN material, InN vacancies are easily generated in the quantum well in the temperature rising process from the quantum well to the quantum barrier, so that the internal stress distribution in the quantum well and the quantum barrier is uneven, the electron space wave function and the hole space wave function are separated, and the wavelength uniformity is easily deteriorated.
Based on these technical drawbacks, the present application provides a quantum well structure comprising:
the quantum well lamination is sequentially stacked in a first direction;
any one of the quantum well stacks includes In sequentially stacked In the first directionyGa1-yThe device comprises an N layer, a superlattice treatment layer and a GaN layer, wherein the value range of y is 0.16-0.2;
the first direction is perpendicular to the InyGa1-yN layer is In the plane, and consists of the InyGa1-yThe N layer points to the GaN layer;
the superlattice treatment layer comprises a plurality of crystal lattice lamination layers which are sequentially stacked in the first direction;
any one of the lattice stacks includes InN layers and In sequentially stacked In the first directionxGa1-xAnd N layers, wherein the value range of x is 0.16-0.2.
The more traditional multilayer quantum well structure of this application is InyGa1-yA superlattice treatment layer is added between the N layer and the GaN layer, and comprises an InN layer and InxGa1-xAnd N layers. Due to InN layer, and InxGa1-xThe mobility of In the N layer is higher, and the quantum well structure In can be effectively compensatedyGa1-yInN vacancy decomposed by heating In the N layer, repairing InyGa1-yLattice defects of the N layer while improving InyGa1-yThe segregation and enrichment phenomena of In the N layer can obviously reduce the wavelength standard deviation (Std) and the wavelength half-peak width (HW) of the device, thereby achieving the purpose of improving the wavelength uniformity, and simultaneously, the interface between the quantum well and the quantum barrier is repairedThe brightness is also improved by the complex improvement, which is a good improvement and complement to the bottleneck of wavelength uniformity encountered in the current mini-LED mass production.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
Referring to fig. 1, fig. 1 is a schematic partial structure diagram of a quantum well structure according to an embodiment of the present invention.
The quantum well structure includes:
the quantum well structure comprises a plurality of quantum well lamination layers H, wherein the quantum well lamination layers H are sequentially stacked in a first direction K.
Any one of the quantum well stacks H includes In sequentially stacked In the first direction KyGa1-y The N layer 11, the superlattice treatment layer N, and the GaN layer 14, wherein y has a value in a range of 0.16-0.2.
The first direction K is perpendicular to the InyGa1-yN layer 11 is In the plane, and consists of the InyGa1-yThe N layer 11 is directed towards the GaN layer 14.
The superlattice treatment layer N comprises a plurality of crystal lattice lamination layers M which are sequentially stacked in the first direction K.
Any of the lattice stacks M includes an InN layer 12 and In stacked In this order In the first direction KxGa1-xAnd the N layer 13, wherein the value range of x is 0.16-0.2.
In this embodiment, as shown in fig. 1, L represents the number of cycles of stacking the plurality of quantum well stacks H cyclically, for example, 10 cycles of quantum well stacks H, that is, 10 times of stacking quantum well stacks H in the first direction K, where L is 10.
In, InyGa1-yA superlattice treatment layer N is added between the N layer 11 and the GaN layer 14, and the mobility of In the superlattice treatment layer N is higher, so that In can be effectively filledyGa1-yInN vacancy occurring In the N layer 11, repair InyGa1-yLattice defect of N layer 11, improving InThe distribution uniformity of the components is improved, and In is improvedyGa1-y The N layer 11 lattice mass reduces the non-radiative recombination centers.
InyGa1-yThe N layer 11 is used as a light emitting layer, under the condition that In components and the overall lattice quality are improved, internal stress generated by lattice mismatch between heterojunctions can be smaller and more uniform, the overlapped area of an electron space wave function and a hole space wave function can be more, the radiation recombination ratio is improved, and the wavelength uniformity and the internal quantum efficiency can be improved.
In can be effectively improved due to the superlattice treatment layer NyGa1-ySegregation and enrichment phenomena of In the N layer 11 make the heterojunction interface clearer, the crystal quality of the GaN layer 14 can be improved, and the integral In can be improvedyGa1-y The N layer 11 also serves as a positive feedback protection, and the internal quantum efficiency is improved even at lower dislocation densities in the GaN layer 14.
Optionally, the value range of x is 0.16-0.2, for example, the value of x may be set to 0.17, 0.18, 0.19, or the like; the value of y ranges from 0.16 to 0.2, and for example, the value of y can be set to 0.16, 0.18, 0.19, and the like.
It should be noted that the values of x and y may be the same or different, and are not limited specifically.
Optionally, the superlattice treatment layer N comprises 2 to 5 lattice stacks M.
It should be noted that, as shown in fig. 1, Z represents the number of cycles of cyclically superimposing a plurality of lattice stacks M, and in this embodiment, 2 < Z < 5, for example, Z ═ 3 or Z ═ 4.
Optionally, the thickness of the InN layer 12 ranges from 0.1nm to 0.4nm, for example, the thickness of the InN layer 12 is set to 0.2nm, 0.25nm, 0.3nm, or the like.
The growth temperature of the InN layer 12 is set to 700 ℃ to 850 ℃, and for example, the growth temperature of the InN layer 12 is set to 770 ℃, 800 ℃, 840 ℃, or the like.
Optionally, the InxGa1-xThe thickness of the N layer 13 is In the range of 0.1nm to 0.4nm, for example, InxGa1-xThickness of N13 layerThe degree is set to 0.15nm, 0.2nm, 0.35nm, or the like.
In isxGa1-xThe growth temperature of the N layer 13 is 700 ℃ to 850 ℃, for example, InxGa1-xThe growth temperature of the N layer 13 is set to 720 ℃ or 770 ℃ or 840 ℃ or the like.
Optionally, the InyGa1-yThe thickness of the N layer 11 is In the range of 1.5nm to 4nm, for example, InyGa1-yThe thickness of the N layer 11 is set to 2.5nm, 3nm, 3.5nm, or the like.
In isyGa1-yThe growth temperature of the N layer 11 is 700 ℃ to 850 ℃, for example, InyGa1-yThe growth temperature of the N layer 11 is set to 750 ℃, 770 ℃, 820 ℃ or the like.
Optionally, the thickness of the GaN layer 14 ranges from 10nm to 12nm, for example, the thickness of the GaN layer 14 is set to 10nm, 11nm, 12nm, or the like.
The growth temperature of the GaN layer 14 is 800 to 950 ℃, and for example, the growth temperature of the GaN layer 14 is set to 820 ℃ or 880 ℃ or 920 ℃.
The growth temperature of the GaN layer 14 is lower than that of the InN layer 12 and InxGa1-xThe growth temperature of the N layer 13 is higher by 70-100 ℃.
Further, referring to fig. 2, fig. 2 is a schematic partial structure diagram of a quantum well structure according to an embodiment of the present invention.
Optionally, in another embodiment of the present application, the quantum well structure further includes:
and a stress release layer J.
The stress relieving layer J includes a plurality of shallow well layers E stacked in the first direction K.
Any of the shallow well layers E includes an InGaN layer 15 and a GaN layer 16 sequentially stacked in the first direction K.
Optionally, the stress release layer J includes at least one shallow well layer E.
As shown in fig. 2, F represents the number of cycles of cyclically superimposing the plurality of shallow well layers E. In this embodiment, since the stress relieving layer J includes at least one shallow well layer E, F > 1. For example, the shallow well layer E is cycled for 10 cycles, that is, the shallow well layer E is stacked 10 times in the first direction K, where F is 10.
Further, referring to fig. 3, fig. 3 is a schematic structural diagram of a quantum well structure according to an embodiment of the present invention.
It should be noted that the stress relieving layer J in this embodiment is located below the plurality of quantum well stacks H in the above embodiment in the first direction K, and they collectively constitute the quantum well structure described in this application as shown in fig. 3.
Optionally, based on the above embodiments of the present application, in another embodiment of the present application, an LED chip is further provided. Referring to fig. 4, fig. 4 is a schematic structural diagram of an LED chip according to an embodiment of the present invention.
The LED chip includes:
a substrate 17.
A quantum well structure X located on one side of the substrate 17.
The quantum well structure X is the quantum well structure described in the above embodiments.
And the buffer layer 18, the U-shaped gallium nitride layer 19 and the N-type semiconductor layer 20 are sequentially stacked in the second direction W and are positioned between the substrate 17 and the quantum well structure X.
Wherein the second direction W is perpendicular to the plane of the substrate 17 and is directed from the substrate 17 to the quantum well structure X.
And the P-type gallium nitride layer 21 is positioned on one side of the quantum well structure X, which is far away from the substrate 17.
In this embodiment, the material of the substrate 17 may be PSS sapphire, SiC, Si, and AlN-plated sapphire material.
It should be noted that, due to the large lattice mismatch and thermal expansion coefficient mismatch between the substrate 17 and the U-shaped gallium nitride layer 19, the dislocation density of the epitaxial layer of the U-shaped gallium nitride layer 19 is large, and the crystal quality is poor. Therefore, before growing the U-shaped gallium nitride layer 19, a thin buffer layer 18 needs to be grown on the substrate 17 to improve the crystal quality of the epitaxial layer of the U-shaped gallium nitride layer 19.
After growing the U-type gallium nitride layer 19 on the buffer layer 18, the N-type semiconductor layer 20 is grown as an electron injection layer; the quantum well structure X serves as a light emitting layer, and the P-type gallium nitride layer 21 is a quantum well structure X for injecting holes.
It should be noted that the quantum well structure X is the quantum well structure X shown in fig. 3 in the above embodiment, and the second direction W is parallel to and the same as the first direction K in the above embodiment.
Optionally, based on the foregoing embodiment, another embodiment of the present application further provides a method for manufacturing an LED chip, which is used for manufacturing the LED chip described in the foregoing embodiment. Referring to fig. 5, fig. 5 is a schematic flow chart illustrating a method for manufacturing an LED chip according to an embodiment of the present invention.
The manufacturing method comprises the following steps:
s101: as shown in fig. 4, one such substrate 17 is provided.
Optionally, in this step, a device MOCVD is adopted, trimethyl gallium TMGa and triethyl gallium TEGa are used as Ga sources, and ammonia NH is used3Is a source of N, H2、N2As carrier gas, the doping sources are respectively silane SiH4Trimethylaluminum TMAl and magnesium Dicyclopenta CP2Mg。
Further, a sapphire PSS substrate and a graphite plate were used as a carrier plate, and hydrogenation treatment was performed for 1min to remove surface impurities and the like.
S102: as shown in fig. 4, a buffer layer 18, a U-type gallium nitride layer 19, and an N-type semiconductor layer 20 are sequentially formed on the substrate 17 along the second direction W.
Optionally, in this step, TMGa and NH are introduced when the buffer layer 18 is grown on the substrate 173、H2、N2The growth temperature is in the range of 500 ℃ to 850 ℃, and the thickness of the buffer layer 18 in the direction perpendicular to the plane of the substrate 17 is in the range of 5nm to 50 nm. For example, the growth temperature may be 800 ℃ and the thickness may be 20 nm.
Further, in the second direction W, a U-shaped gallium nitride layer 19 is continuously grown on the side of the buffer layer 18 away from the substrate 17, and TMGa and NH are introduced3、H2、N2The thickness of the U-shaped gallium nitride layer 19 in the direction perpendicular to the plane of the substrate 17 was 2500nm, and the growth temperature was 1100 ℃.
Further, in the second direction W, an N-type gallium nitride layer 20 continues to grow on the side of the U-type gallium nitride layer 19 away from the substrate 17, and TMGa and SiH are introduced4、NH3、H2、N2The thickness of the N-type gallium nitride layer 20 in the direction perpendicular to the plane of the substrate 17 is 2000nm, the growth temperature is 1070 ℃, and the doping concentration of Si is 1E19/cm3。
S103: as shown in fig. 4, a quantum well structure X is formed on a side of the N-type semiconductor layer 20 facing away from the substrate 17.
Optionally, in this step, the quantum well structure X includes a stress relief layer J, as shown in fig. 3, and a quantum well stack H. The stress release layer J includes an InGaN layer 15, and a GaN layer 16; the quantum well stack H comprises InyGa1-y An N layer 11, a superlattice treatment layer N, and a GaN layer 14; the superlattice treatment layer N further includes an InN layer 12, and InxGa1-xAnd an N layer 13.
Further, when the stress release layer J grows on the side of the N-type semiconductor layer 20 departing from the substrate 17, TEGa, TMIn and SiH are introduced4、NH3、H2、N2Since the stress relaxation layer J includes the shallow well layer E of F periods, F periods need to be grown at the time of growth. For example, in the 1 st to 10 th periods, the low concentration InGaN layer 15 is grown in the second direction W, and the shallow well layer E in which the GaN layer 16 is stacked has a thickness of 140nm in a direction perpendicular to the plane of the substrate 17, a growth temperature of the shallow well in the shallow well layer E is 840 ℃, and a growth temperature of the barrier is 900 ℃.
Further, a quantum well stack H is grown, and since the quantum well stack H has L periods, In is grown first In any one period of growthyGa1-yN layer 11, e.g. In first grown In any of periods 11-20yGa1-yN layer, introducing TEGa, TMIn and NH3、N2In a direction perpendicular to the plane of the substrate 17yGa1-yThe thickness of the N layer is2.5nm, the growth temperature is 770 ℃, and y is about 0.18.
In the case of growing the 11 th to 20 th periods of quantum well stack H, In of the 11 th period is grown on the side of the stress relaxation layer J away from the substrate 17yGa1-yN layers, and then the growth of the other layers in quantum well stack H for 11-20 cycles.
Further, In any one period, the superlattice treatment layer N In the quantum well stack H is grown, since the superlattice treatment layer N is composed of Z periods of InN layers 12, and In the second direction WxGa1-xThe N layers 13 are stacked, and the period Z ranges from 2 to 5. For example, InyGa1-yGrowing an InN layer 12 on the side of the N layer, which is far away from the substrate, and introducing TMIn and NH3、N2The growth temperature is 770 ℃, the TMIn flow is 2000sccm, NH3The flow rate was 220L and the thickness of the InN layer 12 in the direction perpendicular to the plane of the substrate 17 was 0.2 nm. Then continuing to grow In on the InN layer 12 side facing away from the substratexGa1-x An N layer 13 into which TEGa, TMIn and NH are introduced3、N2The growth temperature is 770 ℃ and In is In a direction perpendicular to the plane of the substrate 17xGa1-xThe thickness of the N layer 13 is 0.2nm, where x is about 0.18. Repeated stacked growth of InN layer 12 and InxGa1-xN layers 13 are three times, and the period number Z is 3.
Further, In any one cycle, GaN layer 14 In quantum well stack H is grown, for example, InxGa1-xGrowing a GaN layer 14 on the side of the N layer 13 departing from the substrate, and introducing TEGa and SiH4、NH3、H2、N2The growth temperature was 880 ℃, the thickness of the GaN layer 14 in the direction perpendicular to the plane of the substrate 17 was 12nm, and the doping concentration of Si was 1X 1018cm-3。
S104: as shown in fig. 4, a P-type gallium nitride layer 21 is formed on the side of the quantum well structure X facing away from the substrate 17.
Optionally, in this step, TMGa, CP is introduced when the P-type gallium nitride layer 21 is grown on the side of the GaN layer 14 away from the substrate 172Mg，NH3、H2、N2The P-type gallium nitride layer 21 has a thickness of 200nm in a direction perpendicular to the plane of the substrate 17, a growth temperature of 950 ℃ and a Mg concentration of 2X 1019cm-3。
Further, after all the layered structures are grown, cooling annealing treatment is required to be performed, and the growth is finished. Then XRD test is carried out on the grown hierarchical structure, LED chips are manufactured, and photoelectric parameter test is carried out.
In this example, the half-width at half-maximum (HW) and standard deviation of wavelength (Std) of PL test wavelength are significantly reduced by correlation test compared to conventional structures, demonstrating significantly improved electron and hole spatial wave function analysis, InyGa1-yThe interfaces of the N layer 11, the superlattice treatment layer N and the GaN layer 14 are obviously layered, and the internal stress among heterojunctions is reduced. After the chip is manufactured, photoelectric parameter testing and LOP are improved, and the fact that the quality of the multilayer quantum well structure is improved and the internal quantum efficiency is improved is proved.
It should be noted that the embodiment of the above-mentioned manufacturing method is defined as embodiment one.
Compared with the data in the first embodiment, the inventor partially changes the thickness and doping concentration of the quantum well structure layer as other embodiments of the present application, and analyzes the LED chip manufactured according to the data of the embodiments, so as to obtain different conclusions. The following is a description of various embodiments.
Alternatively, in the second embodiment, based on the data in the first embodiment, the inventors changed the thickness of the InN layer 12 in the superlattice treatment layer N so that the thickness of the InN layer 12 becomes 0.3nm in the direction perpendicular to the plane of the substrate 17. At this time, compared to the first embodiment, since the InN layer 12 in the superlattice treatment layer N is thicker, the PL test shows that the standard deviation of the wavelength (Std) is slightly reduced, but the luminance is slightly decreased, so that it can be known that the proportional relationship between the wavelength uniformity and the luminance can be controlled and adjusted according to specific situations in the LED chip manufacturing process.
Optionally, In the third embodiment, based on the data In the first embodiment, the inventors changed In the superlattice treatment layer NxGa1-xThickness of N layer 13, InxGa1-xThe thickness of the N layer 13 becomes 3nm in a direction perpendicular to the plane of the substrate 17. At this time, In is In contrast to the first embodimentxGa1-x The N layer 13 was thick, and PL test showed that the wavelength half-width (HW) and the wavelength standard deviation (Std) were slightly large, but the luminance was high, and it was found that the luminance was improved when the wavelength uniformity was acceptable in the LED chip production process.
Optionally, in a fourth embodiment, based on the data in the first embodiment, the inventors changed the doping concentration of GaN layer 14 in quantum well stack H such that the doping concentration of Si in GaN layer 14 becomes 8 × 1017cm-3. At this time, compared to the first embodiment, due to the doping of the GaN layer 14 is reduced, the IR value shown by the electrical test parameters is reduced, and the ESD performance is slightly improved, so that the IR and ESD yield can be controlled according to specific conditions during the LED chip manufacturing process, and the electrical performance can be improved.
The inventor only changes the above parameters, but does not limit the data of the parameters with scope in the present application, and only needs to make corresponding changes as required.
The quantum well structure, the LED chip and the manufacturing method provided by the present invention are described in detail above, and the principle and the implementation of the present invention are explained in detail herein by applying specific examples, and the description of the above examples is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
It should be noted that, in the present specification, the embodiments are all described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include or include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A quantum well structure, comprising:
the quantum well lamination is sequentially stacked in a first direction;
any one of the quantum well stacks includes In sequentially stacked In the first directionyGa1-yThe device comprises an N layer, a superlattice treatment layer and a GaN layer, wherein the value range of y is 0.16-0.2;
the first direction is perpendicular to the InyGa1-yN layer is In the plane, and consists of the InyGa1-yThe N layer points to the GaN layer;
the superlattice treatment layer comprises a plurality of crystal lattice lamination layers which are sequentially stacked in the first direction;
any one of the lattice stacks includes InN layers and In sequentially stacked In the first directionxGa1-xAnd N layers, wherein the value range of x is 0.16-0.2.
2. The quantum well structure of claim 1, wherein the superlattice treatment layer comprises 2-5 lattice stacks.
3. The quantum well structure of claim 1, wherein the InN layer has a thickness in a range of 0.1nm to 0.4 nm.
4. The quantum well structure of claim 1, wherein the InxGa1-xThe thickness of the N layer ranges from 0.1nm to 0.4 nm.
5. The quantum well structure of claim 1, wherein the InyGa1-yThe thickness of the N layer ranges from 1.5nm to 4 nm.
6. The quantum well structure of claim 1, wherein the GaN layer has a thickness in a range of 10nm to 12 nm.
7. The quantum well structure of claim 1, further comprising:
a stress release layer;
the stress relieving layer comprises a plurality of shallow well layers which are arranged in a stacking mode in the first direction;
any one of the shallow well layers includes an InGaN layer and a GaN layer sequentially stacked in the first direction.
8. The quantum well structure of claim 7, wherein the stress relief layer comprises at least one of the shallow well layers.
9. An LED chip, wherein said chip comprises:
a substrate;
a quantum well structure located on one side of the substrate;
the quantum well structure is the quantum well structure of any one of claims 1-8;
the buffer layer, the U-shaped gallium nitride layer and the N-shaped semiconductor layer are positioned between the substrate and the quantum well structure and are sequentially stacked in the second direction;
wherein the second direction is perpendicular to the plane of the substrate and is directed to the quantum well structure by the substrate;
and the P-type gallium nitride layer is positioned on one side of the quantum well structure, which is far away from the substrate.
10. A method for manufacturing an LED chip according to claim 9, the method comprising:
providing the substrate;
sequentially forming a buffer layer, a U-shaped gallium nitride layer and an N-shaped semiconductor layer on the substrate along the second direction;
forming a quantum well structure on one side of the N-type semiconductor layer, which is far away from the substrate; the quantum well structure is the quantum well structure of any one of claims 1-8;
and forming a P-type gallium nitride layer on one side of the quantum well structure, which is far away from the substrate.
CN202111462290.8A 2021-12-02 2021-12-02 Quantum well structure, LED chip and manufacturing method Pending CN114156382A (en)

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