CN114154452A - Layout and wiring method, device and equipment and readable storage medium - Google Patents
Layout and wiring method, device and equipment and readable storage medium Download PDFInfo
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- CN114154452A CN114154452A CN202111274522.7A CN202111274522A CN114154452A CN 114154452 A CN114154452 A CN 114154452A CN 202111274522 A CN202111274522 A CN 202111274522A CN 114154452 A CN114154452 A CN 114154452A
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- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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Abstract
The application discloses a method, a device and equipment for layout and wiring and a readable storage medium. The functional module aims at the matching of data processing logic and the star topology structure, can utilize the constraint modes with different constraint capacities to constrain each submodule in the functional module to carry out layout and wiring according to the star topology structure, obtain each layout and wiring result, then select the layout and wiring result meeting the requirement of the preset index from each layout and wiring result, and the layout and wiring scheme can be used as the layout and wiring scheme of the functional module, simplify the layout and wiring in the module, reduce the probability of occurrence of winding congestion, short circuit, time delay, functional errors and other problems, save circuit resources, chip power consumption and chip area, and also select the layout and wiring scheme meeting the requirement of the preset index, thereby improving the performance, manufacturability and time sequence convergence effect of the chip. Accordingly, the layout and wiring device, the equipment and the readable storage medium provided by the application also have the technical effects.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a readable storage medium for layout and routing.
Background
At present, the wiring mode of a functional module with complex data interaction logic generally has the following problems: the winding congestion in the module is serious, the problems of short circuit, time delay and the like are easy to occur, and the line resources are short. And thus easily causes a functional error, resulting in an increase in chip power consumption. If EDA tools are used to solve the routing problem, a certain chip area is sacrificed.
Therefore, how to simplify the layout and routing of functional modules with complex data interaction logic is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present application is to provide a method, an apparatus, a device and a readable storage medium for laying out and routing to simplify laying out and routing of a functional module with complex data interaction logic. The specific scheme is as follows:
in a first aspect, the present application provides a method for laying out and routing, including:
determining data processing logic among all sub-modules in any functional module in the chip;
if the data processing logic is matched with the star topology structure, utilizing constraint modes with different constraint capacities to constrain each submodule in the functional module to carry out layout and wiring according to the star topology structure, and obtaining layout and wiring results corresponding to each constraint mode;
and selecting the layout and wiring result meeting the preset index requirement from all the layout and wiring results to serve as the layout and wiring scheme of the functional module.
Preferably, the constraining each sub-module in the functional module by using the constraint modes with different constraint capabilities to perform layout and wiring according to the star topology structure to obtain the layout and wiring results corresponding to each constraint mode respectively includes:
determining a target sub-module which needs to be arranged at the central position of the star topology structure and other sub-modules which need to be arranged around the central position in each sub-module of the functional module according to the data processing logic;
and based on each constraint mode, constraining the target sub-module at the central position, constraining the other sub-modules around the central position, and wiring among the sub-modules to obtain a layout and wiring result corresponding to each constraint mode.
Preferably, before constraining the target sub-module to the central position and constraining the other sub-modules to the periphery of the central position, the method further includes:
and distributing layout space with corresponding size for each sub-module in the functional module according to the number of units included in each sub-module in the functional module.
Preferably, the constraint modes with different constraint capacities are as follows: soft bound, hard bound and/or exclude bound in an EDA tool.
Preferably, the selecting, as the layout and routing scheme of the functional module, a layout and routing result meeting a preset specification requirement from the respective layout and routing results includes:
respectively testing the time sequence information and/or the wiring congestion degree of each layout and wiring result;
and if the time sequence information and/or the wiring congestion degree of any one layout and wiring result meet the preset index requirement, taking the layout and wiring result as the layout and wiring scheme of the functional module.
Preferably, the method further comprises the following steps:
and if a plurality of layout and wiring results meeting the preset index requirements exist, selecting the layout and wiring result with the optimal timing information and/or wiring congestion degree from the plurality of layout and wiring results meeting the preset index requirements as the layout and wiring scheme of the functional module.
Preferably, after the selecting the layout and routing result meeting the preset specification requirement from the layout and routing results as the layout and routing scheme of the functional module, the method further includes:
and visually displaying the layout and wiring scheme by using an EDA tool.
In a second aspect, the present application provides a place and route apparatus, including:
the determining module is used for determining data processing logic among all sub-modules in any functional module in the chip;
the layout and wiring module is used for constraining each submodule in the functional module to carry out layout and wiring according to the star topology structure by utilizing constraint modes with different constraint capacities if the data processing logic is matched with the star topology structure, and obtaining layout and wiring results corresponding to each constraint mode;
and the selection module is used for selecting the layout and wiring result meeting the preset index requirement from all the layout and wiring results to serve as the layout and wiring scheme of the functional module.
In a third aspect, the present application provides an electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the method of placing and routing disclosed above.
In a fourth aspect, the present application provides a readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the method for placing and routing disclosed above.
According to the scheme, the layout and wiring method comprises the following steps: determining data processing logic among all sub-modules in any functional module in the chip; if the data processing logic is matched with the star topology structure, utilizing constraint modes with different constraint capacities to constrain each submodule in the functional module to carry out layout and wiring according to the star topology structure, and obtaining layout and wiring results corresponding to each constraint mode; and selecting the layout and wiring result meeting the preset index requirement from all the layout and wiring results to serve as the layout and wiring scheme of the functional module.
It can be seen that, for the functional module with the data processing logic matched with the star topology structure, the method can utilize constraint modes with different constraint capacities to constrain each submodule in the functional module to perform layout and wiring according to the star topology structure, obtain layout and wiring results corresponding to each constraint mode respectively, and then select a layout and wiring result meeting the requirement of a preset index from each layout and wiring result to serve as a layout and wiring scheme of the functional module. Because the star topology structure is matched with the data processing logic between the submodules in the functional module, the wiring layout can reduce the winding, solve the problem of winding congestion inside the module, reduce the probability of short circuit, time delay, functional error and other problems, save the line resources, the chip power consumption and the chip area, and improve the performance, the manufacturability and the time sequence convergence effect of the chip.
Accordingly, the layout and wiring device, the equipment and the readable storage medium provided by the application also have the technical effects.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a flow chart of a method for laying out and routing disclosed herein;
FIG. 2 is a schematic diagram of a layout and routing result disclosed in the present application;
FIG. 3 is a schematic diagram of another layout and routing result disclosed in the present application;
FIG. 4 is a schematic diagram of a device for laying out and routing wires according to the present disclosure;
fig. 5 is a schematic diagram of an electronic device disclosed in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In order to more clearly describe the present application, the technical background of the present application will be described as follows.
The present application optimizes for chip design layout. The physical implementation of a chip design is often referred to simply as Place-and-Route (P & R). After the layout and the wiring, the steps of timing convergence, power consumption analysis, manufacturability analysis and the like are continuously carried out on the chip, and finally the comprehensive netlist can be converted into a file format for production and manufacture. The method predicts the working frequency of the chip under various conditions by means of static time sequence analysis and the like, achieves path optimization by means of a constraint and optimization engine, and finally realizes the improvement of dominant frequency so that the chip can work under the required frequency. The power consumption analysis result shows the power consumption of the chip, the voltage drop inside the chip and the distribution of current, and reflects the working stability of the chip.
Of course, the power consumption, voltage drop, electromigration and other parameters of the chip are controlled within a certain range, and the chip with manufacturability can be designed, so that the positive effects of improving the yield, reducing the production cost and improving the product profit are achieved.
In the physical design of the chip, the layout planning and layout play an important role in the chip design, and whether the layout planning and layout is reasonable directly relates to timing convergence, smooth wiring, stable power supply and good product rate. In an overall chip design, it typically takes one third of the total physical implementation from floorplanning to completion of the layout. The quality of the floorplan and layout directly determines the quality of the chip.
Data interaction in individual modules (such as switch modules of server chips) in the chips is complex, data flow needs to shuttle back and forth due to functions, and winding is inevitable in layout and wiring. As shown in FIG. 2, A1-A8 are scattered in various places in the module, and the windings are shuttled around along with the positions of A1-A8, which inevitably occupies a large amount of winding resources, causes the winding resources to be tense, and causes a large number of short circuits to appear.
Area is sacrificed if EDA tools are relied upon to handle routing congestion issues. If the occupied area of the module in the chip is increased, time violation and power consumption are increased, and the risk and iteration time which are difficult to estimate are brought to timing convergence and manufacturability.
As can be seen, the wiring of functional modules with complex data interaction logic generally has the following problems: the winding congestion in the module is serious, the problems of short circuit, time delay and the like are easy to occur, and the line resources are short. And thus easily causes a functional error, resulting in an increase in chip power consumption. If EDA tools are used to solve the routing problem, a certain chip area is sacrificed. Therefore, the layout and wiring scheme is provided, the layout and wiring of the functional module with complex data interaction logic can be simplified, the probability of winding congestion, short circuit, time delay, functional error and other problems is reduced, line resources and chip power consumption are saved, and the layout and wiring scheme meeting the requirement of the preset index can be selected, so that the performance, manufacturability and time sequence convergence effect of the chip can be improved.
Referring to fig. 1, an embodiment of the present application discloses a method for laying out and routing, including:
s101, determining data processing logic among all sub-modules in any functional module in the chip.
In this embodiment, the data processing logic between the sub-modules in any functional module can be combed by a technician based on the design logic of the functional module.
Suppose that a functional module includes 9 sub-modules, a1-A8 and C, and the data processing logic between these sub-modules is: a1 sends data to C, and after C receives and processes it, returns the processed result to A1-A8. Accordingly, A2 will also send data to C, which will return the results to A1-A8 after having processed the data sent by A2. Similarly, the logic described above exists between A3-A8 and C, respectively.
If the layout wiring is performed for the functional modules, there may be a layout wiring scheme as shown in fig. 2, where fig. 2 only illustrates the wires from a1-A8 to C, and in the case where the wires can only transmit data in one direction, the wires from C to a1-A8, respectively, are also required. As shown in fig. 2, the layout of the solution is complex, the number of windings is large, and more chip space is required.
S102, if the data processing logic is matched with the star topology structure, the sub-modules in the function module are constrained by constraint modes with different constraint capacities to carry out layout and wiring according to the star topology structure, and layout and wiring results corresponding to the constraint modes are obtained.
Taking the functional module shown in fig. 2 as an example, if a1-A8 in the module all have interaction logic with C, then the data processing logic can be considered to match the star topology. Namely: c can be taken as the center point, and A1-A8 surround C. Accordingly, the method provided in this embodiment re-lays the flat cables of the functional module shown in fig. 2, so as to obtain the result of layout and routing as shown in fig. 3.
Comparing fig. 2 and fig. 3, it can be seen that the wiring of fig. 3 is simpler, the lines between a1 and C, the lines between a2 and C in fig. 3 do not intersect, and the other lines do so, which not only saves the line resources, but also solves the winding problem.
If there are a plurality of functional modules as shown in fig. 3 and the data processing logic between these functional modules also matches the star topology, these functional modules may also be laid out and wired in the star topology.
It should be noted that fig. 2 and 3 only illustrate the positions and connecting lines of different sub-modules, but in practice, the units constituting a sub-module are not all arranged inside the sub-module, and may be dispersed near the edges of the sub-module. Whether the units making up a sub-module are located within the sub-module or dispersed adjacent to the edges of the sub-module depends on the constraining capabilities of the constraining means. Generally, a more constraining manner will confine the cells as much as possible within the sub-module, while a less constraining manner will allow the cells to be distributed at the sub-module edges. Wherein the unit is: standard library cell (standard cell).
The relationship between the strength of the constraint ability and the wiring complexity of the wiring layout result is not suitable for estimation and determination, so that the sub-modules in the same functional module can be subjected to wiring layout by using constraint modes with different constraint abilities, and then the obtained wiring layout results are compared, so that which constraint mode is better can be known definitely.
In one embodiment, the constraint modes with different constraint capabilities are: soft bound, hard bound and/or exclude bound in an EDA tool. Of course, other means of constraint may be used.
Among them, soft bound has the weakest constraint ability, bound has the weaker constraint ability, hard bound has the stronger constraint ability, and excluded bound has the strongest constraint ability.
The soft bound is also called soft guide, and it is only used as a guide to place a module (e.g. the sub-module C in fig. 3) or a cell (standard library unit) without setting a fixed position, and if a time violation or other problems occur, the module or the cell can be placed according to its own requirements, which is one of the least strict constraint requirements. The cell can enter or exit according to the time violation and other requirements. The definition mode of the clock is similar to a virtual clock, pin (interface of cell and outside world)/port (interface of module and outside world) does not need to be specified, coordinates are not needed, and the coordinates can be given.
The bound is also called guide, the constraint capability of the bound is more strict than that of the soft bound, the bound requires to specify coordinates to place a cell or a module on the basis of the soft bound, and the bound still only plays a role in guiding the placement of the cell and the module and does not make a mandatory requirement. Therefore, the cell can be in and out, the designated cell can be placed outside the module, the cell which is not designated can be placed inside the module, and only fixed coordinates need to be designated.
hard bound, also called region, has a stricter constraint ability than bound, and not only plays a role of guiding module or cell placement, but also must place cells or modules according to artificial required constraints, at which time the cells can go in and go out, the designated cells can not be placed outside the modules, and the unassigned cells can be placed inside the modules.
The exception bound is also called as the lancet, the constraint capability of the exception bound is strictest, the cell or the module must be placed strictly according to the artificial constraint, and the constraint condition of the kind is the same as the region and must be met, so that the exception bound does not only play a guiding role. The cell is not accessible and not accessible, the designated cell cannot be placed outside the module, and the cell that is not designated cannot be placed inside the module.
Through experimental comparison, it is finally found that the best layout and wiring result (i.e., the result shown in fig. 3) corresponding to the excclude bound with the strongest constraint capability is obtained, and it can be ensured that data routing between the sub-modules is clear.
S103, selecting the layout and wiring result meeting the preset index requirement from the layout and wiring results to serve as the layout and wiring scheme of the functional module.
In this embodiment, constraint modes with different constraint capabilities are used to constrain each sub-module in the same functional module to perform layout and wiring according to the star topology structure, so as to obtain layout and wiring results corresponding to each constraint mode, and thus it can be known which constraint mode is combined with the star topology structure, and the obtained layout and wiring effect is the best.
Of course, there may be more than one layout and routing result obtained in the present embodiment that meets the predetermined specification. Namely: the multiple layout and wiring results have practicability and feasibility, and then one of the results can be selected to be the best effect or one of the results can be selected at random. Wherein the predetermined index requirement may be set based on timing closure effect and/or routing congestion degree.
In a specific embodiment, after selecting a layout and routing result meeting a preset specification from the layout and routing results as a layout and routing scheme for the functional module, the method further includes: and visually displaying the layout and wiring scheme by using an EDA tool. Of course, the layout and routing results corresponding to each constraint mode can also be visually displayed by an EDA tool. Such as: the placement and routing within the functional module is highlighted in the EDA tool.
In this embodiment, for the functional module in which the data processing logic is matched with the star topology, constraint modes with different constraint capabilities may be utilized to constrain each sub-module in the functional module to perform layout and wiring according to the star topology, so as to obtain layout and wiring results corresponding to each constraint mode, and then a layout and wiring result meeting the requirement of a preset index is selected from each layout and wiring result to serve as a layout and wiring scheme of the functional module.
Therefore, if the star topology structure is matched with the data processing logic between the submodules in the functional module, the inside of the module is laid out and wired according to the star topology structure, so that the winding can be reduced, the problem of winding congestion inside the module is solved, the probability of short circuit, time delay, functional error and other problems is reduced, the line resources, the chip power consumption and the chip area are saved, and the performance, the manufacturability and the time sequence convergence effect of the chip can be improved.
Based on the foregoing embodiment, it should be noted that, in a specific implementation, the constraining each sub-module in the functional module by using constraint manners with different constraint capabilities performs layout and routing according to a star topology structure to obtain layout and routing results corresponding to each constraint manner, including: determining a target sub-module which needs to be arranged at the central position of the star topology structure and other sub-modules which need to be arranged around the central position in each sub-module in the functional module according to the data processing logic; based on each constraint mode, the target sub-module is constrained at the central position, other sub-modules are constrained around the central position, and wiring is carried out among the sub-modules, so that the layout and wiring result corresponding to each constraint mode is obtained.
Wherein, constraining the target sub-module at the central position and constraining other sub-modules around the central position, further comprises: and distributing layout space with corresponding size for each sub-module in the functional module according to the number of units included in each sub-module in the functional module.
Referring to FIG. 3, if there are more and fewer cells in A1-A8, then a larger area may be allocated to more cells and a smaller area may be allocated to less cells. Namely: when other sub-modules are constrained around the central position, the area around the target sub-module can be equally divided, and the sub-modules can also be divided one by one according to the number of units included in each sub-module. The two modes can fix A1-A8l in a specific area, and the arrangement mode can not cause the intersection of data streams any more, thereby fundamentally solving the problem of short circuit.
Of course, the ratio of the area occupied by C in the center of fig. 3 in the whole module can be adjusted according to the number of units in C.
It should be noted that the area that each functional module can occupy in the chip is limited. The functional module has the advantages that each submodule in the functional module is limited to be in a star-shaped topological structure, certain dependency is provided for the overall shape of the module, and the result is better under the condition that the overall shape of the module is rectangular. And meanwhile, the shape of other modules in the chip is limited.
In a specific embodiment, the selecting, as the placement and routing scheme for the functional module, a placement and routing result meeting a preset specification requirement from among the various placement and routing results includes: respectively testing the time sequence information and/or the wiring congestion degree of each layout and wiring result; and if the time sequence information and/or the wiring congestion degree of any one layout and wiring result meet the preset index requirement, taking the layout and wiring result as a layout and wiring scheme of the functional module.
And if a plurality of layout and wiring results meeting the preset index requirements exist, selecting the layout and wiring result with optimal timing information and/or wiring congestion degree from the plurality of layout and wiring results meeting the preset index requirements as the layout and wiring scheme of the functional module.
In the following, a description is given of a layout and routing apparatus provided in an embodiment of the present application, and a layout and routing apparatus described below and a layout and routing method described above may be referred to each other.
Referring to fig. 4, an embodiment of the present application discloses a place and route apparatus, including:
a determining module 401, configured to determine data processing logic between sub-modules in any functional module in a chip;
a layout and wiring module 402, configured to, if the data processing logic is matched with the star topology structure, constrain each sub-module in the functional module by using constraint manners with different constraint capabilities to perform layout and wiring according to the star topology structure, and obtain a layout and wiring result corresponding to each constraint manner;
a selecting module 403, configured to select, from the layout and routing results, a layout and routing result meeting the requirement of the preset index as a layout and routing scheme of the functional module.
In one embodiment, the place and route module includes:
the determining unit is used for determining a target sub-module which needs to be arranged at the central position of the star topology structure and other sub-modules which need to be arranged around the central position in each sub-module in the functional module according to the data processing logic;
and the constraint unit is used for constraining the target sub-module at the central position, constraining other sub-modules around the central position and wiring among the sub-modules based on each constraint mode to obtain a layout and wiring result corresponding to each constraint mode.
In one embodiment, the place and route module further comprises:
and the distribution unit is used for distributing layout space with corresponding size for each sub-module in the functional module according to the number of units included in each sub-module in the functional module.
In one embodiment, the constraint modes with different constraint capabilities are: soft bound, hard bound and/or exclude bound in an EDA tool.
In one embodiment, the selection module comprises:
the test unit is used for respectively testing the time sequence information and/or the wiring congestion degree of each layout and wiring result;
and the selection unit is used for taking the layout and routing result as the layout and routing scheme of the functional module if the time sequence information and/or the routing congestion degree of any layout and routing result meet the preset index requirement.
In one embodiment, the selection unit is further configured to:
and if a plurality of layout and wiring results meeting the preset index requirements exist, selecting the layout and wiring result with optimal timing information and/or wiring congestion degree from the plurality of layout and wiring results meeting the preset index requirements as the layout and wiring scheme of the functional module.
In a specific embodiment, the method further comprises the following steps:
and the display module is used for visually displaying the layout and wiring scheme by utilizing the EDA tool.
For more specific working processes of each module and sub-module in this embodiment, reference may be made to corresponding contents disclosed in the foregoing embodiments, and details are not repeated here.
Therefore, the embodiment provides a layout and wiring device, which can simplify the layout and wiring inside a module, reduce the probability of occurrence of winding congestion, short circuit, time delay, functional error and other problems, save line resources, chip power consumption and chip area, and select a layout and wiring scheme meeting the requirements of preset indexes, thereby improving the performance, manufacturability and timing convergence effect of a chip.
In the following, an electronic device provided by an embodiment of the present application is introduced, and a layout and routing method and an apparatus described above may be referred to each other.
Referring to fig. 5, an embodiment of the present application discloses an electronic device, including:
a memory 501 for storing a computer program;
a processor 502 for executing the computer program to implement the method disclosed in any of the embodiments above.
A readable storage medium provided by the embodiments of the present application is described below, and a readable storage medium described below and a method, an apparatus, and a device for laying out and routing described above may be referred to each other.
A readable storage medium for storing a computer program, wherein the computer program when executed by a processor implements the method for placing and routing disclosed in the foregoing embodiments. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, which are not described herein again.
References in this application to "first," "second," "third," "fourth," etc., if any, are intended to distinguish between similar elements and not necessarily to describe a particular order or sequence. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion, e.g., a process, method, or apparatus that comprises a list of steps or sub-modules is not necessarily limited to those steps or sub-modules explicitly listed, but may include other steps or sub-modules not explicitly listed or inherent to such process, method, or apparatus.
It should be noted that the descriptions in this application referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments may be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present application.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of readable storage medium known in the art.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. A method of placing and routing, comprising:
determining data processing logic among all sub-modules in any functional module in the chip;
if the data processing logic is matched with the star topology structure, utilizing constraint modes with different constraint capacities to constrain each submodule in the functional module to carry out layout and wiring according to the star topology structure, and obtaining layout and wiring results corresponding to each constraint mode;
and selecting the layout and wiring result meeting the preset index requirement from all the layout and wiring results to serve as the layout and wiring scheme of the functional module.
2. The method according to claim 1, wherein the constraining of each sub-module in the functional module by using the constraining manners with different constraining capabilities performs layout and routing according to the star topology structure to obtain the layout and routing results corresponding to each constraining manner respectively comprises:
determining a target sub-module which needs to be arranged at the central position of the star topology structure and other sub-modules which need to be arranged around the central position in each sub-module of the functional module according to the data processing logic;
and based on each constraint mode, constraining the target sub-module at the central position, constraining the other sub-modules around the central position, and wiring among the sub-modules to obtain a layout and wiring result corresponding to each constraint mode.
3. The method of claim 2, wherein constraining the target sub-module to the center position and the other sub-modules to the periphery of the center position further comprises:
and distributing layout space with corresponding size for each sub-module in the functional module according to the number of units included in each sub-module in the functional module.
4. The method of claim 1, wherein the constraint modes with different constraint capabilities are: soft bound, hard bound and/or exclude bound in an EDA tool.
5. The method according to any one of claims 1 to 4, wherein the selecting, as the placement and routing scheme for the functional module, the placement and routing result meeting the requirement of a preset index from the respective placement and routing results includes:
respectively testing the time sequence information and/or the wiring congestion degree of each layout and wiring result;
and if the time sequence information and/or the wiring congestion degree of any one layout and wiring result meet the preset index requirement, taking the layout and wiring result as the layout and wiring scheme of the functional module.
6. The method of claim 5, further comprising:
and if a plurality of layout and wiring results meeting the preset index requirements exist, selecting the layout and wiring result with the optimal timing information and/or wiring congestion degree from the plurality of layout and wiring results meeting the preset index requirements as the layout and wiring scheme of the functional module.
7. The method according to any of claims 1 to 4, wherein after selecting the layout and routing result meeting the predetermined specification from the layout and routing results as the layout and routing scheme of the functional module, the method further comprises:
and visually displaying the layout and wiring scheme by using an EDA tool.
8. A device for laying out and routing wires, comprising:
the determining module is used for determining data processing logic among all sub-modules in any functional module in the chip;
the layout and wiring module is used for constraining each submodule in the functional module to carry out layout and wiring according to the star topology structure by utilizing constraint modes with different constraint capacities if the data processing logic is matched with the star topology structure, and obtaining layout and wiring results corresponding to each constraint mode;
and the selection module is used for selecting the layout and wiring result meeting the preset index requirement from all the layout and wiring results to serve as the layout and wiring scheme of the functional module.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the place and route method according to any of claims 1 to 7.
10. A readable storage medium storing a computer program, wherein the computer program when executed by a processor implements the method of laying out and routing according to any one of claims 1 to 7.
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| CN116127905A (en) * | 2023-04-06 | 2023-05-16 | 之江实验室 | Method for designing substrate, substrate and wafer-level chip integrated structure |
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| CN116127905A (en) * | 2023-04-06 | 2023-05-16 | 之江实验室 | Method for designing substrate, substrate and wafer-level chip integrated structure |
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