CN114152870B - Load simulation detection system and wake-up time distribution method of single-fire switch - Google Patents
Load simulation detection system and wake-up time distribution method of single-fire switch Download PDFInfo
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- CN114152870B CN114152870B CN202110655955.0A CN202110655955A CN114152870B CN 114152870 B CN114152870 B CN 114152870B CN 202110655955 A CN202110655955 A CN 202110655955A CN 114152870 B CN114152870 B CN 114152870B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/327—Testing of circuit interrupters, switches or circuit-breakers
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
- H05B47/00—Circuit arrangements for operating light sources in general, i.e. where the type of light source is not relevant
- H05B47/10—Controlling the light source
- H05B47/16—Controlling the light source by timing means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
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Abstract
The invention relates to a load simulation detection system and a wake-up time distribution method of a single-fire switch, wherein the system comprises a simulation working load branch circuit for simulating the working state of a chip of a single-fire switch panel and a simulation dormant load branch circuit for simulating the dormant state of a wireless chip; the selector switch is used for gating the two analog load branches to realize the alternate switching conduction of the analog working load branch and the analog dormant load branch; the control module is used for controlling the change-over switch to alternately conduct the two analog load branch circuits according to the set analog working load and the power-on duration of the analog dormant load so as to determine a group of analog working load and the power-on duration of the analog dormant load, so that the load connected to the bottom plate of the single-fire switch is not slightly flashed, the chip serving as a switch panel is matched with the bottom plate and the connected load of the bottom plate of the single-fire switch in working state time and dormant state time, and the problem of ghost fire generated when the load connected to the bottom plate of the single-fire switch in the industry is in a light-off state is effectively solved.
Description
Technical Field
The invention belongs to the technical field of single-fire switches, and particularly relates to a load simulation detection system and a wake-up time distribution method of a single-fire switch.
Background
A single live wire switch (single live wire switch) as shown in FIG. 1 refers to a switch which can normally work only by connecting a live wire to a switch panel. The single live switch need not connect the zero line in flush mounting plate of switch department promptly, and is the same with traditional machinery single control switch's mode of connection, and relative zero live switch, its benefit is: the switch panel department of the user of traditional fitment does not have the zero line, can't directly replace installation zero line intelligence switch panel, and adopts the single live switch can directly accomplish intelligent transformation, need not to lay the zero line again.
This single live switch in the use, its electricity-taking principle is: the single live switch has to be connected with a load (a lamp), and a zero line at the other end of the load forms a loop, and a part of energy is obtained from the loop to maintain the panel to work. The working principle leads to the phenomenon of 'ghost fire', namely the phenomenon of load micro-flashing in a lamp-off state, when a single-fire switch is used for carrying non-resistance lamps (LED lamps and fluorescent lamps) and is not well processed.
The reason for the occurrence of load micro-flashes is that such lamps are of very low power and will be lit up when very little energy (current) is passed through; if the energy required by the panel is high (i.e. the energy output from the base plate to the panel is higher than a certain value), the lamp will be slightly bright or slightly flash in the off state (referred to as "ghost fire" phenomenon). Moreover, even if the chip of the single-fire switch in the prior art is set to be dormant in the light-off state, the wireless communication module of the switch is in low power consumption, and the micro-flash problem of the small load of the switch in the light-off state cannot be avoided.
Disclosure of Invention
The invention aims to provide a load simulation detection system and a wake-up time distribution method of a single-fire switch, which are used for solving the problem that the existing single-fire switch is easy to have load micro-flash.
Based on the purpose, the technical scheme of the load simulation detection system is as follows:
the simulation branch circuit comprises a simulation working load branch circuit used for simulating the working state of the chip on the single fire switch panel and a simulation dormant load branch circuit used for simulating the dormant state of the chip on the single fire switch panel;
one end of the change-over switch is used for connecting the output end of a DCDC voltage-stabilized power supply on a bottom plate of the tested single fire switch, and the gating end of the change-over switch is in gating connection with the simulation working load branch and the simulation dormant load branch to realize alternate switching conduction of the simulation working load branch and the simulation dormant load branch;
a control module for setting the electrifying time of the simulation work load branch as (t)10-i · Δ t), simulating the energization duration of the dormant load branch as (t)20+ i · Δ t), i ═ 0,1,2, …, Δ t being the first set time step, t10To set the maximum on-time, t, of the dummy workload branch20Controlling the change-over switch to alternately turn on the simulated work load branch and the simulated dormant load branch in order to set the minimum turn-on time of the simulated work load branch so as to determine the power-on time (t) of a group of simulated work load branches10-N · Δ t), simulating the duration of energization (t) of the dormant load branch20+ N.DELTA.t), N is not less than 0, so that the load connected to the bottom plate of the single-fire switch does not have micro-flash, and t is equal to10-N·Δt)、(t20+ N · Δ t) as the operating state time and the resting state time on the switch panel matching the base plate and the load connected thereto.
The beneficial effects of the above technical scheme are:
the load simulation detection system can determine a group of proper conduction time values by repeatedly and rapidly switching the conduction time of the simulation working load branch and the simulation dormant load branch to control the working time and the dormancy time of the upper panel of the single-fire switch, so that the low power consumption of the regular dormancy of the chip on the panel of the single-fire switch and the reasonable distribution of the awakening time of the single-fire switch are realized, and the ghost fire problem of the single-fire switch in a light-off state commonly existing in the industry is effectively solved. Moreover, the system can obtain the test result quickly, improve the test efficiency and reduce the workload and the working time of software personnel and hardware testing personnel.
Furthermore, in order to effectively test the analog branch circuit within a reasonable conduction time range when the system is tested, the system also comprises a first detection branch circuit, wherein the first detection branch circuit comprises a voltage monitoring device connected with the output end of the DCDC stabilized voltage power supply, and is used for determining the maximum time for maintaining the working state of the switch panel according to the voltage waveform of the voltage monitoring device when the analog working load branch circuit is switched on by the switch, namely the maximum conduction time t of the analog working load branch circuit10。
The effect is to determine a reasonable maximum on-time t10The on-time of a group of simulated working load branches and simulated dormant load branches meeting the conditions can be rapidly measured by taking the on-time as a starting point and setting the time step length to carry out the test at one time in a targeted manner.
Furthermore, in order to obtain the optimal working state time and the optimal dormant state time matched with the bottom plate and the load connected with the bottom plate on the switch panel, the system also comprises a second detection branch circuit, wherein the second detection branch circuit comprises a voltage monitoring device connected with the input end of a lamp-turning-off power-taking module on the switch bottom plate, and is used for determining the conducting time of a group of optimal simulated working load branch circuits and simulated dormant load branch circuits as (t) according to the voltage waveform of the voltage monitoring device when the simulated working load branch circuits and the simulated dormant load branch circuits are alternately gated10-N·Δt1+i·Δt2)、(t20+N·Δt1-i·Δt2)，i＝1,2,…，Δt2For a second set time step, Δ t2<Δt1And the time is used as the working state time and the dormant state time which are optimally matched with the bottom plate and the load connected with the bottom plate on the switch panel.
The effect is that on the basis of carrying out coarse adjustment by using the first set time step length, fine adjustment is carried out by using the second set time step length, and the two step length adjustment modes are matched for use, so that the working state time and the sleep state time which are optimally matched with the bottom plate and the load connected with the bottom plate on the switch panel can be obtained.
Further, in order to simulate the load power requirements of the panel of the one-fire switch to be tested in the working state and the dormant state, the simulation workload arranged on the simulation workload branch circuit comprises a variable resistor R1 for adjusting the resistance value of the variable resistor R1, so that the power of the simulation workload reaches the panel required power P1 of the chip of the one-fire switch to be tested in the working state;
the simulated sleep load arranged on the simulated sleep load branch comprises a variable resistor R2 used for adjusting the resistance value of the variable resistor R2, so that the power of the simulated sleep load reaches the panel required power P2 of the chip sleep state of the tested single fire switch.
Furthermore, the control module is a signal generator, the change-over switch is a mechanical switch or two triodes Q11 and Q12, the anode of the triode Q11 is used for connecting the output end of the DCDC voltage-stabilized power supply, the cathode of the triode Q11 is connected with the resistor R1, and the control end of the triode Q11 is connected with the signal generator; similarly, the anode of the transistor Q12 is used for connecting the output end of the DCDC voltage-stabilized power supply, the cathode of the transistor Q12 is connected with the resistor R2, and the control end of the transistor Q12 is connected with the signal generator.
Furthermore, the simulation branch circuit further comprises an ammeter I, the positive end of the ammeter I is connected with the output end of the DCDC voltage-stabilized power supply on the bottom plate of the tested single-fire switch, the negative end of the ammeter I is connected with the fixed end of the change-over switch, and the ammeter I is used for detecting the current on the simulation branch circuit.
Based on the purpose, the technical scheme of the wake-up time distribution method of the single live switch is as follows:
the load simulation detection system is used for testing the bottom plate of the single live switch and the load connected with the bottom plate, and comprises the following steps:
1) controlling the analog working load branch circuit and the analog dormant load branch circuit to be conducted in turn, and adjusting the resistance values of variable resistors in the analog working load branch circuit and the analog dormant load branch circuit to enable the power of the analog working load branch circuit and the analog dormant load branch circuit to reach the working required power P1 and the dormant required power P2 on the single fire switch panel;
2) within a set time range (t)max,tmin) Gradually adjusting the conduction duration of the simulated working load branch and the simulated dormant load branch according to the set time step length delta t, and judging whether the load connected with the switch bottom plate has micro-flash or not in the testing process of each adjustment; until the conduction time (t) of a group of simulated workload branches and simulated dormant load branches is found10-N·Δt，t20+ N.DELTA.t), the load connected to the bottom plate of the tested single-fire switch can not be slightly flashed all the time when the two analog load branches are switched on, and the working state time and the dormant state matched with the bottom plate and the type of the load connected with the bottom plate on the switch panel can be determinedA (c) is added;
in this step, tmaxFor simulating the maximum on-time t of the working load branch10，tminAnd the minimum communication time length specified by the communication rule is adopted when the chip on the tested single fire switch panel is communicated.
The effect of the above technical scheme is:
the wake-up time distribution method of the single fire switch utilizes the load simulation detection system, can efficiently solve the problem of time distribution of the working and sleeping time of the chip on the switch panel, saves the cost of manpower and material resources, and can effectively avoid the problem of the ghost fire of the single fire switch.
Further, in order to obtain the optimal working state time and the optimal dormant state time matched with the bottom plate and the load connected with the bottom plate on the switch panel, the method further comprises the following step 3):
within a set time range (t)10-N·Δt1，t10) At a second set time step Δ t2，Δt2<Δt1Gradually adjusting the conduction time of the simulated working load branch and the simulated dormant load branch, wherein the conduction time of the simulated working load branch and the simulated dormant load branch which are adjusted each time is (t)10-N·Δt1+i·Δt2)、(t20+N·Δt1-i·Δt2) 1,2, …, it is long to confirm that a set of switches on, can guarantee that the load that the bottom plate is connected does not produce the critical condition of little sudden strain of a muscle, and this critical condition is judged through the voltage monitoring device who gets the electricity module input and be connected with the switch bottom plate lamp-turning off, and the judgement standard is: the voltage waveform displayed on the voltage monitoring device can be maintained stable without generating voltage drop; and taking a group of conduction time lengths meeting the judgment standard as the working state time and the dormant state time which are optimally matched with the type of the bottom plate and the load connected with the bottom plate on the switch panel.
Further, in order to ensure that the conduction time of a group of simulated work load branches and simulated dormant load branches for avoiding the micro-flash of the single-fire switch load can be determined, the method further comprises the following steps:
when in the set time range (t)max,tmin) Gradually adjusting the conduction time of the simulated working load branch and the simulated dormant load branch for multiple times until the last group of conduction time tmin、(T-tmin) And T is a preset wake-up period, and no group of conduction time length which can prevent the load connected with the bottom plate of the single-fire switch from micro-flashing is found, so that a third set time step length delta T is needed3，Δt3<Δt1Gradually increasing the conduction time of the simulated dormant load branch and maintaining the conduction time t of the simulated working load branchminAnd turning on the two analog load branches again in turn without changing the current until finding a group of turn-on time tmin、(T-tmin+i·Δt3) I is 1,2, …, the load connected to the base plate of the single fire switch is not micro-flash, and the wake-up period is adjusted to (T + i. delta T)3)。
Further, in order to increase the applicability of the wake-up time distribution method to single fire switches of various load models, the method further comprises the following steps: respectively testing the single live switch bottom plates of n load signals and loads connected with the single live switch bottom plates by using the contents in the steps 1), 2) and 3), wherein n is more than or equal to 2, determining the conduction time of n groups of simulated working load branches and simulated sleeping load branches capable of avoiding micro-flash, comparing the conduction time of the n groups of simulated working load branches, and taking the conduction time of a group corresponding to the minimum value as the finally determined working state time and sleeping time of the switch panel; or comparing n groups, simulating the conducting time of the dormant load branch, and taking the conducting time group corresponding to the maximum value as the finally determined working state time and the dormant time of the switch panel chip.
Drawings
FIG. 1 is a schematic diagram of a single live switch wiring configuration in the prior art of the present invention;
FIG. 2 is a schematic diagram of a load simulation test system in an embodiment of the system of the present invention;
FIG. 3 is an overall circuit diagram of a single fire switch in an embodiment of the system of the present invention;
FIG. 4 is a schematic view of a load simulation test system in embodiment 2 of the method of the present invention;
fig. 5 is a circuit diagram of another connection of a diverter switch in an embodiment of the system of the present invention.
Detailed Description
The following further describes embodiments of the present invention with reference to the drawings.
The embodiment of the system is as follows:
the present embodiment provides a load simulation detecting system, as shown in fig. 2, the load simulation detecting system includes: the device comprises an analog branch and a first detection branch, wherein the analog branch comprises hardware comprising resistive analog loads R1 and R2, a change-over switch K1, a signal generator Q1 and an ammeter I, wherein the negative end of the ammeter I is connected with the fixed end of a change-over switch K1, the first gating end of the change-over switch K1 is sequentially connected with a variable resistor R1 (also called an analog working load) and a ground GND, and the branch where the variable resistor R1 and the ground GND are located is the analog working load branch; the second gating end of the switch K2 is sequentially connected with a variable resistor R2 (also called a simulated sleeping load) and a ground GND, and a branch where the variable resistor R2 and the ground GND are located is a simulated sleeping load branch; the output end of the signal generator is connected with a switch K1 for providing a trigger signal of the switch.
In fig. 2, the positive terminal of the ammeter I is connected to the output terminal of the DCDC voltage-stabilized power supply on the bottom plate of the single fire switch, and the connected detection branch is: and the first detection branch is connected with the output end of the DCDC stabilized voltage supply and is provided with an oscilloscope M2.
The left part in fig. 2 is a part of the circuit on the bottom plate of the single fire switch, and the whole circuit of the single fire switch is shown in fig. 3 and comprises a bottom plate and a panel, wherein the bottom plate comprises: the lamp-turning-off and power-taking module is connected with a load, and a DCDC voltage-stabilizing power supply, wherein the input end of a relay driving and lamp-turning-on and power-taking circuit is connected with the load through a relay, the output end of the relay driving and lamp-turning-on and power-taking circuit is connected with the DCDC voltage-stabilizing power supply, the output end of the DCDC voltage-stabilizing power supply is connected with a panel, a monitoring signal port on the panel is connected with a load detection module, and the load detection module is connected with the load; and a control signal port on the panel is connected with a relay driving and light-on power-taking circuit and used for sending a relay control signal. Specifically, the hardware components of the single fire switch are described as follows:
(1) turning off the lamp and getting the electricity module: for obtaining a voltage in the off state, i.e. with the relay open. The module does not work (cannot get electricity) under the relay closed state (the light-on state).
(2) The relay drives and turns on the light and gets the electric circuit: the relay is used for driving and controlling the relay and taking electricity in a light-on state (namely, in a relay closing state).
(3) A DCDC voltage-stabilized source: the power supply circuit comprises a power supply chip, wherein the power supply chip is used for ensuring that the power supply circuit can be normally started, and the voltage is increased to more than 5V to start a DCDC voltage-stabilized power supply to supply power to a later stage.
(4) The load detection circuit: for obtaining a signal for monitoring the load. The relay is disconnected, no load exists, and high level is output; carrying and outputting low level; the relay is closed, and no matter load or no load, high level is output.
(5) Power and signal interface section: for obtaining power and load monitoring signals for the backplane, and for sending relay control signals.
When the single live switch is turned off, the panel of the single live switch in fig. 3 is powered by the load-off power supply module-DCDC voltage-stabilized power supply to provide a current for the panel to operate and sleep, so that the load simulation detection system of the embodiment utilizes the simulation branch to simulate the operating and sleep states of the panel (the panel power requirement in the chip operating state is P1, and the panel power requirement in the chip sleep state is P2) to determine the optimal time for the panel to operate and sleep, thereby achieving the purpose of avoiding the "ghost fire".
Based on the above consideration, after the load simulation detection system is built, the test process of the load simulation detection system on the switch bottom plate and the load connected with the switch bottom plate is as follows:
and S1, controlling the first gating end of the switch K1 to be connected, enabling the analog working branch where the resistor R1 (which is a variable resistor) is located to be connected, gradually adjusting the resistor R1 until the power of the resistor R1 reaches the required power P1 of the panel in the working state, and not adjusting the resistance value of the resistor R1 any more.
In this step, in the process of adjusting the resistance value of the resistor R1, a current value is obtained through the ammeter I, and the power P1 of the resistor R1 is calculated in combination with the resistance value of the resistor R1 (the internal resistance of which is known), and when the power P1 reaches the required power P1, the resistance value of the resistor R1 is not adjusted.
Similarly, the second gating end of the switch K1 is controlled to be connected, so that the analog working branch where the resistor R2 (which is a variable resistor) is located is connected, the resistance of the resistor R2 is gradually adjusted until the power P2 of the resistor R2 reaches the required power P2 of the panel in the sleep state, and the resistance of the resistor R2 is not adjusted.
Similarly, by calculating the power P2 of the resistor R2, when the power P2 reaches the required power P2, the resistance of R2 is not adjusted.
S2, controlling the first gating end of the switch K1 to be switched on, starting timing, monitoring the voltage value on the oscilloscope M2, continuously timing when the voltage waveform trend displayed on the oscilloscope M2 is stable, ending timing when the voltage waveform trend is reduced (the voltage is continuously reduced within a certain short time), and counting the time period to be t10The time period is the maximum on time of the analog workload (resistor R1), i.e. the maximum time for the switch panel to maintain the operating state.
Acquiring a wake-up period T of the switch panel, and combining the maximum working time T of the panel with the sum of the working time T1 and the sleep time T2 of the chip on the panel according to the wake-up period T10The minimum on-time t of the simulated sleep load (resistor R2) is calculated20I.e. the minimum time for which the switch panel remains in the sleep state, t20＝T-t10。
S3, the resistance values of the R1 and the R2 which are adjusted in the step S1 are maintained unchanged, and the time length t set in the step S2 is set10、t20Controlling the first and second pass ends of the switch K1 to switch them several times continuously, i.e. electrifying the analog work load (resistor R1) for a period of time t10And simulating the power-on of the dormant load (resistor R2) for a period of time t20And repeating the steps for several times, and checking whether the load connected to the switch bottom plate in the process has micro-flash.
If micro-flash occurs, the power-on duration of the simulation workload is adjusted to be (t) according to the set time step length delta t and the first time10- Δ t), the power-on duration of the simulated sleeping load is adjusted to (t)20+ Δ t), and switching the first gating end and the second gating end for a plurality of times continuously, repeating for a plurality of times, and checking whether the load connected to the switch bottom plate in the process has micro-flash. If micro-flash still occurs, the power-on duration of the simulation workload is adjusted to be smaller for the second time according to the set time step length delta t, and the power-on duration is (t)10-2 Δ t), the power-on duration of the simulated sleeping load is increased by (t)20+2 Δ t), the switch is switched over again after the adjustment, the power-on duration is controlled, and whether the load connected with the bottom plate is slightly flashed or not is observed.
The power-on time of the analog workload is (t) until the Nth adjustment10-N · Δ t), the duration of energization of the simulated sleeping load being (t)20+ N.DELTA.t), the working state time (t) of the switch panel matched with the bottom plate and the load connected with the bottom plate can be determined according to the fact that the load connected with the bottom plate does not have the micro-flash phenomenon after the two paths of loads are controlled to be switched on in turn at the moment10-N · Δ t), sleep time (t)20+ N.DELTA.t), N is not less than 0, and the load connected to the base plate can be ensured not to generate micro-flash.
In this embodiment, the initial value of the wake-up period T is a reasonable preset value based on the experience effect, and the value is equal to the sum of the operating time and the sleep time of the chip. In addition, since the duty ratio of the chip on time to the chip off time is larger, the possibility of the lamp flickering is higher (the supplied energy is lower than the consumed energy), and therefore, the adjustment of the on time t1 of the wireless chip on the panel needs to be within a certain range (t 1)max,tmin) Internal implementation, tmaxIs the maximum working time t10The time is tminThe minimum communication time length determined by a certain communication rule is adopted when the chip on the panel communicates, for example, 150ms is taken.
The two-way duration adjustment process is illustrated below:
when the set wake-up period T is 1S, T is determined according to the contents of step S2maxTake 500ms, then tminAnd taking 150ms, namely determining the conduction time of the first group of the simulated workload and the simulated sleep load as (500ms ), switching the simulated load to be conducted according to the conduction time, and if the load connected with the bottom plate has micro-flash, adjusting the conduction time of the simulated workload and the simulated sleep load once to be (450ms, 550ms) according to the set time step delta t as 50ms, and controlling the switching of the simulated load to be conducted according to the conduction time.
If the load connected with the bottom plate still has micro-flash, the conduction time of the simulated work load and the simulated sleep load is adjusted to (400ms, 550ms) again, and so on until the conduction time (t) of a certain group of the simulated work load and the simulated sleep load is found10-N·Δt，t20+ N.DELTA.t), can make two-way analog load switch the conducting process, the load that connects on the bottom plate does not take place the micro flash phenomenon all the time, then confirm the panel operating condition time that can avoid the micro flash problem under the load type that this bottom plate connects, dormancy time, as long as according to work and dormancy of the control single fire switch upper panel of this time, can effectual elimination single fire switch "ghost fire" phenomenon when turning off the light.
In this embodiment, the switch K1 is used to switch the resistive analog loads R1 and R2, and thus, the switch may be a mechanical switch, an electronic switch, a triode, a MOS transistor, or other devices or tools with a switch switching function. For example, if the switch is used, two gating branches are provided, the first gating branch is connected with the fixed end of the switch K1 and the first gating end, and the second gating branch is connected with the fixed end of the switch K1 and the second gating end.
If the triode is adopted for realizing the purpose, the change-over switch K1 comprises two triodes Q11 and Q12, the anode of the triode Q11 is used for connecting the output end of a DCDC stabilized power supply, the cathode of the triode Q11 is connected with a resistor R1, and the control end of the triode Q11 is connected with a signal generator; similarly, the anode of the transistor Q12 is used for connecting the output end of the DCDC voltage-stabilized power supply, the cathode of the transistor Q12 is connected with the resistor R2, and the control end of the transistor Q12 is connected with the signal generator.
As another implementation manner, switching of the two analog load branches may also be implemented by using a transistor, as shown in fig. 5, the branch where the variable resistor R1 is located is controlled by using a transistor Q1.
In this embodiment, the signal generator is used to provide a trigger signal for the switch K1, so as to switch the switch to the resistive load 1 (i.e., the resistor R1) or the analog load 2 (i.e., the resistor R2), and simulate the operating state and the sleep state on the switch panel, respectively.
In this embodiment, the oscilloscope is used to measure the voltage waveform change, and therefore, as another implementation, a digital multimeter may be used instead of the oscilloscope to measure the voltage waveform change.
The load simulation detection system has the following advantages:
(1) the on-time of the simulated work load and the simulated dormancy load tested by the system is used for controlling the work and dormancy time of a chip (namely a ZigBee module in a figure 3) on a single-fire switch panel, so that the low power consumption of the chip of the single-fire switch for regular dormancy is realized, and the problem of ghost fire of the switch bottom plate connecting load commonly existing in the industry is solved.
(2) The system can obtain the test result quickly, improve the test efficiency and reduce the workload and the working time of software personnel and hardware testing personnel; the accuracy and effectiveness of determining the working and sleep time of the switch panel are improved.
Method example 1:
based on the load simulation detection system in the above system embodiment, this embodiment provides a wake-up time allocation method for a single fire switch, including the following steps:
1) the panel of the single-fire switch is simulated by using the load simulation detection system, the simulation branch of the load simulation detection system is connected with the DCDC voltage-stabilized power supply on the bottom plate of the single-fire switch, two paths of simulation loads on the simulation branch are controlled to be conducted in turn, namely a simulation working load and a simulation dormant load are conducted in turn, the resistance values of variable resistors R1 and R2 in the simulation working load and the simulation dormant load are adjusted, and the power of the simulation working load and the simulation dormant load reaches the working state required power P1 and the dormant state required power P2 of the panel of the single-fire switch (namely the required power of the panel when the wireless communication chip is dormant).
2) Adjusting the resistance values of the resistors R1 and R2 according to the step 1) within a set time range (t)max,tmin) Gradually adjusting the conduction time of the simulated work load and the simulated dormant load according to the set time step length delta t, and judging whether the load connected with the switch bottom plate has micro-flash or not in the process; on-time (t) until finding a set of simulated workload, simulated sleeping loads10-N·Δt，t20+ N.DELTA.t), can make two way analog load switch the conducting process, the load that connects on the bottom plate does not take place the micro flash phenomenon all the time, then confirm the panel reasonable operating condition time that can avoid the micro flash problem under the load type that this bottom plate connects, dormancy time to realize the rational distribution of the awakening time of single fire switch, can effectual elimination single fire switch "ghost fire" phenomenon when turning off the light.
In this step, tmaxIs the maximum working time t10The determination process is described in the related description of the system embodiment, tminAnd the minimum communication time length is determined by adopting a certain communication rule when the chip on the panel communicates.
According to the wake-up time distribution method of the single fire switch, the load simulation detection system is utilized, the problem of time distribution of working and sleeping of the switch panel can be efficiently solved, the cost of manpower and material resources is saved, and the problem of ghost fire of the single fire switch can be effectively avoided.
Method example 2:
the present embodiment is also a load simulation test system, as shown in fig. 4, a second test branch is added to the system in fig. 2, and the second test branch includes an oscilloscope M1 connected to the input terminal of the lamp-off power-on module on the switch backplane.
Based on the system, the method for allocating wake-up time of a single live switch proposed in this embodiment is different from the method in method embodiment 1 in that the conduction time (t) of the simulated workload and the simulated sleep load determined in method embodiment 1 are10-N·Δt，t20+ N · Δ t), which is a reasonable value to ensure that no micro-flash trimming occurs after the switch is used, is not the optimal on-time, which is the present embodimentThe method can determine a group of optimal values for ensuring that the micro-flash fine tuning does not occur after the switch is used, and the method comprises the following steps:
according to the content of step 1) and step 2) in method embodiment 1, the on-time of the simulated workload and the simulated dormant load is determined as (t)10-N·Δt1，t20+N·Δt1)，Δt1The method is characterized by further comprising the following steps of:
3) within a set time range (t)10-N·Δt1，t10) At a second set time step Δ t2，Δt2<Δt1Gradually adjusting the conduction time of the simulated work load and the simulated sleep load, wherein the conduction time of the simulated work load and the simulated sleep load which are adjusted each time is (t)10-N·Δt1+i·Δt2)、(t20+N·Δt1-i·Δt2) And i is 1,2 and …, finding a group of conducting time length, and ensuring that the load on the panel does not generate the critical condition of micro-flash, wherein the critical condition is judged by observing an oscilloscope M1 on a second detection branch in the load simulation detection system, and the judgment standard is as follows: the voltage waveform displayed on the oscilloscope M1 can be maintained steady (maintaining a horizontal line for a long time) without a voltage drop over time.
The implementation process of this step is illustrated:
the determined parameters are: first set time step Δ t150ms, second set time step Δ t210ms, the maximum on-time t of the simulated work load10500ms, N3, then (t)10-N·Δt1，t10) Is (350ms, 500 ms).
In this step, within a range of (350ms, 500ms), with a step length of 10ms as a unit of one-time adjustment, the turn-on duration of the analog workload of 10ms is increased, and the turn-on duration of the analog sleep load of 10ms is decreased, where the turn-on durations of the analog workload and the analog sleep load adjusted each time are (350+ i · Δ t)2)、(650-i·Δt2) I is 1,2, …,5, where the maximum value of i is given by Δ t1And Δ t2Is determined by the ratio of (a) to (b).
In the step 2), the conduction time lengths of the two paths of analog loads are adjusted by taking every 50ms as a step length, so that a non-maximum conduction time length which meets the condition that the analog working loads do not have micro-flash may be found, however, in the aspect of the distribution problem of the panel wake-up period of the single-fire switch, compared with the time of the sleep state, the time of the working state is preferably ensured to be longer. Based on the consideration, on the basis of roughly adjusting the conduction time of the two paths of analog loads in the step 2), fine adjustment of the conduction time of the two paths of analog loads is performed again in the step.
Method example 3:
the method for allocating wake-up time of a single fire switch in this embodiment is different from the method in embodiment 1 in that the wake-up time is within a set time range (t)max,tmin) Gradually adjusting the conduction time of the simulated work load and the simulated dormant load for many times until the last group of conduction time tmin、(T-tmin) None of the groups of conduction time lengths is found, so that the load connected with the base plate of the single-fire switch can not generate micro-flash, such as tmin＝150ms，T＝1s，(T-tmin) 850ms, a third set time step Δ t is required3，Δt3<Δt1E.g., 20ms, the conduction time of the emulated sleep load is gradually increased and the conduction time t of the emulated working load is maintainedminThe two branches of the analog load are conducted again in turn without changing the current time until a group of conducting time duration t is foundmin、(T-tmin+i·Δt3) And i is 1,2 and …, so that the load connected with the bottom plate of the single fire switch does not have micro-flash.
Method example 4:
the method for allocating wake-up time of a single live switch in this embodiment is different from the method in method embodiment 2 in that the method in method embodiment 2 is directed to a certain load model connected to a single live switch backplane, and the method for allocating wake-up time determined in this embodiment is applicable to a plurality of load models, and the specific method is as follows:
taking load models connected by multiple (i.e. n) single-fire switch baseplates, e.g. three loadsThe load model number and the rated power of the three loads are respectively 5w, 7w and 9w, the load simulation detection system in the system embodiment is sequentially utilized to respectively detect the bottom plates of the three connected loads, according to the method in the method embodiment 1/method embodiment 2, the conduction time of three groups of simulated working loads and simulated dormant loads capable of avoiding the micro-flash phenomenon is determined, and the determined conduction time of the three groups is respectively (t) t1 1,t1 2)、(t2 1,t2 2)、(t3 1,t3 2) Comparing the conduction time t of the three groups of simulated work loads1 1、t2 1、t3 1Taking the set of on-times for which the minimum value corresponds, e.g. t1 1At a minimum, then (t)1 1,t1 2) As the finally determined working state time and the sleep time of the switch panel, the single-fire switch of various types of loads can be used simultaneously, and the problem of load micro-flash of the switch during the light-off process can be avoided.
Or comparing the conduction time t of three groups of simulated dormant loads1 2、t2 2、t3 2The group of conduction time corresponding to the maximum value is taken as the finally determined working state time and the sleep time of the switch panel, and the switch panel can be adapted to different lamps to be tested.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting the same, and although the present invention is described in detail with reference to the above embodiments, those of ordinary skill in the art should understand that: modifications and equivalents may be made to the embodiments of the invention without departing from the spirit and scope of the invention, which is to be covered by the claims.
Claims (10)
1. A load simulation test system, comprising:
the simulation branch circuit comprises a simulation working load branch circuit used for simulating the working state of the chip on the single fire switch panel and a simulation dormant load branch circuit used for simulating the dormant state of the chip on the single fire switch panel;
one end of the change-over switch is used for connecting the output end of a DCDC voltage-stabilized power supply on a bottom plate of the tested single fire switch, and the gating end of the change-over switch is in gating connection with the simulation working load branch and the simulation dormant load branch to realize alternate switching conduction of the simulation working load branch and the simulation dormant load branch;
a control module for setting the electrifying time of the simulation work load branch as (t)10-i · Δ t), simulating the energization duration of the dormant load branch as (t)20+ i · Δ t), i ═ 0,1,2, …, Δ t being the first set time step, t10To set the maximum on-time, t, of the dummy workload branch20In order to set the minimum conduction time of the simulation working load branch, the change-over switch is controlled to alternately conduct the simulation working load branch and the simulation dormant load branch so as to determine the electrifying time (t) of a group of simulation working load branches10-N · Δ t), simulating the duration of energization (t) of the dormant load branch20+ N.DELTA.t), N is not less than 0, so that the load connected to the bottom plate of the one-fire switch does not have micro-flash, and t is equal to10-N·Δt)、(t20+ N · Δ t) as the operating state time and the resting state time on the switch panel matching the base plate and the load connected thereto.
2. The load simulation detection system according to claim 1, further comprising a first detection branch, wherein the first detection branch comprises a voltage monitoring device connected to the output terminal of the DCDC regulated power supply, and is configured to determine a maximum time for maintaining the operation state of the switch panel, i.e. a maximum on-time t of the analog work load branch, according to a voltage waveform of the voltage monitoring device when the analog work load branch is switched on by the switch10。
3. The load simulation test system of claim 1, further comprising a second test branch, the second test branch comprisingThe voltage monitoring device is connected with the input end of the lamp-turning-off power-taking module on the switch bottom plate and used for determining the conducting time length of a group of optimal simulated working load branches and simulated dormant load branches according to the voltage waveform of the voltage monitoring device when the simulated working load branches and the simulated dormant load branches are turned on in turn (t)10-N·Δt1+i·Δt2)、(t20+N·Δt1-i·Δt2)，i＝1,2,…，Δt2For a second set time step, Δ t2<Δt1And the time is used as the working state time and the dormant state time which are optimally matched with the bottom plate and the load connected with the bottom plate on the switch panel.
4. The load simulation detection system according to claim 1, wherein the simulation workload arranged on the simulation workload branch comprises a variable resistor R1 for adjusting the resistance of the variable resistor R1, so that the power of the simulation workload reaches the panel required power P1 of the chip operating state of the tested single fire switch;
the simulated sleep load arranged on the simulated sleep load branch comprises a variable resistor R2 used for adjusting the resistance value of the variable resistor R2, so that the power of the simulated sleep load reaches the panel required power P2 of the chip sleep state of the tested single fire switch.
5. The load simulation detection system according to claim 1, wherein the control module is a signal generator, the switch is a mechanical switch or two transistors Q11, Q12, an anode of the transistor Q11 is used for connecting an output end of a DCDC regulated power supply, a cathode of the transistor Q11 is connected with a resistor R1, and a control end of the transistor Q11 is connected with the signal generator; similarly, the anode of the transistor Q12 is used for connecting the output end of the DCDC voltage-stabilized power supply, the cathode of the transistor Q12 is connected with the resistor R2, and the control end of the transistor Q12 is connected with the signal generator.
6. The load simulation detection system according to claim 4, wherein the simulation branch further comprises an ammeter I, a positive terminal of the ammeter I is connected to the output terminal of the DCDC voltage-stabilized power supply on the bottom plate of the tested single fire switch, a negative terminal of the ammeter I is connected to the fixed terminal of the switch, and the ammeter I is used for detecting the current on the simulation branch.
7. A wake-up time distribution method of a single live switch, characterized in that a baseplate of the single live switch and a load connected with the baseplate are tested by using the load simulation detection system according to any one of claims 1 to 6, and the method comprises the following steps:
1) controlling the analog working load branch circuit and the analog dormant load branch circuit to be conducted in turn, and adjusting the resistance values of variable resistors in the analog working load branch circuit and the analog dormant load branch circuit to enable the power of the analog working load branch circuit and the analog dormant load branch circuit to reach the working required power P1 and the dormant required power P2 on the single fire switch panel;
2) within a set time range (t)max,tmin) Gradually adjusting the conduction duration of the simulated working load branch and the simulated dormant load branch according to the set time step length delta t, and judging whether the load connected with the switch bottom plate has micro-flash or not in the testing process of each adjustment; until the conduction time (t) of a group of simulated workload branches and simulated dormant load branches is found10-N·Δt，t20+ N.DELTA.t), the load connected with the bottom plate of the tested single fire switch can not be slightly flashed all the time in the switching and conducting process of the two analog load branches, and the working state time and the dormant state time matched with the bottom plate and the type of the load connected with the bottom plate on the switch panel are determined;
in this step, tmaxFor simulating the maximum on-time t of the working load branch10，tminAnd the minimum communication time length specified by the communication rule is adopted when the chip on the tested single fire switch panel is communicated.
8. The wake-up time distribution method for a single fire switch according to claim 7, further comprising the following step 3):
within a set time range (t)10-N·Δt1，t10) At a second set time stepΔt2，Δt2<Δt1Gradually adjusting the conduction time of the simulated working load branch and the simulated dormant load branch, wherein the conduction time of the simulated working load branch and the simulated dormant load branch which are adjusted each time is (t)10-N·Δt1+i·Δt2)、(t20+N·Δt1-i·Δt2) 1,2, …, it is long to confirm that a set of switches on, can guarantee that the load that the bottom plate is connected does not produce the critical condition of little sudden strain of a muscle, and this critical condition is judged through the voltage monitoring device who gets the electricity module input and be connected with the switch bottom plate lamp-turning off, and the judgement standard is: the voltage waveform displayed on the voltage monitoring device can be maintained stable without voltage drop; and taking a group of conduction time lengths meeting the judgment standard as the working state time and the dormant state time which are optimally matched with the type of the bottom plate and the load connected with the bottom plate on the switch panel.
9. The wake-up time distribution method for a single fire switch according to claim 7, further comprising the steps of:
when in the set time range (t)max,tmin) Gradually adjusting the conduction time of the simulated working load branch and the simulated dormant load branch for multiple times until the last group of conduction time tmin、(T-tmin) And T is a preset wake-up period, and no group of conduction time length which can prevent the load connected with the bottom plate of the single-fire switch from micro-flashing is found, so that a third set time step length delta T is needed3，Δt3<Δt1Gradually increasing the conduction time of the simulated dormant load branch and maintaining the conduction time t of the simulated working load branchminThe two analog load branches are conducted again in turn without change until a group of conducting time duration t is foundmin、(T-tmin+i·Δt3) I is 1,2, …, the load connected to the base plate of the single fire switch is not micro-flash, and the wake-up period is adjusted to (T + i. delta T)3)。
10. The wake-up time distribution method for a single fire switch according to claim 8, further comprising the steps of: respectively testing the single live switch bottom plates of n load signals and loads connected with the single live switch bottom plates by using the contents in the steps 1), 2) and 3), wherein n is more than or equal to 2, determining the conduction time of n groups of simulated working load branches and simulated sleeping load branches capable of avoiding micro-flash, comparing the conduction time of the n groups of simulated working load branches, and taking the conduction time of a group corresponding to the minimum value as the finally determined working state time and sleeping time of the switch panel; or comparing n groups, simulating the conducting time of the dormant load branch, and taking the conducting time group corresponding to the maximum value as the finally determined working state time and the dormant time of the switch panel chip.
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