CN114152228A - Method, system, equipment and storage medium for checking chip surrounding capacitance - Google Patents

Method, system, equipment and storage medium for checking chip surrounding capacitance Download PDF

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Publication number
CN114152228A
CN114152228A CN202111271374.3A CN202111271374A CN114152228A CN 114152228 A CN114152228 A CN 114152228A CN 202111271374 A CN202111271374 A CN 202111271374A CN 114152228 A CN114152228 A CN 114152228A
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power supply
capacitor
capacitors
chip
supply pins
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CN114152228B (en
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宫鹏
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01BMEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01BMEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B21/00Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant
    • G01B21/02Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness
    • G01B21/04Measuring arrangements or details thereof, where the measuring technique is not covered by the other groups of this subclass, unspecified or not relevant for measuring length, width, or thickness by measuring coordinates of points
    • G01B21/047Accessories, e.g. for positioning, for tool-setting, for measuring probes
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2805Bare printed circuit boards
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/281Specific types of tests or tests for a specific type of fault, e.g. thermal mapping, shorts testing
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Measurement Of Resistance Or Impedance (AREA)

Abstract

The invention provides a method, a system, equipment and a storage medium for checking the capacitance around a chip, wherein the method comprises the following steps: determining all first capacitors in a preset range of pins on the outermost layer of the chip, and acquiring the positions and sizes of the first capacitors; obtaining coordinates of all power supply pins of the chip, and determining the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius; determining a second capacitor of the first capacitor in the detection range, and judging whether the number and the size of the second capacitors are the same as a preset value or not; and determining that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as the preset value. The invention determines the detection range of the power supply pins by acquiring the coordinates of all the power supply pins of the chip, taking the coordinates of the power supply pins as the center and taking the preset interval as the radius, and improves the design reliability of the PCB and greatly improves the design efficiency of the PCB by checking whether the quantity and the size of the capacitors in the detection range meet the requirements or not.

Description

Method, system, equipment and storage medium for checking chip surrounding capacitance
Technical Field
The present invention relates to the field of chips, and more particularly, to a method, system, device, and storage medium for checking a capacitance around a chip.
Background
At present, a plurality of types of Printed Circuit Board (PCB) design software exist in the market, and Cadence is used as the most widely applied software in the industry, not only because it has strong functions and a plurality of types of related software for support, but also because it provides an open secondary development interface and a more perfect development language library, users can perform secondary development according to their own needs. The sketch language is a high-level programming language which is built in Cadence software and is based on a C language and an LISP language, the Cadence provides rich interactive functions for the sketch language, and the work efficiency can be greatly improved by researching the sketch language and then writing tools.
Various capacitances can be seen on the power supply filter circuit, for example, different capacitance values of 100uF, 10uF, 100nF, 10 nF. The digital circuit needs to operate stably and reliably, the power supply needs to be 'clean', energy supplement needs to be timely, and filtering decoupling needs to be good. In short, filtering decoupling is to store energy when the chip does not need current and to replenish energy in time when the chip needs current. The function of the capacitor is to store charge. Capacitive filtering is added in the power supply, and a certain amount of capacitive decoupling is placed on the power pin of each chip. In the PCB design stage, the board card needs to uniformly place capacitors around pins of the chip according to the number and the capacitance value of the capacitors in the schematic diagram. The number of the pins of some chips is very large, and the number of the pins of some chips is as high as 800 and 1000. The server mainboard is provided with dozens of chips, so that manual inspection is time-consuming and labor-consuming, the inspection efficiency is low, and the accuracy is not high. Poor capacitance filtering effect can be caused in the later period, and the problem is difficult to find, so that the design quality of the whole system is influenced.
Disclosure of Invention
In view of this, an embodiment of the present invention provides a method, a system, a computer device, and a computer readable storage medium for checking capacitors around a chip, in which coordinates of all power supply pins of the chip are obtained, a detection range of the power supply pins is determined by taking the coordinates of the power supply pins as a center and taking a preset pitch as a radius, and whether the number and size of the capacitors in the detection range meet requirements is checked, so that PCB design reliability is improved and PCB design efficiency is greatly improved.
In view of the above, an aspect of the embodiments of the present invention provides a method for checking a capacitance around a chip, including the following steps: determining all first capacitors in a preset range of pins on the outermost layer of a chip, and acquiring the positions and the sizes of the first capacitors; obtaining coordinates of all power supply pins of the chip, and determining the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius; determining second capacitors of the first capacitors in the detection range, and judging whether the number and the size of the second capacitors are the same as a preset value or not; and determining that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as a preset value.
In some embodiments, the method further comprises: judging whether a second capacitor exists in the detection range of the plurality of power supply pins at the same time; and responding to the fact that the second capacitor exists in the detection range of the plurality of power supply pins at the same time, and detecting whether the second capacitor is a filter capacitor.
In some embodiments, the detecting whether the second capacitance is a filter capacitance comprises: judging whether the second capacitor is connected with the nearest power supply pin or not; and in response to the second capacitor being connected to the nearest supply pin, considering the second capacitor to be a filter capacitor of the nearest supply pin.
In some embodiments, the method further comprises: and responding to the fact that the second capacitor is not connected with a power supply pin, giving an alarm and highlighting the second capacitor.
In another aspect of the embodiments of the present invention, a system for checking a capacitance around a chip is provided, including: the first acquisition module is configured to determine all first capacitors in a preset range of pins at the outermost layer of the chip and acquire the positions and sizes of the first capacitors; the second acquisition module is configured to acquire coordinates of all power supply pins of the chip, and determine the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius; the judging module is configured to determine a second capacitor of the first capacitor in the detection range, and judge whether the number and the size of the second capacitors are the same as a preset value; and the determining module is configured to determine that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as preset values.
In some embodiments, the system further comprises a detection module configured to: judging whether a second capacitor exists in the detection range of the plurality of power supply pins at the same time; and responding to the fact that the second capacitor exists in the detection range of the plurality of power supply pins at the same time, and detecting whether the second capacitor is a filter capacitor.
In some embodiments, the detection module is further configured to: judging whether the second capacitor is connected with the nearest power supply pin or not; and in response to the second capacitor being connected to the nearest supply pin, considering the second capacitor to be a filter capacitor of the nearest supply pin.
In some embodiments, the system further comprises an alert module configured to: and responding to the fact that the second capacitor is not connected with a power supply pin, giving an alarm and highlighting the second capacitor.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: the detection range of the power supply pins is determined by acquiring the coordinates of all the power supply pins of the chip, centering the coordinates of the power supply pins and taking the preset distance as the radius, and the PCB design efficiency is greatly improved while the reliability of the PCB design is improved by checking whether the quantity and the size of capacitors in the detection range meet the requirements.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a method for inspecting a capacitance around a chip according to the present invention;
FIG. 2 is a diagram of an embodiment of a system for checking capacitance around a chip according to the present invention;
FIG. 3 is a schematic diagram of a hardware structure of an embodiment of a computer apparatus for checking a capacitance around a chip according to the present invention;
FIG. 4 is a diagram of an embodiment of a computer storage medium for checking capacitance around a chip according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In a first aspect of embodiments of the present invention, an embodiment of a method of checking a capacitance around a chip is presented. Fig. 1 is a schematic diagram illustrating an embodiment of the method for checking the capacitance around the chip according to the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, determining all first capacitors in a preset range of pins on the outermost layer of the chip, and acquiring the positions and sizes of the first capacitors;
s2, obtaining coordinates of all power supply pins of the chip, and determining the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius;
s3, determining second capacitors of the first capacitors in the detection range, and judging whether the number and the size of the second capacitors are the same as a preset value or not; and
and S4, determining that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as the preset values.
The PCB design has capacitors with various capacitance values, the capacitors with different capacitance values are required to be uniformly distributed around the pins for the chip according to the number and the capacitance values of the capacitors, the pin number of the chip, the layout space and the like, and the closer the capacitors are to the pins of the chip, the better the capacitors are. But placing capacitors around its pins is required around tens of chips on a server motherboard. In the prior art, the capacitors with different capacitance values around the chip can be highlighted into different colors only on the PCB, different power networks are highlighted into different colors, and whether a certain amount of capacitors exist around each pin of the chip is compared one by one. Different colors identify different electricity usage networks. The manual inspection quantity and the capacitance value one by one are time-consuming and labor-consuming, the inspection efficiency is low, the accuracy is not high, the poor capacitance filtering effect can be caused in the later period, the problem is difficult to solve, and the design quality of the whole system is influenced.
The invention can avoid a great deal of time waste caused by careless omission and manual inspection during the design of PCB engineers, and can avoid the phenomenon that the capacitor is arranged farther and the capacitance value is not uniformly distributed. By writing the twist, the PCB design reliability is improved, meanwhile, the PCB design efficiency is greatly improved, and the time and the labor cost are saved.
Determining all first capacitors in a preset range of pins on the outermost layer of the chip, and acquiring the positions and the sizes of the first capacitors. All capacitances in the range of 200 mils around the outermost pin of the chip are obtained from the selected chip, and for convenience of description, the capacitances are referred to as first capacitances, including the capacitance of the TOP layer and the capacitance of the bottom layer. And acquiring the layer of the first capacitor and the capacitance value of the first capacitor.
And acquiring coordinates of all power supply pins of the chip, and determining the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius.
And determining second capacitors of the first capacitors in the detection range, and judging whether the number and the size of the second capacitors are the same as a preset value. And (3) calling the first capacitor in the detection range as a second capacitor, and judging whether capacitors with preset capacitance values and quantity exist in the detection range of each power supply pin.
And determining that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as a preset value.
In some embodiments, the method further comprises: judging whether a second capacitor exists in the detection range of the plurality of power supply pins at the same time; and responding to the fact that the second capacitor exists in the detection range of the plurality of power supply pins at the same time, and detecting whether the second capacitor is a filter capacitor.
In some embodiments, the detecting whether the second capacitance is a filter capacitance comprises: judging whether the second capacitor is connected with the nearest power supply pin or not; and in response to the second capacitor being connected to the nearest supply pin, considering the second capacitor to be a filter capacitor of the nearest supply pin. The second capacitor may not be connected to the nearest supply pin, but for reasons of layout rationality the user may be prompted to reset the position of the second capacitor when it is not connected to the nearest supply pin.
In some embodiments, the method further comprises: and responding to the fact that the second capacitor is not connected with a power supply pin, giving an alarm and highlighting the second capacitor.
It should be particularly noted that, the steps in the embodiments of the method for checking the capacitor around the chip can be mutually intersected, replaced, added and deleted, so that these reasonable permutation and combination transformations should also fall into the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
In view of the above object, a second aspect of the embodiments of the present invention provides a system for inspecting a capacitance around a chip. As shown in fig. 2, the system 200 includes the following modules: the first acquisition module is configured to determine all first capacitors in a preset range of pins at the outermost layer of the chip and acquire the positions and sizes of the first capacitors; the second acquisition module is configured to acquire coordinates of all power supply pins of the chip, and determine the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius; the judging module is configured to determine a second capacitor of the first capacitor in the detection range, and judge whether the number and the size of the second capacitors are the same as a preset value; and the determining module is configured to determine that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as preset values.
In some embodiments, the system further comprises a detection module configured to: judging whether a second capacitor exists in the detection range of the plurality of power supply pins at the same time; and responding to the fact that the second capacitor exists in the detection range of the plurality of power supply pins at the same time, and detecting whether the second capacitor is a filter capacitor.
In some embodiments, the detection module is further configured to: judging whether the second capacitor is connected with the nearest power supply pin or not; and in response to the second capacitor being connected to the nearest supply pin, considering the second capacitor to be a filter capacitor of the nearest supply pin.
In some embodiments, the system further comprises an alert module configured to: and responding to the fact that the second capacitor is not connected with a power supply pin, giving an alarm and highlighting the second capacitor.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, determining all first capacitors in a preset range of pins on the outermost layer of the chip, and acquiring the positions and sizes of the first capacitors; s2, obtaining coordinates of all power supply pins of the chip, and determining the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius; s3, determining second capacitors of the first capacitors in the detection range, and judging whether the number and the size of the second capacitors are the same as a preset value or not; and S4, determining that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as preset values.
In some embodiments, the steps further comprise: judging whether a second capacitor exists in the detection range of the plurality of power supply pins at the same time; and responding to the fact that the second capacitor exists in the detection range of the plurality of power supply pins at the same time, and detecting whether the second capacitor is a filter capacitor.
In some embodiments, the detecting whether the second capacitance is a filter capacitance comprises: judging whether the second capacitor is connected with the nearest power supply pin or not; and in response to the second capacitor being connected to the nearest supply pin, considering the second capacitor to be a filter capacitor of the nearest supply pin.
In some embodiments, the method further comprises: and responding to the fact that the second capacitor is not connected with a power supply pin, giving an alarm and highlighting the second capacitor.
Fig. 3 is a schematic diagram of a hardware structure of an embodiment of the computer apparatus for checking capacitance around a chip according to the present invention.
Taking the device shown in fig. 3 as an example, the device includes a processor 301 and a memory 302.
The processor 301 and the memory 302 may be connected by a bus or other means, such as the bus connection in fig. 3.
The memory 302 is a non-volatile computer-readable storage medium, and can be used for storing non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for checking the chip periphery capacitance in the embodiment of the present application. The processor 301 executes various functional applications of the server and data processing, i.e., implements a method of checking the capacitance around the chip, by running a nonvolatile software program, instructions, and modules stored in the memory 302.
The memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created by use of a method of checking capacitance around a chip, or the like. Further, the memory 302 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 302 optionally includes memory located remotely from processor 301, which may be connected to a local module via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
One or more computer instructions 303 corresponding to a method of checking the capacitance around the chip are stored in the memory 302 and when executed by the processor 301 perform the method of checking the capacitance around the chip in any of the method embodiments described above.
Any embodiment of the computer apparatus for performing the method for checking the capacitance around the chip may achieve the same or similar effects as any corresponding embodiment of the method.
The present invention also provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs a method of checking a chip periphery capacitance.
Fig. 4 is a schematic diagram of an embodiment of a computer storage medium for checking the capacitance around the chip according to the present invention. Taking the computer storage medium as shown in fig. 4 as an example, the computer readable storage medium 401 stores a computer program 402 which, when executed by a processor, performs the method as described above.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for checking the capacitance around the chip can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims (10)

1. A method of inspecting capacitance around a chip, comprising the steps of:
determining all first capacitors in a preset range of pins on the outermost layer of a chip, and acquiring the positions and the sizes of the first capacitors;
obtaining coordinates of all power supply pins of the chip, and determining the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius;
determining second capacitors of the first capacitors in the detection range, and judging whether the number and the size of the second capacitors are the same as a preset value or not; and
and determining that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as a preset value.
2. The method of claim 1, further comprising:
judging whether a second capacitor exists in the detection range of the plurality of power supply pins at the same time; and
and responding to the condition that a second capacitor exists in the detection range of a plurality of power supply pins at the same time, and detecting whether the second capacitor is a filter capacitor.
3. The method of claim 2, wherein the detecting whether the second capacitance is a filter capacitance comprises:
judging whether the second capacitor is connected with the nearest power supply pin or not; and
and in response to the second capacitor being connected to the nearest power supply pin, considering the second capacitor as a filter capacitor of the nearest power supply pin.
4. The method of claim 1, further comprising:
and responding to the fact that the second capacitor is not connected with a power supply pin, giving an alarm and highlighting the second capacitor.
5. A system for inspecting capacitance around a chip, comprising:
the first acquisition module is configured to determine all first capacitors in a preset range of pins at the outermost layer of the chip and acquire the positions and sizes of the first capacitors;
the second acquisition module is configured to acquire coordinates of all power supply pins of the chip, and determine the detection range of the power supply pins by taking the coordinates of the power supply pins as a center and taking a preset interval as a radius;
the judging module is configured to determine a second capacitor of the first capacitor in the detection range, and judge whether the number and the size of the second capacitors are the same as a preset value; and
and the determining module is configured to determine that the power supply pins meet the requirements in response to the fact that the number and the size of the second capacitors are the same as a preset value.
6. The system of claim 5, further comprising a detection module configured to:
judging whether a second capacitor exists in the detection range of the plurality of power supply pins at the same time; and
and responding to the condition that a second capacitor exists in the detection range of a plurality of power supply pins at the same time, and detecting whether the second capacitor is a filter capacitor.
7. The system of claim 6, wherein the detection module is further configured to:
judging whether the second capacitor is connected with the nearest power supply pin or not; and
and in response to the second capacitor being connected to the nearest power supply pin, considering the second capacitor as a filter capacitor of the nearest power supply pin.
8. The system of claim 5, further comprising an alert module configured to:
and responding to the fact that the second capacitor is not connected with a power supply pin, giving an alarm and highlighting the second capacitor.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225830A (en) * 1991-02-26 1993-07-06 Mitutoyo Combination optical and capacitive absolute position apparatus and method
CN101996268A (en) * 2009-08-20 2011-03-30 鸿富锦精密工业(深圳)有限公司 Circuit wiring system and method
CN102253780A (en) * 2011-07-22 2011-11-23 苏州瀚瑞微电子有限公司 Method for positioning two-dimensional capacitance sensor
CN104596451A (en) * 2013-10-31 2015-05-06 约翰内斯·海德汉博士有限公司 Position measuring device
CN109932488A (en) * 2019-03-18 2019-06-25 东莞市荣旭自动化科技有限公司 Capacitor appearance detecting method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225830A (en) * 1991-02-26 1993-07-06 Mitutoyo Combination optical and capacitive absolute position apparatus and method
CN101996268A (en) * 2009-08-20 2011-03-30 鸿富锦精密工业(深圳)有限公司 Circuit wiring system and method
CN102253780A (en) * 2011-07-22 2011-11-23 苏州瀚瑞微电子有限公司 Method for positioning two-dimensional capacitance sensor
CN104596451A (en) * 2013-10-31 2015-05-06 约翰内斯·海德汉博士有限公司 Position measuring device
CN109932488A (en) * 2019-03-18 2019-06-25 东莞市荣旭自动化科技有限公司 Capacitor appearance detecting method

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