CN114141878A - Power MOSFET device and preparation method thereof - Google Patents

Power MOSFET device and preparation method thereof Download PDF

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Publication number
CN114141878A
CN114141878A CN202111499851.1A CN202111499851A CN114141878A CN 114141878 A CN114141878 A CN 114141878A CN 202111499851 A CN202111499851 A CN 202111499851A CN 114141878 A CN114141878 A CN 114141878A
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metal
groove
opening
metal plug
dielectric layer
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周源
胡磊
王超
杨棂鑫
邢岳
王振达
罗胡瑞
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Beijing Yandong Microelectronic Technology Co ltd
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Beijing Yandong Microelectronic Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The application relates to the technical field of semiconductors and discloses a power MOSFET device and a preparation method thereof. The power MOSFET device includes: a semiconductor substrate; a body region extending from the surface of the semiconductor substrate into the semiconductor substrate, and a doped region formed in the body region; the body region includes a first region as a cell region, and a second region located around the first region; the first groove and the second groove penetrate through the first area, the third groove penetrates through the second area, the depth of the second groove is smaller than that of the first groove, and the inner walls of the first groove and the second groove are both provided with gate dielectric layers; the first metal plug is positioned in the first groove, the second metal plug is positioned in the second groove, the third metal plug is positioned in the third groove, and a Schottky junction is formed between the second metal plug and the bottom of the second groove. The power MOSFET device can reduce the forward conduction voltage and improve the frequency characteristic of the device.

Description

Power MOSFET device and preparation method thereof
Technical Field
The application relates to the technical field of semiconductors, in particular to a power MOSFET device and a preparation method thereof.
Background
A Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) is a Field Effect Transistor that can be widely used in analog circuits and digital circuits. The power MOSFET refers to a MOSFET device in a power output stage, and generally has an operating current greater than 1A. The mainstream power MOSFET types on the market at present mainly comprise Planar, Trench, Lateral, Super Junction and Advanced Trench type MOSFETs with different internal structures formed due to technical change.
Trench (Trench) MOSFETs are power MOSFETs with very high performance-to-cost ratio, such as VDMOSFETs with U-shaped trenches (Vertical Double Diffused Metal-Oxide-Semiconductor Field Effect transistors), which have the advantages of bipolar transistors and common MOS devices, especially negative temperature coefficients, and do not have the problem of secondary breakdown of bipolar power, and therefore, U-shaped Trench VDMOSFETs (UMOS for short) are ideal power devices for both switching and linear applications.
However, the forward conduction voltage drop of the conventional UMOS is generally 0.7V to 0.8V, and the high-frequency rectifying and switching circuit and the protection circuit often require a lower forward conduction voltage drop in special application scenarios such as low voltage and large current, while the conventional UMOS cannot meet the requirements in the special application scenarios.
Disclosure of Invention
The embodiment of the application provides a power MOSFET device and a preparation method thereof, so that the forward conduction voltage drop of UMOS is reduced, and the use requirements under certain special application scenes can be met.
In some embodiments, a power semiconductor device includes:
a semiconductor substrate;
a body region extending from the surface of the semiconductor substrate into the semiconductor substrate, and a doped region formed in the body region; the body region includes a first region as a cell region, and a second region located around the first region;
the first groove and the second groove penetrate through the first area, the third groove penetrates through the second area, the depth of the second groove is smaller than that of the first groove, and the inner wall of the first groove and the inner wall of the third groove are both provided with gate dielectric layers;
the first metal plug is positioned in the first groove, the second metal plug is positioned in the second groove, the third metal plug is positioned in the third groove, and a Schottky junction is formed between the second metal plug and the bottom of the second groove;
a first interlayer dielectric layer covering the body region, wherein openings corresponding to the first groove, the second groove and the third groove are formed in the first interlayer dielectric layer; the first metal plug, the second metal plug and the third metal plug extend into the corresponding openings respectively, and the tops of the first metal plug, the second metal plug and the third metal plug are at least not lower than the surface of the first interlayer dielectric layer;
and the second interlayer dielectric layer is positioned on the surface of the first interlayer dielectric layer, covers the first groove and is provided with a leading-out port so as to expose the second metal plug and the third metal plug respectively.
In some embodiments, a method of manufacturing a power semiconductor device includes:
forming a body region in the semiconductor substrate, forming a doped region in the body region and a first interlayer dielectric layer covering the body region, wherein the body region comprises a first region serving as a cellular region and a second region located around the first region, and the first interlayer dielectric layer is provided with a first opening and a second opening corresponding to the first region and a third opening corresponding to the second region;
etching the semiconductor substrate corresponding to the first opening and the third opening to form a first groove penetrating through the first area and a third groove penetrating through the second area;
forming a grid dielectric layer on the inner wall of the first groove and the inner wall of the third groove;
etching the semiconductor substrate corresponding to the second opening to form a second groove penetrating through the first area;
depositing metal into the first groove, the second groove and the third groove respectively; enabling the metal in the second groove to react with the semiconductor substrate to form a Schottky junction; carrying out back etching or planarization treatment on the deposited metal to respectively and correspondingly form a first metal plug, a second metal plug and a third metal plug in the first groove, the second groove and the third groove;
forming a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer;
and etching the second interlayer dielectric layer to form a lead-out opening, and exposing the second metal plug and the third metal plug.
By adopting the power semiconductor device and the preparation method thereof provided by the embodiment of the application, the following technical effects are achieved:
the overlapped part of the trench gate (including the first trench and the third trench) and the body region is a channel region, and the metal plugs (including the first metal plug and the third metal plug) filled in the first trench and the third trench and the gate insulating layer (including the first insulating layer and the second insulating layer) form a capacitor structure. When the trench gate is at a high potential, the channel region is inverted to be in the same conductive type as the source and the drain, and the Schottky junction is in short circuit through the inverted channel to realize the conduction of the drain and the source; when the high potential of the trench gate disappears, the inversion channel also disappears, and the Schottky junction works in the reverse cut-off region to realize the turn-off of the drain and the source. The Schottky junction is used for realizing the conduction or the disconnection of the drain electrode and the source electrode, meanwhile, the forward potential barrier of the Schottky junction is lower than that of a PN junction, only one majority carrier participates in the conduction when the Schottky junction works, the recombination of the carriers does not exist, and the switching speed is higher. Therefore, the integration of the Schottky structure in the UMOS structure can reduce the forward conduction voltage of the UMOS, improve the frequency characteristic of the device, and meet the requirements of a high-frequency rectifying and switching circuit and a protection circuit in special application scenes such as low voltage, large current and the like.
Drawings
Fig. 1 is a schematic structural diagram of a power MOSFET device according to an embodiment of the present application;
fig. 2 to fig. 21 are schematic structural diagrams of a semiconductor device in steps of a method for manufacturing a power MOSFET device according to an embodiment of the present application;
fig. 22 to fig. 26 are schematic diagrams of mask structures in a power MOSFET manufacturing process according to an embodiment of the present application.
Description of reference numerals:
200: a substrate; 300: an epitaxial layer; 400: a body region; 500: a doped region; 600: a first interlayer dielectric layer; 700: a second interlayer dielectric layer; 800: photoresist; 901: a first electrode; 902: a gate electrode; 11: a first trench; 12: a second trench; 13: a third trench; 21: a gate dielectric layer; 31: a first metal plug; 32: a second metal plug; 33: a third metal plug; 41: a first metal layer; 42: a second metal layer; 43: a third metal layer; 50: a Schottky junction; 61: a first opening; 62: a second opening; 63: a third opening; 71. a first photoresist opening; 72. a second photoresist opening; 73. a third photoresist opening.
Detailed Description
So that the manner in which the features and elements of the present embodiments can be understood in detail, a more particular description of the embodiments, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures may be shown to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims of the embodiments of the application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion.
In the embodiment of the present application, the power MOSFET device and the method for manufacturing the same are exemplarily described as being applied to UMOS, but the power MOSFET device and the method for manufacturing the same provided in the embodiment of the present application are not limited to be substantial, and the power MOSFET device and the method for manufacturing the same may also be applied to other types of power MOSFET devices having U-shaped trenches.
Fig. 1 is a schematic structural diagram of a power MOSFET device according to an embodiment of the present application. As shown in connection with fig. 1, a power MOSFET device includes:
a semiconductor substrate;
a body region 400 extending from a surface of the semiconductor substrate into the semiconductor substrate, the body region 400 including a first region as a cell region (Main cell region) and a second region as a gate region, the second region being located around the first region;
a doped region 500 formed within the body region 400;
the first groove 11 and the second groove 12 which penetrate through the first area and the third groove 13 which penetrates through the second area, the depth of the second groove 12 is smaller than that of the first groove 11, and the inner wall of the first groove 11 and the inner wall of the third groove 13 are both provided with a grid dielectric layer 21; the depths of the first trench 11, the second trench 12 and the third trench 13 are all greater than the thickness of the body region 400;
a first metal plug 31 located in the first trench 11, a second metal plug 32 located in the second trench 12, and a third metal plug 33 located in the third trench 13, wherein the second metal plug 32 and the bottom of the second trench 12 form a schottky junction;
a first interlayer dielectric layer 600 covering the body region 400, the first interlayer dielectric layer 600 being provided with openings corresponding to the first trench 11, the second trench 12, and the third trench 13, respectively; the first metal plug 31, the second metal plug 32 and the third metal plug 33 respectively extend into the corresponding openings, and the tops of the first metal plug 31, the second metal plug 32 and the third metal plug 33 are at least not lower than the surface of the first interlayer dielectric layer 600;
and a second interlayer dielectric layer 700 located on the surface of the first interlayer dielectric layer 600, wherein the second interlayer dielectric layer 700 covers the first trench 11, and a lead-out opening is formed in the second interlayer dielectric layer 700 to expose the second metal plug 32 and the third metal plug 33 respectively.
In a particular application, the choice of semiconductor substrate is also different for different types of power MOSFET devices. For UMOS, an epitaxial wafer may be employed as a semiconductor substrate; for other types of power MOSFET devices the use of a single wafer as the semiconductor substrate is not excluded. The epitaxial wafer may be commercially available, or may be obtained by depositing an epitaxial layer on the surface of a substrate by a process such as CVD (Chemical Vapor Deposition) or PVD (Physical Vapor Deposition).
The thickness of the gate dielectric layer 21 is not specifically limited in the embodiment of the present application, and those skilled in the art may configure the appropriate thickness of the gate dielectric layer 21 according to the threshold voltage requirement of the device. For example, a 250 angstrom gate dielectric layer 21 may be used.
It should be noted that, in the embodiment, UMOS is taken as an example for description, the first trench 11 located in the Main Cell area and the third trench 13 located in the Gate area are used together to form a trench Gate, so that, based on an achievable layout, the second trenches 12 are located in an area defined by the first trench 11 and are arranged in an array in the area; the third groove 13 is located outside the area defined by the first groove 11 and communicates with the first groove 11. In other layout structures, various groove arrangement modes can be set according to the groove types and functions.
The overlapped part of the trench gate and the body region 400 is a channel region, the metal plugs (including the first metal plug 31 and the third metal plug 33) filled in the first trench 11 and the third trench 13 and the gate dielectric layer 21 form a capacitor structure, when the trench gate is at a high potential, the channel region is inverted to be in a conductive type same as that of the source and the drain, and the inverted channel short-circuits the Schottky junction 50 to realize the conduction of the drain and the source; when the high potential of the trench gate disappears, the inversion channel also disappears, and the schottky junction 50 works in the reverse cut-off region to realize the turn-off of the drain and the source. The Schottky junction 50 is used for realizing the conduction or the disconnection of the drain electrode and the source electrode, meanwhile, the forward barrier of the Schottky junction 50 is lower than that of a PN junction, only one majority carrier participates in the conduction when the Schottky junction 50 works, the recombination of the carriers does not exist, and the switching speed is higher. Therefore, integrating the schottky junction 50 in the UMOS structure can reduce the forward on-state voltage of the UMOS, and improve the frequency characteristics of the device, so as to meet the requirements of the high-frequency rectifying and switching circuit and the protection circuit in special application scenarios such as low voltage, large current, and the like.
In addition, different from the properties of a common doped polysilicon semiconductor, the first metal plug 31 is arranged in the first trench 11, the third metal plug 33 is arranged in the third trench 13, so that the effects of carrier offset, depletion and the like can not occur when bias voltage is applied, the grid voltage resistance is stable, the grid charge is low, and the response speed is high; the resistance of metal is low, the resistance of a grid electrode is low, the reaction is faster during alternating signals, and the switching time can be effectively reduced; the process cost of doped polysilicon deposition is high, the equipment maintenance cost is high, the polysilicon deposition process can be omitted in the embodiment of the application, and the process cost is reduced.
The first metal plug 31 may be a "U" shaped solid structure matching with the shape of the trench; or the hollow structure can be a U-shaped hollow structure, but the side wall of the hollow structure is ensured to be continuous. Also, as for the aforementioned second metal plugs 32 and third metal plugs 33, a "U" -shaped hollow structure or a "U" -shaped solid structure (non-hollow structure) may be employed.
In a specific application, in the case where the first metal plug 31, the second metal plug 32, and the third metal plug 33 are hollow structures, although a very small amount of limiting current capability is lost, the respective basic functions can be ensured. Compared with a metal plug with a solid structure, the metal plug with a hollow structure can shorten the process, reduce the stress of the grooves (especially the first groove 11 and the third groove 13) on the wafer, and avoid the wafer from warping to a certain extent.
In the case where the first metal plug 31, the second metal plug 32, and the third metal plug 33 are hollow structures, the first metal plug 31, the second metal plug 32, and the third metal plug 33 independently include a first metal layer 41 and a second metal layer 42, respectively; the first metal layer 41 covers the gate dielectric layer 21 and the inner wall of the second trench 12 and extends to the first interlayer dielectric layer 600; the second metal layer 42 is connected with one end of the first metal layer 41 far away from the semiconductor substrate; the upper surface of the second metal layer 42 is flush with the upper surface of the first interlayer dielectric layer 600; the first metal layer 41 and the second metal layer 42 define a receiving cavity, which is a hollow cavity.
In the case where the first metal plug 31, the second metal plug 32, and the third metal plug 33 are solid structures, the first metal plug 31, the second metal plug 32, and the third metal plug 33 independently include a first metal layer 41 and a second metal layer 42, respectively; the first metal layer 41 covers the gate dielectric layer 21 and the inner wall of the second trench 12 and extends to the first interlayer dielectric layer 600; the second metal layer 42 is connected with one end of the first metal layer 41 far away from the semiconductor substrate; the upper surface of the second metal layer 42 is flush with the upper surface of the first interlayer dielectric layer 600; the first metal layer 41 and the second metal layer 42 define a receiving cavity, which is filled with the third metal layer 43.
In a particular application, the material forming the first metal layer 41 may be Ti (titanium) or a Ti/TiN stack; the material forming the second metal layer 42 may be TiN; the material forming the third metal layer 43 may be W (tungsten).
In the case where the first metal plug 31, the second metal plug 32, and the third metal plug 33 are hollow structures, the second metal layer 42 may function as an adhesion layer to increase metal adhesion and a barrier layer to prevent metal diffusion. For the second metal plug 31, the first metal layer 41 may form a silicide with the epitaxial layer 300 of the semiconductor substrate, which is the schottky junction 50.
In the case where the first metal plug 31, the second metal plug 32, or the third metal plug 33 is a solid structure, the third metal layer 43 may increase the conductive capability of the first metal plug 31, the second metal plug 32, or the third metal plug 33, which is equivalent to filling the hollow structure with the third metal layer 43. At this time, the second metal layer 42 may wrap the third metal layer 43, blocking the third metal layer 43 from diffusing.
The person skilled in the art can select the hollow structure or the solid structure according to the actual situation, and the embodiment of the present application is not limited in this respect.
In the specific implementation process, the wafer warpage can be effectively improved on the premise of ensuring that the power MOSFET device functions normally, by controlling the filling degree of the first metal layer 41 in the first trench 11 and the third trench 13, especially the thickness of the first metal layer 41 relative to the bottom of the trenches. Practice proves that when the thickness of the first metal layer 41 along the depth direction of the first groove 11 and the third groove 13 is 1/6-2/3 of the depth of the grooves, the wafer warpage can be reduced; for example, the thickness of the first metal layer 41 in the trench depth direction of the first trench 11 and the third trench 13 is the trench depth 1/6, 1/5, 1/3, 1/2 or 2/3, especially 1/3 to 1/2, so that wafer warpage can be effectively avoided. In actual production, a device with stronger hole filling capability such as SIP (Self-Ionized Physical Vapor Deposition), IMP (Ionized Metal Physical Vapor Deposition), RFPVD (Radio Frequency Physical Vapor Deposition) and the like can be selected to control the filling degree of the first Metal layer 41 to the groove, so as to achieve the above effects, thereby facilitating subsequent wafer back thinning and back metallization, reducing the risk of wafer cracking, and significantly improving the warpage problem even after the wafer back is thinned, thereby reducing the probability of wafer fragment thinning. In addition, for a single chip, the reliability of the device is actually improved to some extent because the problem of stress is alleviated.
The width of the bottom opening of the lead-out port of the second interlayer dielectric layer 700 is greater than the widths of the top openings of the second metal plug 32 and the third metal plug 33, so that the first electrode 901 can be in contact with the second metal plug 32 and not in contact with the first metal plug 31, and the gate 902 can be in contact with the third metal plug 33, thereby reducing the requirements of photoetching and etching the second interlayer dielectric layer 700 on precision; and the photoetching pattern size of the leading-out port is larger than 250nm under the general condition, and the photoetching equipment using a KrF light source can be omitted, so that the processing difficulty is reduced.
Further, the width of the upper end of the lead-out opening is larger than or equal to the width of the lower end of the lead-out opening, namely, the longitudinal section of the opening is in an inverted trapezoid shape, and the upper bottom (shorter side) of the trapezoid is relatively closer to the semiconductor substrate. This may facilitate subsequent metal filling.
A first front side top metal and a second front side top metal are formed on the upper surface of the second interlayer dielectric layer 700, wherein the first front side top metal covers the first metal plug 31 and the second metal plug 32, and the second front side top metal covers the third metal plug 33. For a MOSFET, the first front side top layer metal can serve as the source and the second front side top layer metal as the gate 902.
The surface of the first front surface top layer metal and the surface of the second front surface top layer metal can be deposited with an insulating protective layer, and the insulating protective layer is etched to form a pressure welding area.
And grinding the back surface of the power MOSFET device to metalize the back surface and serve as a second electrode. For a MOSFET, this electrode is the drain.
Fig. 2 to fig. 19 are schematic structural diagrams of a MOSFET device in steps of a method for manufacturing a power MOSFET device according to an embodiment of the present application; fig. 20 to 24 are schematic views of mask structures in the process of manufacturing a power MOSFET device.
As shown in fig. 2, the semiconductor substrate includes a substrate 200 and an epitaxial layer 300 on a surface of the substrate 200.
The parameters of the substrate 200 and the epitaxial layer 300 are not specifically limited in the embodiment of the present application, and those skilled in the art may change the parameters of the substrate 200, such as resistivity, epitaxial thickness, and crystal orientation, as needed. For example, a phosphorus doped substrate 200 having a resistivity of less than 0.02 Ω cm, a <100> crystal orientation, a resistivity of greater than 0.1 Ω, and a phosphorus doped epitaxy thickness of greater than 2 μm may be used.
As shown in fig. 3 to 6, a body region 400 is formed in a semiconductor substrate, a doped region 500 is formed in the body region 400, and a first interlayer dielectric layer 600 covers the body region 400, wherein the body region 400 includes a first region serving as a cell region and a second region located around the first region, and the first interlayer dielectric layer 600 is provided with a first opening 61 and a second opening 62 corresponding to the first region, and a third opening 63 corresponding to the second region.
As shown in fig. 3, the semiconductor substrate is doped to form a body region 400. Body region 400 may be formed by implanting impurities into epitaxial layer 300 and then annealing. In particular practice, the junction depth of the body region 400 is also increased by the subsequent thermal processing, so that the annealing after ion implantation is not an essential step, and the annealing process can be selected and adjusted according to actual process conditions. The doping impurities and the doping concentration used for doping the epitaxial layer 300 can be set according to actual requirements. For example, a P-type impurity such as boron on the order of E12 or more may be implanted into epitaxial layer 300 to form a P-type doped region as body region 400. The body region 400 extends from the upper surface of the substrate 200 to a certain depth into the substrate 200, and those skilled in the art can flexibly adjust the body region according to the parameter performance requirements of the device.
As shown in FIG. 4, E15/cm was implanted into body region 4002The N-type impurity ions with more than an order of magnitude are annealed to form the doped region 500, the doped region 500 extends from the upper surface of the body region 400 to a set depth, and a person skilled in the art can flexibly adjust the set depth according to the parameter performance requirement of the device, so that the set depth is smaller than the depth of the body region 400. A first interlayer dielectric layer 600 is deposited On the upper surface of the doped region 500, the first interlayer dielectric layer 600 may be obtained by various known silicon oxide growth methods such as PECVD (Plasma Enhanced Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), SACVD (Sub Atmospheric Chemical Vapor Deposition), thermal oxidation, SOG (Spin On Glass), etc., and a person skilled in the art may flexibly select a Deposition method and a thickness according to different application scenarios.
Coating a photoresist 800 on the first interlayer dielectric layer 600, performing photolithography by using a first mask as shown in fig. 22 to form the photoresist 800 having a shape as shown in fig. 5, and etching the first interlayer dielectric layer 600 by using the photoresist 800 having the shape as a mask to form the first interlayer dielectric layer 600 having the shape as shown in fig. 5, wherein the first interlayer dielectric layer 600 is provided with a first opening 61 and a second opening 62 corresponding to the first region, and a third opening 63 corresponding to the second region; the first opening 61 is used to locate the first groove 11, the second opening 62 is used to locate the second groove 12, and the third opening is used to locate the third groove 13.
The first mask lithography and etching of the first interlayer dielectric layer 600 is the finest patterning step in the overall power MOSFET device, and typically a KrF device using a 248nm light source or other devices using shorter wavelength light sources are used.
After etching the first interlayer dielectric layer 600, the photoresist 800 is removed, and the patterned first interlayer dielectric layer 600 as shown in fig. 6 is formed, and the patterned first interlayer dielectric layer 600 is used as Hard Mask for the subsequent self-aligned etching of silicon.
As shown in fig. 7, the semiconductor substrate corresponding to the first opening 61 and the third opening 63 is etched to form the first trench 11 penetrating the first region and the third trench 13 penetrating the second region.
Firstly, a photoresist 800 is coated on the first interlayer dielectric layer 600, and a second mask as shown in fig. 23 is used for photoetching to form a first photoresist pattern of the first interlayer dielectric layer 600 as shown in fig. 7, wherein the first photoresist pattern covers all regions except for a region where a trench gate structure (including the first trench 11 and the third trench 13) needs to be formed, a first photoresist opening 71 and a second photoresist opening 72 are respectively arranged in the regions of the first photoresist pattern corresponding to the first opening 61 and the third opening 63, the width of the first photoresist opening 71 is greater than that of the first opening 61, and the width of the second photoresist opening 72 is greater than that of the third opening 61. Then, the semiconductor substrate corresponding to the first opening 61 and the third opening 63 is etched by using the first photoresist pattern and the first interlayer dielectric layer 600 as masks, so as to form a first trench 11 penetrating through the first region and a third trench 13 penetrating through the second region as shown in fig. 7. The photoresist is then removed.
In a specific application, the depth of the first trench 11 and the third trench 13 is required to be greater than the thickness of the body region 400, so that the first trench 11 and the third trench 13 extend into the epitaxial layer 300 of the semiconductor substrate through the body region 400.
In the process of forming the first trench 11 and the third trench 13, the selection ratio of silicon to the photoresist 800 and the first interlayer dielectric layer 600 is ensured by selecting etching conditions, and silicon etching is performed in the region not covered by the photoresist 800 or the first interlayer dielectric layer 600, so that self-aligned etching is realized.
The width of the first photoresist opening 71 is larger than that of the first opening 61, and the width of the second photoresist opening 72 is larger than that of the third opening 61, so that the requirement on the precision of a photoetching machine is reduced, and meanwhile, the alignment redundancy is improved.
As shown in fig. 8, a gate dielectric layer 21 is formed on the inner wall of the first trench 11 and the inner wall of the third trench 13.
The gate dielectric layer 21 is grown on the inner wall of the first trench 11 and the inner wall of the third trench 13 by thermal oxidation, and a person skilled in the art can set the thickness of the gate dielectric layer 21 according to the threshold voltage requirement of the semiconductor power device, for example, a gate dielectric layer 21 with a thickness of 250 angstroms can be used.
Referring to fig. 9, the semiconductor substrate corresponding to the second opening 62 is etched to form a second trench 12 penetrating the first region.
Firstly, a photoresist 800 is coated on the first interlayer dielectric layer 600, a third mask as shown in fig. 24 is used for photoetching, a second photoresist pattern as shown in fig. 9 is formed on the first interlayer dielectric layer 600, the second photoresist pattern covers all the area except the area where the second trench 12 needs to be formed, a third photoresist opening 73 is formed in the area of the second photoresist pattern corresponding to the second opening 62, and the width of the third photoresist opening 73 is greater than that of the second opening 62. Then, the semiconductor substrate corresponding to the second opening 62 is etched by using the second photoresist pattern and the first interlayer dielectric layer 600 as a mask, so as to form a second trench 12 penetrating through the first region as shown in fig. 9. The photoresist is then removed.
The width of the third photoresist opening 73 is greater than the width of the second opening 62, reducing the requirements on the lithography machine while increasing the redundancy of the overlay.
The depth of the second trench 12 is greater than the thickness of the body region 400, so that the second trench 12 penetrates through the body region 400 and extends into the epitaxial layer 300 of the semiconductor substrate; the depth of the second trench 12 is smaller than the depth of the first trench 11 or the third trench 13.
In the process of etching the second trench 12, the selection ratio of silicon to the photoresist 800 and the first interlayer dielectric layer 600 is ensured by selecting etching conditions, and silicon etching is performed in the region not covered by the photoresist 800 or the first interlayer dielectric layer 600, so that self-aligned etching is realized.
As shown in fig. 10 to 14, metal is deposited into the first trench 11, the second trench 12, and the third trench 13, respectively; forming a schottky junction 50 by reacting the metal in the second trench 12 with the semiconductor substrate by rapid thermal annealing or alloying; and the deposited metal is etched back or planarized to form a first metal plug 31, a second metal plug 32 and a third metal plug 33 in the first trench 11, the second trench 12 and the third trench 13, respectively.
In fig. 10 to 14, taking the first metal layer 41 as a Ti or Ti/TiN stack, the second metal layer 42 as TiN, and the third metal layer 43 as W as an example, a process of forming the first metal plug 31, the second metal plug 32, and the third metal plug 33 from the first metal layer 41, the second metal layer 42, and the third metal layer 43 will be exemplarily described.
Referring to fig. 10, a first metal layer 41 is formed, and the first metal layer 41 covers the gate dielectric layer 21 and the inner wall of the second trench 12 and extends into the opening of the first interlayer dielectric layer 60; the first metal layer 41 covers the gate dielectric layer 21 of the first trench 11, a containing cavity may be defined in the first trench 11, the first metal layer 41 covers an inner wall of the second trench 12, a containing cavity may be defined in the second trench 12, the first metal layer 41 covers the gate dielectric layer 21 of the third trench 13, and a containing cavity may be defined in the third trench 13. Then, a third metal layer 43 is formed on the first metal layer 41, so that the third metal layer 43 fills the accommodating cavities in the first trench 11, the second trench 12, and the third trench 13.
Further, in the process of forming the first metal layer 41, the thickness of the first metal layer 41 in the direction of the trench depth of the first trench 11 and the third trench 13 may be 1/6 to 2/3 of the trench depth. Thus, by controlling the filling degree of the first metal layer 41 to the first trench 11 and the third trench 13, especially the thickness of the first metal layer 41 relative to the bottom of the trenches, the wafer warpage can be effectively improved on the premise of ensuring the normal realization of the function of the power MOSFET device; in addition, for a single chip, the reliability of the device is actually improved to some extent because the problem of stress is alleviated. Specifically, devices with stronger hole filling capability such as SIP, IMP, RFPVD, etc. may be selected to control the filling degree of the first metal layer 41 to the first trench 11 and the third trench 13, so as to achieve the above filling effect.
The bottom of the second trench 12 is subjected to a rapid thermal anneal or alloying process, which causes the second trench 12 to react the metal in the second trench 12 with the semiconductor substrate to form a schottky junction 50 as shown in fig. 11.
The third metal layer 43 is etched back so that the upper surface of the third metal layer 43 is lower than the surface of the first interlayer dielectric layer 600, thereby forming the structure shown in fig. 12.
Referring to fig. 13, a second metal layer 42 is formed at an end of the first metal layer 41 away from the semiconductor substrate, the top of the second metal layer 42 is at least not lower than the surface of the first interlayer dielectric layer 600, the first metal layer 41 and the second metal layer 42 define a containing cavity, and the containing cavity is filled with a third metal layer 43.
Wherein the second metal layer 42 includes the third metal layer 43, and the second metal layer 42 can act as a barrier layer to prevent the third metal layer 43 from diffusing.
The second metal layer 42 may be formed using PVD or CVD.
Referring to fig. 14, the second metal layer 42 is etched back or CMP to expose the upper surface of the first interlayer dielectric layer 600. Thus, the first metal plug 31, the second metal plug 32, and the third metal plug 33 are formed by the first metal layer 41, the second metal layer 42, and the third metal layer 43, respectively. The second metal layer 42 serves as a barrier layer for preventing the third metal layer 43 from diffusing, and the third metal layer 43 serves as a filler and a conductive layer, so that the limiting current capacity of the device is improved.
As shown in connection with FIG. 15, use of SiO in addition to thermal oxidation is known2The deposition method forms the second interlayer dielectric layer 700 on the upper surface of the first interlayer dielectric layer 600 and makes the total thickness of the first interlayer dielectric layer 600 and the second interlayer dielectric layer 700 greater than 2000 angstroms. The thicknesses listed here are merely exemplary and do not substantially limit the embodiments of the present application, and those skilled in the art can flexibly adjust the thicknesses according to actual situations.
Referring to fig. 16, the second interlayer dielectric layer 700 is etched to form a lead-out, exposing the second metal plug 31 and the third metal plug 33.
Specifically, the photoresist 800 may be first coated on the second interlayer dielectric layer 700, and then exposed by using a fourth mask as shown in fig. 25, so that the photoresist 800 covers all regions except the metal plugs (the second metal plug 32 and the third metal plug 33) serving as two electrode terminals, and the second interlayer dielectric layer 700 in the region not covered by the photoresist 800 is etched until the upper surfaces of the metal plugs (the second metal plug 32 and the third metal plug 33) are exposed, allowing a portion of the sidewalls of the metal plugs to be exposed by appropriate over-etching, but not exposing the upper surface of the first metal plug 31 in the first trench 11. Under the condition that the second interlayer dielectric layer 700 is ensured to expose the upper surfaces of the second metal plug 32 and the third metal plug 33 and not to expose the first metal plug 31, the lead-out formed on the second interlayer dielectric layer 700 can be larger than the upper surfaces of the second metal plug 32 and the third metal plug 33 (only the upper surface of the first metal plug 31 is not exposed), that is, the opening of the fourth mask can be larger than the upper surfaces of the second metal plug 32 and the third metal plug 33, so that the requirement on a photoetching machine is reduced, and the redundancy of alignment is improved.
Further, in the process of etching the second interlayer dielectric layer 700, the width of the upper end of the lead-out opening is greater than or equal to the width of the lower end of the lead-out opening, that is, the longitudinal section of the opening is in an inverted trapezoid shape, and the upper bottom (shorter side) of the trapezoid is relatively closer to the semiconductor substrate. This facilitates subsequent metal filling.
Referring to fig. 17, a front side top metal is deposited on the upper surface of the second interlayer dielectric layer 700, and the front side top metal is subjected to photolithography and etching by using a fifth mask as shown in fig. 26, so that the front side top metal forms a first front side top metal and a second front side top metal, wherein the first front side top metal covers the first metal plug 31 and the second metal plug 32, and the second front side top metal covers the third metal plug 33. The first front surface top layer metal and the second front surface top layer metal can adopt Ti-TiN-AlCu or AlSiCu. The first front side top-level metal may serve as a first electrode 901 of the power MOSFET device and the second front side top-level metal may serve as a gate 902 of the power MOSFET device.
For a MOSFET, the first electrode 901 (the first front side top layer metal) can serve as a source.
On the basis of the structure shown in fig. 17, the insulating protective layer can be deposited on the surface of the first front surface top metal and the second front surface top metal, and the insulating protective layer is etched to form a pressure welding area; and grinding the back surface of the semiconductor substrate to metalize the back surface to form a second electrode. For a MOSFET, the second electrode is the drain.
The foregoing fig. 10 to 14 exemplarily provide a process of forming the first metal plug 31, the second metal plug 32, and the third metal plug 33. In addition, the first metal plug 31, the second metal plug 32, and the third metal plug 33 may be formed by another process.
The following embodiment provides another process of forming the first metal plug 31, the second metal plug 32, and the third metal plug.
Referring to fig. 18 and 19, taking the first metal layer 41 as a Ti or Ti/TiN stack and the second metal layer 42 as TiN as an example, a process of forming another first metal plug 31, a second metal plug 32, and a third metal plug 33 from the first metal layer 41 and the second metal layer 42 will be exemplarily described. The first metal plug 31, the second metal plug 32 and the third metal plug 33 with hollow structure can be formed by the first metal 41 and the second metal layer 42.
Depositing metal into the first trench 11, the second trench 12 and the third trench 13 respectively, and firstly forming a first metal layer 41, wherein the first metal layer 41 covers the inner walls of the gate dielectric layer 21 and the second trench 12 and correspondingly extends into the opening of the first interlayer dielectric layer 60; forming a second metal layer 42 at one end of the first metal layer 41 far away from the semiconductor substrate, wherein the top of the second metal layer 42 is at least not lower than the surface of the first interlayer dielectric layer 600, and the first metal layer 41 and the second metal layer 42 define an accommodating cavity; the first metal layer 41 in the second trench 12 is reacted with the semiconductor substrate to form a schottky junction 50 by rapid thermal annealing or alloying, resulting in the structure shown in fig. 18.
The deposited second metal layer 42 is etched back or planarized to form the first metal plug 31, the second metal plug 32 and the third metal plug 33 with hollow structure in the first trench 11, the second trench 12 and the third trench 13, respectively, as shown in fig. 19.
In the above process, the second metal layer 42 may be deposited using PVD or CVD; during the etching back or planarization process of the second metal layer 42, the over-polishing amount of the CMP needs to be controlled to prevent the upper surface of the closed metal plug from being damaged.
The first metal plug 31, the second metal plug 32, and the third metal plug 33 of the hollow structure shown in fig. 19 can secure the basic function of the power MOSFET device although a part of the limiting current capability is lost.
Fig. 20 is a structure after forming a second interlayer dielectric layer 700 on the basis of the structure shown in fig. 19; fig. 21 is a structure after forming a first front surface top layer metal and a second front surface top layer metal on the basis of the structure shown in fig. 21. In the foregoing embodiment, the process of forming the second interlayer dielectric layer 700 and the first front side top metal and the second front side top metal has been described in detail, and details are not repeated here.
Fig. 22 to fig. 26 are schematic structural diagrams of a mask provided in the embodiment of the present application.
Fig. 22 is a schematic structural diagram of a first mask according to an embodiment of the present disclosure, and in fig. 22, a dot-shaded area is an area without photoresist protection after photolithography.
Fig. 23 is a schematic structural diagram of a second mask provided in an embodiment of the present application, where in fig. 23, hatched areas are regions protected by photoresist, dotted hatches are regions of trench gates (a first trench and a third trench) in the first mask, and regions without color are all first interlayer dielectric layers.
Fig. 24 is a schematic structural diagram of a third mask according to an embodiment of the present disclosure, in fig. 24, a cross-hatched area is a photoresist-protected area, a dot-hatched area is a second trench area in the first mask, and a non-color area is a first interlayer dielectric layer.
Fig. 25 is a schematic structural view of a fourth mask according to an embodiment of the present disclosure, in fig. 25, a diagonal hatching region is an opening region of the fourth mask, and all regions except the diagonal hatching region are covered with a photoresist.
Grey is SiO retained by the second interlevel dielectric layer2And a covered trench gate conductive plug structure.
Fig. 26 is a schematic structural diagram of a fifth mask provided in this embodiment, in fig. 26, a diagonally shaded area indicates areas of two electrodes, front top metal of the electrode area is covered by photoresist, all areas outside the areas are not protected by the photoresist, the front top metal is etched and removed, and the front top metal is divided into a first front top metal (a left diagonally shaded portion in fig. 26) and a second front top metal (a right diagonally shaded portion in fig. 26), where the first front top metal may be a first electrode, and the second front top metal may be a gate electrode.
It should be understood that the schematic diagrams of the square Cell layout provided in fig. 22 to 26 are only used to illustrate the relative position relationship of each portion, and the shape and size of the Cell area are not limited, and besides, there are various design methods such as stripe cells, diamond cells, and hexagon cells, which are not specifically limited in this embodiment of the present application.
In the description of the present application, the terms "upper", "lower", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of describing the present application but do not require that the present application must be constructed and operated in a specific orientation, and thus, cannot be construed as limiting the present application.
The particular features, structures, materials, or characteristics described in this application may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present application, and that variations, modifications, substitutions and alterations may be made to the above embodiments by those of ordinary skill in the art within the scope of the present application.

Claims (10)

1. A power MOSFET device, comprising:
a semiconductor substrate;
the semiconductor substrate comprises a body region extending from the surface of the semiconductor substrate to the semiconductor substrate and a doped region formed in the body region; the body region includes a first region as a cell region, and a second region located around the first region;
the first groove and the second groove penetrate through the first area, the third groove penetrates through the second area, the depth of the second groove is smaller than that of the first groove, and grid dielectric layers are arranged on the inner wall of the first groove and the inner wall of the third groove;
the first metal plug is positioned in the first groove, the second metal plug is positioned in the second groove, the third metal plug is positioned in the third groove, and a Schottky junction is formed between the second metal plug and the bottom of the second groove;
a first interlayer dielectric layer covering the body region, wherein openings corresponding to the first groove, the second groove and the third groove are formed in the first interlayer dielectric layer; the first metal plug, the second metal plug and the third metal plug extend into the corresponding openings respectively, and the tops of the first metal plug, the second metal plug and the third metal plug are at least not lower than the surface of the first interlayer dielectric layer;
and the second interlayer dielectric layer is positioned on the surface of the first interlayer dielectric layer, covers the first groove, and is provided with a leading-out port so as to expose the second metal plug and the third metal plug respectively.
2. The power MOSFET device of claim 1, wherein the first metal plug, the second metal plug, and the third metal plug each independently comprise:
the first metal layer covers the grid dielectric layer and the inner wall of the second groove and extends to the first interlayer dielectric layer;
the second metal layer is connected with one end, far away from the semiconductor substrate, of the first metal layer;
wherein,
the upper surface of the second metal layer is flush with the upper surface of the first interlayer dielectric layer;
the first metal layer and the second metal layer define a containing cavity, and the containing cavity is a cavity or is filled with a third metal layer.
3. The power MOSFET device of claim 2, wherein the first metal layer has a thickness in a depth direction of the first trench and the third trench of 1/6-2/3 of a trench depth.
4. The power MOSFET device of claim 2, wherein the material forming the first metal layer is Ti or a Ti/TiN stack; the material for forming the second metal layer is TiN; the material forming the third metal layer is W.
5. The power MOSFET device of any of claims 1 through 4, wherein a bottom width of the tap is greater than or equal to a top opening width of the second metal plug and the third metal plug;
the width of the upper end of the leading-out opening is larger than or equal to the width of the lower end of the leading-out opening.
6. A method for manufacturing a power MOSFET device, comprising:
forming a body area in a semiconductor substrate, forming a doped area in the body area and a first interlayer dielectric layer covering the body area, wherein the body area comprises a first area serving as a cellular area and a second area located around the first area, and the first interlayer dielectric layer is provided with a first opening and a second opening corresponding to the first area and a third opening corresponding to the second area;
etching the semiconductor substrate corresponding to the first opening and the third opening to form a first groove penetrating through the first area and a third groove penetrating through the second area;
forming a grid dielectric layer on the inner wall of the first groove and the inner wall of the third groove;
etching the semiconductor substrate corresponding to the second opening to form a second groove penetrating through the first area;
depositing metal into the first trench, the second trench and the third trench, respectively; enabling the metal in the second groove to react with the semiconductor substrate to form a Schottky junction; carrying out back etching or planarization treatment on the deposited metal to respectively and correspondingly form a first metal plug, a second metal plug and a third metal plug in the first groove, the second groove and the third groove;
forming a second interlayer dielectric layer on the upper surface of the first interlayer dielectric layer;
and etching the second interlayer dielectric layer to form a lead-out port and expose the second metal plug and the third metal plug.
7. The method according to claim 6, wherein etching the semiconductor substrate corresponding to the first opening and the third opening to form a first trench penetrating the first region and a third trench penetrating the second region comprises:
forming a first photoresist pattern on the first interlayer dielectric layer, wherein regions of the first photoresist pattern corresponding to the first opening and the third opening are respectively provided with a first photoresist opening and a second photoresist opening, the width of the first photoresist opening is greater than that of the first opening, and the width of the second photoresist opening is greater than that of the third opening;
and etching the semiconductor substrate corresponding to the first opening and the third opening by taking the first photoresist pattern and the first interlayer dielectric layer as masks to form a first groove penetrating through the first area and a third groove penetrating through the second area.
8. The method according to claim 6, wherein etching the semiconductor substrate corresponding to the second opening to form a second trench penetrating the first region comprises:
forming a second photoresist pattern on the first interlayer dielectric layer, wherein a third photoresist opening is formed in a region, corresponding to the second opening, of the second photoresist pattern, and the width of the third photoresist opening is larger than that of the second opening;
and etching the semiconductor substrate corresponding to the second opening by using the second photoresist pattern and the first interlayer dielectric layer as masks to form a second groove penetrating through the first region.
9. The method of any one of claims 6 to 8, wherein forming the first metal plug, the second metal plug, and the third metal plug comprises:
forming a first metal layer, wherein the first metal layer covers the gate dielectric layer and the inner wall of the second groove and correspondingly extends into the opening of the first interlayer dielectric layer;
and forming a second metal layer at one end of the first metal layer far away from the semiconductor substrate, wherein the top of the second metal layer is at least not lower than the surface of the first interlayer dielectric layer, and the first metal layer and the second metal layer define an accommodating cavity.
10. The method of manufacturing according to claim 9, further comprising, before forming the second metal layer: and forming a third metal layer on the first metal layer to fill the accommodating cavity.
CN202111499851.1A 2021-12-09 2021-12-09 Power MOSFET device and preparation method thereof Pending CN114141878A (en)

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