CN114141627A - Silicon carbide semiconductor device and manufacturing method thereof - Google Patents

Silicon carbide semiconductor device and manufacturing method thereof Download PDF

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CN114141627A
CN114141627A CN202111363503.1A CN202111363503A CN114141627A CN 114141627 A CN114141627 A CN 114141627A CN 202111363503 A CN202111363503 A CN 202111363503A CN 114141627 A CN114141627 A CN 114141627A
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epitaxial layer
layer
region
well region
epitaxial
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袁俊
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Hubei Jiufengshan Laboratory
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Hubei Jiufengshan Laboratory
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Priority to CN202111363503.1A priority Critical patent/CN114141627A/en
Publication of CN114141627A publication Critical patent/CN114141627A/en
Priority to EP22894550.7A priority patent/EP4376056A1/en
Priority to PCT/CN2022/125793 priority patent/WO2023088013A1/en
Priority to US18/426,392 priority patent/US20240170540A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The application discloses carborundum semiconductor device and preparation method thereof, epitaxial wafer includes: a semiconductor substrate; the first epitaxial layer is arranged on the surface of the semiconductor substrate; the second epitaxial layer is arranged on the surface of one side, away from the semiconductor substrate, of the first epitaxial layer; and the third epitaxial layer is arranged on the surface of one side, away from the first epitaxial layer, of the second epitaxial layer. The grid electrode is formed through the groove formed in the third epitaxial layer, and ion implantation can be carried out in the second epitaxial layer based on the groove before the grid electrode is formed, so that a doped region in a shape opposite to that of the second epitaxial layer is formed in the second epitaxial layer, and the problem that a large-depth doped region is not conveniently formed in a silicon carbide semiconductor power device is solved.

Description

Silicon carbide semiconductor device and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor devices, and more particularly, to a silicon carbide (SiC) semiconductor device and a method for manufacturing the same.
Background
With the continuous development of science and technology, more and more electronic devices are widely applied to daily life and work of people, bring great convenience to the daily life and work of people, and become an indispensable important tool for people at present.
The main structure of an electronic device that realizes various functions is an integrated circuit, and semiconductor devices are important constituent electronic components of the integrated circuit. Silicon carbide semiconductor devices have become a major development in the semiconductor field due to their superior characteristics in high power applications.
Due to the characteristics of silicon carbide materials, if doping with a large implantation depth is to be realized, high-energy ion implantation may cause lattice damage, so in the existing manufacturing method, when a silicon carbide semiconductor device with a large depth doping region is manufactured, a required doping region needs to be formed in an epitaxial layer formed in advance by etching and ion implantation in the manufacturing process of an epitaxial wafer, and then a subsequent epitaxial layer is formed.
Disclosure of Invention
In view of the above, the present application provides a silicon carbide semiconductor device and a method for manufacturing the same, and the scheme is as follows:
a method of fabricating a silicon carbide semiconductor device, comprising:
providing an epitaxial wafer, wherein the epitaxial wafer comprises: a semiconductor substrate; the first epitaxial layer is arranged on the surface of the semiconductor substrate; the second epitaxial layer is arranged on the surface of one side, away from the semiconductor substrate, of the first epitaxial layer; the third epitaxial layer is arranged on the surface of one side, away from the first epitaxial layer, of the second epitaxial layer;
forming a well region, a source region and a groove in the third epitaxial layer;
performing ion implantation in the second epitaxial layer based on the groove to form a doped region in an inversion mode with the second epitaxial layer; the doped region penetrates through the second epitaxial layer;
and forming a gate in the groove.
Preferably, in the above manufacturing method, the second epitaxial layer has a region to be implanted and a first layer of well region surrounding the region to be implanted;
forming a well region, a source region and a trench in the third epitaxial layer, including:
forming a second layer of well region, a third layer of well region and a source region in sequence in the third epitaxial layer through ion implantation; the second layer of well region is positioned between the first layer of well region and the third layer of well region, and the source region is positioned on one side of the third layer of well region, which is far away from the second layer of well region;
forming the groove in the surface of one side, away from the second epitaxial layer, of the third epitaxial layer; the bottom of the trench is positioned between the second epitaxial layer and the third layer well region;
the source region and the third layer well region are both contacted with the side wall of the groove; the second layer well region has a distance with the side wall of the groove.
Preferably, in the above method, the method of manufacturing an epitaxial wafer includes:
sequentially forming the first epitaxial layer, the second epitaxial layer and the third epitaxial layer on the surface of the semiconductor substrate in an epitaxial mode;
the first epitaxial layer and the third epitaxial layer are doped in the same type and are doped in a reverse mode with the second epitaxial layer.
Preferably, the above method further comprises:
forming a metal source electrode connected with the source region;
and forming a metal drain on the surface of one side of the semiconductor substrate, which is far away from the first epitaxial layer.
The application also provides a silicon carbide semiconductor device prepared by the manufacturing method, which comprises the following steps:
an epitaxial wafer, the epitaxial wafer comprising: a semiconductor substrate; the first epitaxial layer is arranged on the surface of the semiconductor substrate; the second epitaxial layer is arranged on the surface of one side, away from the semiconductor substrate, of the first epitaxial layer; the third epitaxial layer is arranged on the surface of one side, away from the first epitaxial layer, of the second epitaxial layer;
the well region, the source region and the groove are arranged in the third epitaxial layer;
a doped region penetrating through the second epitaxial layer, the doped region being doped in an inversion type and formed by ion implantation based on the trench;
a gate disposed within the trench.
Preferably, in the silicon carbide semiconductor device, the second epitaxial layer has a region to be implanted and a first layer of well region surrounding the region to be implanted; the third epitaxial layer is internally provided with a second layer of well region, a third layer of well region and the source region; the second layer of well region is positioned between the first layer of well region and the third layer of well region, and the source region is positioned on one side of the third layer of well region, which is far away from the second layer of well region; the source region and the third layer of well region are both contacted with the side wall of the groove; the second layer of well region has a distance with the side wall of the groove; the groove is positioned in the surface of one side, away from the semiconductor substrate, of the third epitaxial layer; the bottom of the trench is positioned between the second epitaxial layer and the third layer well region;
the thickness of the third epitaxial layer is not more than 1 mu m; the distance between the bottom of the groove and the first epitaxial layer is less than 1 μm.
Preferably, in the above silicon carbide semiconductor device, a width of the trench satisfies a uniform condition in a direction in which a bottom of the trench is directed to the opening.
Preferably, in the above silicon carbide semiconductor device, a width of the trench gradually increases in a direction in which a bottom of the trench is directed toward the opening.
Preferably, in the above silicon carbide semiconductor device, the width of the doped region is not greater than the width of the trench.
Preferably, in the silicon carbide semiconductor device, the doping regions, the first epitaxial layer, and the third epitaxial layer have the same doping type;
the doping concentration of the doping area is greater than the doping concentrations of the first epitaxial layer and the third epitaxial layer.
As can be seen from the above description, in the silicon carbide semiconductor device and the manufacturing method thereof provided in the present application, the epitaxial wafer includes: a semiconductor substrate; the first epitaxial layer is arranged on the surface of the semiconductor substrate; the second epitaxial layer is arranged on the surface of one side, away from the semiconductor substrate, of the first epitaxial layer; and the third epitaxial layer is arranged on the surface of one side, away from the first epitaxial layer, of the second epitaxial layer. The grid electrode is formed through the groove formed in the third epitaxial layer, and ion implantation can be carried out in the second epitaxial layer based on the groove before the grid electrode is formed, so that a doped region in a shape opposite to that of the second epitaxial layer is formed in the second epitaxial layer, and the problem that a large-depth doped region is not conveniently formed in a silicon carbide semiconductor power device is solved.
Drawings
In order to more clearly illustrate the embodiments of the present application or technical solutions in related arts, the drawings used in the description of the embodiments or prior arts will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
The structures, proportions, and dimensions shown in the drawings and described in the specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure, which is defined by the claims, but rather by the claims, it is understood that these drawings and their equivalents are merely illustrative and not intended to limit the scope of the present disclosure.
FIG. 1 is a schematic diagram of a DMOSFET structure;
FIG. 2 is a schematic diagram of a UMOSFET structure;
FIG. 3 is a waveform diagram of voltage overshoot and ringing at the instant of MOSFET switching;
fig. 4-10 are process flow diagrams of a method for fabricating a silicon carbide semiconductor device according to an embodiment of the present disclosure;
fig. 11 is a schematic structural view of a silicon carbide semiconductor device according to an embodiment of the present application;
fig. 12 is a schematic view of the principal current paths of the silicon carbide semiconductor device shown in fig. 10 at the moment of turn-on;
fig. 13 is a schematic view of equivalent parasitic parameters of the silicon carbide semiconductor device shown in fig. 12;
fig. 14 is a layout of a silicon carbide semiconductor device in a trench design and an ion implantation area in a doped region according to an embodiment of the present application.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown, and in which it is to be understood that the embodiments described are merely illustrative of some, but not all, of the embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Because of its excellent characteristics, SiC materials have a strong attraction in terms of high power, and thus are one of the ideal materials for high-performance power MOSFETs. The SiC vertical power MOSFET device mainly comprises a lateral double-diffused DMOSFET and a UMOSFET with a vertical gate groove structure.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a DMOSFET, which includes: a substrate 2 of n + (heavily n-type doped); an n- (n-type lightly doped) drift region 3 disposed on a surface of the substrate 2; a p-type well region 4 located within the drift region 3; and a source region 5 located within the p-type well region, the source region 5 comprising an n + doped region 51 and a p + (p-type heavily doped) doped region 52. A grid dielectric layer 7 is arranged on the surface of the drift region 3, and a grid 8 is arranged on the surface of the grid dielectric layer 7. The surface of the substrate 2 facing away from the drift region 3 has a drain 1.
The DMOSFET structure employs planar diffusion technology, uses refractory materials such as polysilicon gate as a mask, and defines a p-base region and an n + source region with the edges of the polysilicon gate. The DMOS name is derived from this double diffusion process. And forming a surface channel region by utilizing the side diffusion difference of the p-type base region and the n + source region.
As shown in fig. 2, fig. 2 is a schematic structural diagram of a UMOSFET, and the difference from the structure shown in fig. 1 is that a U-shaped groove is provided in the UMOSFET, a gate dielectric layer 7 covers the surface of the U-shaped groove, and a gate 8 is filled in the U-shaped groove. UMOSFET with vertical gate trench structure, its name is derived from U-type trench structure. The U-shaped groove structure is formed in the grid region by reactive ion etching. The U-shaped trench structure has a high channel density (channel density is defined as the active region channel width), which results in a significant reduction in the on-state characteristic resistance of the device.
After years of research in the industry, planar SiC MOSFETs have been introduced into commercial products by some manufacturers. For the common lateral DMOSFET structure, the modern technological progress has reached the degree that the reduction of the MOS cell size cannot reduce the on-resistance, mainly because the on-resistance per unit area is difficult to reduce to 2m Ω · cm even with smaller lithographic size due to the limitation of the JFET neck region resistance2And the trench structure can effectively solve the problem. The U-shaped groove structure is shown in figure 2, and the groove etching technology in each process of manufacturing the memory storage capacitor is adopted, so that the transverse direction of a conductive channel is changed into the longitudinal direction, compared with the common structure, the JFET neck resistance is eliminated, the cell density is greatly increased, and the current processing capacity of the power semiconductor is improved.
However, SiC UMOSFETs still have several problems in practical process fabrication and application:
1) the high electric field in the SiC drift region causes the electric field on the gate dielectric layer to be very high, which is exacerbated at the corners of the trench, thereby causing rapid breakdown of the gate dielectric layer at high drain voltages; the electrostatic effect to harsh environments and the high voltage spikes in the circuit are poorly tolerated.
2) Because the SiC power MOSFET is mainly applied in the field of high voltage, high frequency and large current, the parasitic parameters in the circuit can cause spike burrs to be generated in the high frequency switching process, as shown in fig. 3, fig. 3 is a waveform diagram of instantaneous voltage overshoot and oscillation phenomena of the MOSFET switching, and based on fig. 3, instantaneous overvoltage on a device current path is caused, and loss in the switching process is increased; or a large surge voltage is generated due to a change in power load or the like, so that the surge voltage resistance and overvoltage protection of the MOSFET are also very important.
Because the conventional MOSFET device itself does not have surge voltage self-suppression capability and overvoltage protection capability, it is often necessary to design a complicated snubber circuit, a surge voltage suppression circuit and an overvoltage protection circuit in practical applications. The external matching suppression and overvoltage protection circuit is often delayed in time, high-frequency spike voltage surge in the actual switching process is still borne by the device, so that breakdown failure of a channel region of the device and gradual failure of ohmic contact regions of a gate structure and an electrode sometimes can be caused, and the reliability problem of the device is caused.
3) The limited depth of ion implantation makes many targeted trench gate protection structures and anti-surge designs technically difficult to implement. The depth of the trench used for forming the gate is generally 1 μm to 2 μm, because the actual process of forming the buried protection structure cannot be directly performed by ion implantation to protect the gate structure in the trench, because the depth of the ion implantation in the silicon carbide process is difficult to exceed 1 μm. In the prior art, a required doped region is formed in an epitaxial layer which is formed in advance by etching and ion implantation, and then two P-type epitaxial layers with specific structures are formed, so that the manufacturing process is complex and the manufacturing cost is high.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, the present application is described in further detail with reference to the accompanying drawings and the detailed description.
As shown in fig. 4 to 10, fig. 4 to 10 are process flow charts of a method for manufacturing a silicon carbide semiconductor device according to an embodiment of the present application, where the method includes:
step S11: as shown in fig. 4, an epitaxial wafer is provided, the epitaxial wafer comprising: a semiconductor substrate 10; a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10; the second epitaxial layer 12 is arranged on the surface of one side, away from the semiconductor substrate 10, of the first epitaxial layer 11; and the third epitaxial layer 13 is arranged on the surface of one side, away from the first epitaxial layer 11, of the second epitaxial layer 12.
The epitaxial wafer is a silicon carbide epitaxial wafer, and the semiconductor substrate 10 and each epitaxial layer on the surface thereof are made of a silicon carbide material.
Step S12: as shown in fig. 5-8, a well region, a source region 15 and a trench 20 are formed in the third epitaxial layer 13;
step S13: as shown in fig. 9, ion implantation is performed in the second epitaxial layer 12 on the basis of the trenches 20 to form doped regions 17 of opposite type to the second epitaxial layer 12; the doped region 17 penetrates through the second epitaxial layer 12;
step S14: as shown in fig. 10, a gate 18 is formed within the trench 20.
Fig. 10 shows only one cell structure of the semiconductor device. The semiconductor device may be a silicon carbide MOSFET device. In an actual product, the semiconductor device may have a plurality of cell structures. The number of cells and the layout mode may be set according to the requirement, which is not specifically limited in the embodiment of the present application.
In the manufacturing method of the embodiment of the application, the manufacturing method of the epitaxial wafer comprises the following steps: sequentially forming the first epitaxial layer 11, the second epitaxial layer 12 and the third epitaxial layer 13 in an epitaxial manner on the surface of the semiconductor substrate 10; the first epitaxial layer 11 and the third epitaxial layer 13 have the same doping type, and are doped in an opposite type to the second epitaxial layer 12.
The semiconductor substrate 10 may be an n + -type doped silicon carbide substrate, the first epitaxial layer 11 and the third epitaxial layer 13 are both n-type doped silicon carbide epitaxial layers, and the second epitaxial layer 12 is a p-type doped silicon carbide epitaxial layer. For example, the p-type doped second epitaxial layer 12 is a buried layer, an epitaxial wafer with the buried layer is skillfully adopted, and ion implantation is performed by using the trench 20 required by the gate 8 to form the doped region 17, thereby solving the difficulties of the shielding of the trench gate structure and the implantation process of silicon carbide material. And the doped region 17 can form a JFET structure which can be modulated in a device current path, so that the device resistance and the self-locking protection effect can be automatically adjusted, and meanwhile, the cell size of the device can be smaller.
In the semiconductor device, the well region structure includes: a first layer well region 141, a second layer well region 142, and a third layer well region 143. The second epitaxial layer 12 has a region to be implanted and a first layer well region 141 surrounding the region to be implanted; the region to be implanted is used to form the doped region 17.
In step S12, forming a well region, a source region 15, and a trench 20 in the third epitaxial layer 13 includes:
first, as shown in fig. 5-7, a second layer well region 142, a third layer well region 143, and a source region 15 are sequentially formed in the third epitaxial layer 13 by ion implantation; the second layer well region 142 is located between the first layer well region 141 and the third layer well region 143, and the source region 15 is located on a side of the third layer well region 143 away from the second layer well region 142.
Specifically, as shown in fig. 5, ion implantation is performed based on the mask layer 01, and a second layer well region 142 is formed in the third epitaxial layer 13, where the second layer well region 142 surrounds a non-implanted region. And forming a required non-implantation area based on the patterned mask layer 01. The vertical projections of the trenches 20 and the doped regions 17 are in the non-implanted regions and are spaced from the non-implanted regions in a direction parallel to the epitaxial wafer (i.e., the horizontal direction in fig. 5-8). Further, as shown in fig. 6, a third layer well region 143 is formed on the second layer well region 142 by ion implantation again, and the third layer well region 143 covers the second layer well region 142 and the non-implanted region surrounded by the second layer well region 142. Further, as shown in fig. 7, source region 15 is formed on third layer well region 143 again by ion implantation.
Then, as shown in fig. 8, forming the trench 20 in a side surface of the third epitaxial layer 13 facing away from the second epitaxial layer 12; the bottom of the trench 20 is located between the second epitaxial layer 12 and the third layer well region 143.
Wherein the source region 15 and the third layer well region 143 are both in contact with the sidewall of the trench 20; when the source region 15 is formed by ion implantation, the ion implantation region covers the region for forming the trench 20, so that the source region 15 which is not removed can be directly contacted with the sidewall of the trench 20 after the trench is formed subsequently. Similarly, when the third layer well region 143 is formed by ion implantation, the ion implantation region covers the region for forming the trench 20, so that after the trench is formed subsequently, the third layer well region 143 that is not removed can be directly contacted with the sidewall of the trench 20.
The second layer well region 142 is spaced apart from the sidewalls of the trench 20. The size of the non-implanted region surrounded by the second layer well region 142 is set to be larger than the size of the trench 20, and the vertical projection of the trench 20 is set to be located in the non-implanted region and have a distance from the non-implanted region, that is, the second layer well region 142 is not in contact with the sidewall of the trench 20, so that a distance is formed between the second layer well region 142 and the sidewall of the trench 20.
As shown in fig. 10, the manufacturing method further includes:
forming a metal source electrode 21 connected with the source region 15;
and forming a metal drain 19 on the surface of one side of the semiconductor substrate 10, which is far away from the first epitaxial layer 11.
The source region 15 includes a first region 151 and a second region 152 with opposite doping types, and the source region 15 contacts both the first region 151 and the second region 152. The first region 151 may be provided as an n + -type doped region and the second region 152 may be provided as a p + -type doped region.
In the silicon carbide semiconductor device formed by the manufacturing method of the embodiment of the present application, the well region structure includes three layers, which are a first layer of well region 141, a second layer of well region 142, and a third layer of well region 143. The uppermost third layer well region 143 is located on the left and right sides of the trench 20 and contacts the sidewalls of the trench 20. The second layer well 142 of the middle layer includes two portions located at the left and right sides of the trench 20, and is not in contact with the sidewall of the trench 20. The lowermost first layer well region 141 is located under trench 20 without contacting trench 20.
The distance between the left and right portions of the second layer of well region 142 and the vertical central axis of the cell structure is greater than the distance between the left and right portions of the first layer of well region 141 and the vertical central axis of the cell structure, specifically, the vertical central axis of the cell structure is the central axis of the trench 20, as shown by the dotted line in fig. 10, and the first layer of well region 141 is closer to the central axis than the second layer of well region 142.
A specific JFET structure can be formed on a current path between the source and the drain through the doped region 17, and the on-state characteristic of the JFET structure can be optimally adjusted through the pattern design of the doped region 17, the ion implantation concentration and the pattern profile, so as to improve the performance of the semiconductor device.
This application technical scheme through ingenious second epitaxial layer 12 of involving in the epitaxial wafer and running through second epitaxial layer 12 doping region 17 has solved the shielding of SiC slot MOSFET grid oxygen structure and the difficult problem of the deep implantation technology in the carborundum material, simultaneously, doping region 17 can also introduce the JFET structure that can pass through ion implantation modulation on the current path of device, when automatically regulated device on-resistance and auto-lock protective effect, can also keep less device cell size.
As can be seen from the above description, the silicon carbide semiconductor device formed based on the manufacturing method of the embodiment of the present application has at least the following beneficial effects:
the silicon carbide semiconductor device can introduce a JFET structure on a current path of the cellular structure, can automatically adjust the on-resistance and the self-locking protection effect of the device, and can keep the cellular size of the smaller device, and the on-characteristic of the JFET structure is optimally adjusted by the pattern design of the doped region 17, the ion implantation concentration and the pattern profile, so that the silicon carbide semiconductor device is flexible in design and process and has better manufacturability.
By utilizing an epitaxial wafer with a buried layer (the second epitaxial layer 12) and the JFET structure modulated by the implantation of the doped region 17, depletion regions at two sides can be automatically expanded under large surge voltage so as to increase the on-resistance of the JFET structure, which is equivalent to a buffer circuit structure for automatically suppressing surge peaks; meanwhile, when the surge voltage is overlarge, depletion regions on two sides continue to expand and are overlapped with each other, a blocking effect is achieved, a grid dielectric layer on the surface of the groove inside is protected, and a certain peak voltage overvoltage protection effect is achieved.
Although a certain on-resistance is increased by introducing the JFET structure, the JFET structure has the effects of switch buffering and surge voltage self-suppression.
The silicon carbide semiconductor device can increase the self-inhibition resistance of the device to surge voltage and overvoltage, and avoid device damage and reliability loss caused by time delay in actual action of an overvoltage protection circuit and an overcurrent protection circuit.
Meanwhile, the peak jitter in the circuit switching process is buffered, and the switching loss is reduced; can reduce buffer circuit and buffer circuit structure in the circuit design, reduce the components and parts of discreteness to reduce cost has also reduced actual module volume, reinforcing reliability.
Based on the foregoing embodiments, another embodiment of the present application further provides a silicon carbide semiconductor device, which may be prepared by the manufacturing method described in the foregoing embodiments, and the structure of the silicon carbide semiconductor device may be as shown in fig. 10, where the silicon carbide semiconductor device includes:
an epitaxial wafer, the epitaxial wafer comprising: a semiconductor substrate 10; a first epitaxial layer 11 disposed on the surface of the semiconductor substrate 10; the second epitaxial layer 12 is arranged on the surface of one side, away from the semiconductor substrate 10, of the first epitaxial layer 11; a third epitaxial layer 13 disposed on a surface of the second epitaxial layer 12 on a side facing away from the first epitaxial layer 11;
the well region, the source region 15 and the trench are arranged in the third epitaxial layer;
a doped region 17 penetrating the second epitaxial layer 12, the doped region 17 and the second epitaxial layer being counter-doped and formed by ion implantation based on the trench;
a gate 18 disposed within the trench. The gate 18 includes a fill dielectric filling the trench and a metal gate at the surface of the fill dielectric. The surface of the groove is provided with a grid dielectric layer, and after the grid dielectric layer is formed, a grid 18 is formed in the groove. The filling medium can be polysilicon and the like. Before forming a gate dielectric layer in the trench, a doped region 17 is formed.
Wherein the second epitaxial layer 12 has a region to be implanted and a first layer well region 141 surrounding the region to be implanted; the third epitaxial layer 13 has a second layer well region 142, a third layer well region 142 and the source region 15; the second layer well region 142 is located between the first layer well region 141 and the third layer well region 143, and the source region 15 is located on a side of the third layer well region 143 facing away from the second layer well region 142; the source region 15 and the third layer well region 143 are both in contact with the sidewalls of the trench; the bottom of the trench is located between the second epitaxial layer 12 and the third layer well region 143; the second layer well region 142 is located at two sides of the trench, and has a distance with the sidewall of the trench.
In the silicon carbide semiconductor device, the thickness of the third epitaxial layer 13 does not exceed 1 μm, so that the ion implantation depth of the second well region 142 and the third well region 143 does not exceed 1 μm, the second well region 142 and the third well region 143 can be formed in the third epitaxial layer 13 of the silicon carbide material through ion implantation, and lattice damage is not caused.
In the embodiment of the present invention, the distance between the bottom of the trench and the first epitaxial layer 11 is less than 1 μm, so that when the doped region 17 is formed by performing ion implantation based on the trench, the ion implantation depth of the doped region 17 is less than 1 μm, and the doped region 17 can be formed in the second epitaxial layer 12 of the silicon carbide material by ion implantation without causing lattice damage. The doped regions 17 and the trench bottom have a non-zero spacing.
Optionally, in a direction (a direction from bottom to top in fig. 10) in which the bottom of the trench points to the opening, the width of the trench satisfies a uniform condition, that is, the widths of the trenches are all the same or approximately the same in the direction, that is, the trench is a rectangular trench. The second epitaxial layer 12 is generally an epitaxial layer having a uniform thickness, and the width of the trenches is set to satisfy the uniform condition, so as to form the doped regions 17 having a uniform width in the direction.
In another mode, the structure of the electronic device may be as shown in fig. 11, and fig. 11 is a schematic structural view of a silicon carbide semiconductor device according to an embodiment of the present application, which is different from the structure shown in fig. 10 in that the width of the trench gradually increases in a direction in which the bottom of the trench is directed to the opening, that is, the trench is a V-shaped trench or an inverted trapezoidal trench. If the trench is a V-shaped trench, the doped region 17 is a V-shaped structure, if the trench is an inverted trapezoid trench, when the ion implantation window is larger than the bottom of the trench, the doped region is an inverted trapezoid structure as shown in fig. 11, and if the ion implantation window is not larger than the bottom of the trench, the doped region is a rectangular structure.
In the embodiment of the present application, the width of the doped region 17 is not greater than the width of the trench, so that the doped region 17 can be formed by ion implantation based on the trench, the depth of the ion implantation is reduced,
the doping regions 17, the first epitaxial layer 11 and the third epitaxial layer 13 have the same doping type.
The silicon carbide semiconductor device is an NMOS. The semiconductor substrate 10 is an n + type substrate, the first epitaxial layer 11 and the third epitaxial layer 13 are both doped in an n-type manner, the second epitaxial layer 12 is doped in a p-type manner, and the doped region 17 is doped in an n-type manner. In the embodiment of the application, the doping concentration has the relation of n + greater than n > n-, and p + greater than p > p-. n-, n and n + are homotype dopants, all of the first type dopants. p-, p and p + are homotype dopants, all of a second type dopant. The first type doping and the second type doping are inverse type doping.
Obviously, the silicon carbide semiconductor device may also be a PMOS. The doping type can be set based on the requirement to form NMOS or PMOS.
The doping concentration of the doped region 17 is greater than the doping concentrations of the first epitaxial layer 11 and the third epitaxial layer 13. The doped region 17 is doped n +.
As shown in fig. 12, fig. 12 is a schematic diagram of a main current path of the silicon carbide semiconductor device shown in fig. 10 at the turn-on moment, a current path is formed between a source electrode and a drain electrode, a middle dotted curve shown in fig. 12 represents a circuit path, and current passes through a JFET structure formed based on the doped region 17. Due to the rapid change of the current, a high-frequency spike voltage is generated in the circuit, and at the same time, due to the rapid change of the voltage on the current, the depletion region (the region between the left and right dashed curves in fig. 12) of the JFET structure expands or contracts rapidly corresponding to different voltage changes, and the JFET structure is equivalent to a parallel structure of a variable resistor R and a junction capacitor C, as shown in fig. 13, and fig. 13 is a schematic diagram of equivalent parasitic parameters of the silicon carbide semiconductor device shown in fig. 12.
Through specific circuit application and device electrical model simulation, the appropriate thickness d and doping concentration of the second epitaxial layer 12, and the pattern design, concentration and pattern profile design of the ion implantation structure of the doping region 17 are selected for optimal adjustment, so that appropriate parasitic parameter values (required variable resistor R and a junction capacitor C) can be obtained, and when the parasitic parameter values are actually applied to circuit modules with different switching frequencies, an effective voltage spike suppression effect is achieved, and meanwhile, the switching-on loss is reduced.
In the embodiments of the present application, the silicon carbide semiconductor device is described only as a single cell structure. It is apparent that the semiconductor device may be fabricated by simultaneously fabricating a plurality of cell structures based on a wafer-level process and then dividing the wafer to form the silicon carbide semiconductor device having a plurality of cell structures.
As shown in fig. 14, fig. 14 is a layout of a silicon carbide semiconductor device in a trench design and an ion implantation area of a doped region, an implantation window of the doped region 17 is located in the trench 20, and a channel characteristic of a JFET structure can be adjusted by a pattern design, an ion implantation concentration, and a pattern profile design of the doped region 17. The implantation window area of the doped region 17 may be smaller than or equal to the area of the trench 20.
The embodiments in the present description are described in a progressive manner, or in a parallel manner, or in a combination of a progressive manner and a parallel manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments can be referred to each other.
It should be noted that in the description of the present application, it is to be understood that the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are only used for convenience in describing the present application and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be configured and operated in a specific orientation, and thus, should not be construed as limiting the present application. When a component is referred to as being "connected" to another component, it can be directly connected to the other component or intervening components may also be present.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in an article or device that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A method of fabricating a silicon carbide semiconductor device, comprising:
providing an epitaxial wafer, wherein the epitaxial wafer comprises: a semiconductor substrate; the first epitaxial layer is arranged on the surface of the semiconductor substrate; the second epitaxial layer is arranged on the surface of one side, away from the semiconductor substrate, of the first epitaxial layer; the third epitaxial layer is arranged on the surface of one side, away from the first epitaxial layer, of the second epitaxial layer;
forming a well region, a source region and a groove in the third epitaxial layer;
performing ion implantation in the second epitaxial layer based on the groove to form a doped region in an inversion mode with the second epitaxial layer; the doped region penetrates through the second epitaxial layer;
and forming a gate in the groove.
2. The method of manufacturing of claim 1, wherein the second epitaxial layer has a region to be implanted and a first layer of well region surrounding the region to be implanted;
forming a well region, a source region and a trench in the third epitaxial layer, including:
forming a second layer of well region, a third layer of well region and a source region in sequence in the third epitaxial layer through ion implantation; the second layer of well region is positioned between the first layer of well region and the third layer of well region, and the source region is positioned on one side of the third layer of well region, which is far away from the second layer of well region;
forming the groove in the surface of one side, away from the second epitaxial layer, of the third epitaxial layer; the bottom of the trench is positioned between the second epitaxial layer and the third layer well region;
the source region and the third layer well region are both contacted with the side wall of the groove; the second layer well region has a distance with the side wall of the groove.
3. The method of manufacturing according to claim 1, wherein the method of manufacturing an epitaxial wafer comprises:
sequentially forming the first epitaxial layer, the second epitaxial layer and the third epitaxial layer on the surface of the semiconductor substrate in an epitaxial mode;
the first epitaxial layer and the third epitaxial layer are doped in the same type and are doped in a reverse mode with the second epitaxial layer.
4. The method of manufacturing according to any one of claims 1 to 3, further comprising:
forming a metal source electrode connected with the source region;
and forming a metal drain on the surface of one side of the semiconductor substrate, which is far away from the first epitaxial layer.
5. A silicon carbide semiconductor device produced by the production method according to any one of claims 1 to 4, comprising:
an epitaxial wafer, the epitaxial wafer comprising: a semiconductor substrate; the first epitaxial layer is arranged on the surface of the semiconductor substrate; the second epitaxial layer is arranged on the surface of one side, away from the semiconductor substrate, of the first epitaxial layer; the third epitaxial layer is arranged on the surface of one side, away from the first epitaxial layer, of the second epitaxial layer;
the well region, the source region and the groove are arranged in the third epitaxial layer;
a doped region penetrating through the second epitaxial layer, the doped region being doped in an inversion type and formed by ion implantation based on the trench;
a gate disposed within the trench.
6. The silicon carbide semiconductor device according to claim 5, wherein the second epitaxial layer has a region to be implanted and a first layer well region surrounding the region to be implanted; the third epitaxial layer is internally provided with a second layer of well region, a third layer of well region and the source region; the second layer of well region is positioned between the first layer of well region and the third layer of well region, and the source region is positioned on one side of the third layer of well region, which is far away from the second layer of well region; the source region and the third layer of well region are both contacted with the side wall of the groove; the second layer of well region has a distance with the side wall of the groove; the groove is positioned in the surface of one side, away from the semiconductor substrate, of the third epitaxial layer; the bottom of the trench is positioned between the second epitaxial layer and the third layer well region;
the thickness of the third epitaxial layer is not more than 1 mu m; the distance between the bottom of the groove and the first epitaxial layer is less than 1 μm.
7. The silicon carbide semiconductor device according to claim 5, wherein a width of the trench satisfies a uniform condition in a direction in which a bottom of the trench points to the opening.
8. The silicon carbide semiconductor device according to claim 5, wherein a width of the trench gradually increases in a direction in which a bottom of the trench points toward the opening.
9. The silicon carbide semiconductor device according to claim 5, wherein the width of the doped region is not greater than the width of the trench.
10. The silicon carbide semiconductor device according to claim 5, wherein the doping regions, the first epitaxial layer, and the third epitaxial layer are of the same doping type;
the doping concentration of the doping area is greater than the doping concentrations of the first epitaxial layer and the third epitaxial layer.
CN202111363503.1A 2021-11-17 2021-11-17 Silicon carbide semiconductor device and manufacturing method thereof Pending CN114141627A (en)

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CN202111363503.1A CN114141627A (en) 2021-11-17 2021-11-17 Silicon carbide semiconductor device and manufacturing method thereof
EP22894550.7A EP4376056A1 (en) 2021-11-17 2022-10-18 Silicon carbide semiconductor device and manufacturing method therefor
PCT/CN2022/125793 WO2023088013A1 (en) 2021-11-17 2022-10-18 Silicon carbide semiconductor device and manufacturing method therefor
US18/426,392 US20240170540A1 (en) 2021-11-17 2024-01-30 Silicon carbide semiconductor device and manufacturing method therefor

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023088013A1 (en) * 2021-11-17 2023-05-25 湖北九峰山实验室 Silicon carbide semiconductor device and manufacturing method therefor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023088013A1 (en) * 2021-11-17 2023-05-25 湖北九峰山实验室 Silicon carbide semiconductor device and manufacturing method therefor

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