CN114141295A - Memory and programming method and reading method thereof - Google Patents
Memory and programming method and reading method thereof Download PDFInfo
- Publication number
- CN114141295A CN114141295A CN202111434128.5A CN202111434128A CN114141295A CN 114141295 A CN114141295 A CN 114141295A CN 202111434128 A CN202111434128 A CN 202111434128A CN 114141295 A CN114141295 A CN 114141295A
- Authority
- CN
- China
- Prior art keywords
- programmed
- memory cell
- temperature
- time
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Read Only Memory (AREA)
Abstract
The present disclosure relates to a memory and a programming method and a reading method thereof, the programming method including: acquiring the programming temperature of a to-be-programmed storage unit of a memory, wherein the programming temperature is the temperature of the to-be-programmed storage unit; applying a programming voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stopping programming of the memory cell to be programmed, wherein the first sensing time comprises a first temperature compensation time adjusted according to a programming temperature, the second sensing time comprises a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different.
Description
Technical Field
The present application relates to a memory device, and more particularly, to a programming method, a reading method and apparatus of a memory.
Background
A flash memory is a type of non-volatile memory that is capable of retaining stored data without power up. Compared with the conventional hard disk, the flash memory has the advantages of faster reading speed, lower power consumption, better shock resistance and the like, and is therefore applied more and more. For example, flash memory is commonly used in electronic systems such as personal computers, digital cameras, digital media players, digital recorders, vehicles, wireless devices, cellular telephones, and removable memory modules. As the application field of flash memory is expanded, the flash memory is also exposed to more and more complex application environments, and therefore, reliability at different temperatures becomes an important product verification item of the flash memory.
After programming the memory cells of the memory, the threshold voltage of each memory cell is changed to achieve information storage. In using the memory, one may face low temperature programming, high temperature reading; high temperature programming, low temperature reading, etc. However, the polysilicon channel in flash memory is sensitive to temperature due to its physical characteristics, and its resistance has a high temperature dependence. For example, at a lower programming temperature, the threshold voltage distribution of the memory states may be wider, when read at a high temperature, the threshold voltage of the memory cell shifts, the threshold voltage distribution spreads may be different, and the difference between the memory states may also vary. Such temperature dependence may cause variations in threshold voltages determined during different stages of programming, memory states determined during read, etc., and ultimately result in data read errors.
Therefore, there is a need for a memory having good reliability at different temperatures.
It should be appreciated that this background section is intended in part to provide a useful background for understanding the present technology and is not intended to imply that such matter has necessarily been prior art, as is known to those skilled in the art, prior to the present application.
Disclosure of Invention
An aspect of the present disclosure provides a method of programming a memory, including: acquiring the programming temperature of a to-be-programmed storage unit of a memory, wherein the programming temperature is the temperature of the to-be-programmed storage unit; applying a programming voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stopping programming of the memory cell to be programmed, wherein the first sensing time comprises a first temperature compensation time adjusted according to a programming temperature, and the second sensing time comprises a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different.
In one embodiment, the first sensing time includes a first predetermined sensing time and a first temperature compensation time, and the second sensing time includes a second predetermined sensing time and a second temperature compensation time, the first predetermined sensing time being less than the second predetermined sensing time.
In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between a programmed temperature and a predetermined reference temperature.
In one embodiment, the reference temperature is 85 ℃.
In one embodiment, the first temperature compensation time and the second temperature compensation time are respectively determined according to a variation curve of the sensing current with time when the memory cell to be programmed is turned on in a corresponding time period at the programming temperature.
In one embodiment, the first temperature compensation time is set to be less than the second temperature compensation time when the slope time of the change curve decreases.
In one embodiment, the faster the charge is drained off in the corresponding time period, the shorter the corresponding first temperature compensation time or second temperature compensation time.
In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between a programming temperature and a reference temperature and a variation curve of a sensing current with time when a memory cell to be programmed is turned on at the programming temperature.
In one embodiment, the programming method further comprises: reprogramming the memory cell to be programmed when the bit line voltage is less than or equal to a first target voltage after a first sensing time or when the bit line voltage is less than or equal to a second target voltage after a second sensing time, wherein the reprogramming comprises: changing the programming voltage; applying the changed program voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed; applying the verifying voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time; if yes, detecting whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage after the second sensing time, if yes, stopping programming the memory cell to be programmed, and if not, repeating the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage.
In one embodiment, the programming method further comprises: when the memory cell to be programmed is reprogrammed, the programming voltage is increased.
In one embodiment, the programming method further comprises: when the memory cell to be programmed is reprogrammed for multiple times, the programming voltage is gradually increased by the same step voltage.
In one embodiment, the programming method further comprises: applying a read voltage to a programmed memory cell to turn on the programmed memory cell; determining a storage state of the programmed memory cell after a read sensing time, wherein the read sensing time comprises a read temperature compensation time, the read temperature compensation time is determined according to a temperature when the programmed memory cell is read, and has the same temperature dependence curve as the second temperature compensation time used when the programmed memory cell is programmed.
Another aspect of the present disclosure provides a memory including an input/output circuit and a storage circuit, the input/output circuit including: a bus interface configured to receive data from outside the memory and transmit data from the memory to outside; and an input/output controller configured to control operation of the bus interface, the memory circuit comprising: a memory array comprising a plurality of memory cells; and a memory controller configured to control operations of the plurality of memory arrays, the memory controller, when programming a memory cell to be programmed of the plurality of memory cells, configured to: acquiring the programming temperature of a memory unit to be programmed in a memory array; applying a programming voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stopping programming of the memory cell to be programmed, wherein the first sensing time comprises a first temperature compensation time adjusted according to the programming temperature, the second sensing time comprises a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different.
Drawings
The above and other advantages and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
Fig. 1 shows a schematic diagram of a storage state of a memory cell in a memory according to an embodiment of the present disclosure.
Fig. 2 illustrates a method of programming a memory cell in a memory according to an embodiment of the present disclosure.
FIG. 3 illustrates a sensed current versus temperature compensation time in accordance with an embodiment of the disclosure.
Fig. 4 illustrates a change in the sensing voltage caused by a temperature compensation time according to an embodiment of the present disclosure.
FIG. 5 shows a schematic diagram of a memory according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It will also be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present. When an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. To this end, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements.
Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.
Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of one or more embodiments. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," and the like may also be used herein to distinguish between different classes or groups of elements. For the sake of simplicity, the terms "first", "second", etc. may denote "first class (or first group)", "second class (or second group)", etc. respectively.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
As used herein, "about" or "approximately" includes the stated value as well as the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the specified quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Some example embodiments are described and illustrated in the accompanying drawings with respect to functional blocks, units and/or modules as is conventional in the art. Those skilled in the art will appreciate that the blocks, units, and/or modules are physically implemented with electrical (or optical) circuitry, such as logic, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connectors, and so forth, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where the blocks, units, and/or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled by software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware for performing some functions or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. In addition, each block, unit and/or module in some example embodiments may be physically separated into two or more interactive and discrete blocks, units and/or modules without departing from the scope of the inventive concept. Furthermore, the blocks, units and/or modules in some example embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.
Fig. 1 shows a schematic diagram of a storage state of a memory cell in a memory according to an embodiment of the present disclosure. A memory according to embodiments of the present disclosure may include a plurality of memory cells therein, the memory cells capable of storing a plurality of memory states. As shown in fig. 1, an exemplary memory cell can include memory states 101, 102, and 103, which can correspond to programmed states of "00", "01", "11", etc., for example. It should be noted that fig. 1 is a schematic diagram shown for convenience of explaining the technical scheme of the present disclosure, and other memory states and a greater or lesser number of memory states are also possible in the memory of the present disclosure. There is a gap between the voltages corresponding to the different memory states 101, 102 and 103, and when reading the memory state of the memory cell, the different memory states can be distinguished according to the threshold voltages 111 and 121, wherein the first threshold voltage 111 is between the first memory state 101 and the second memory state 102, and the second threshold voltage 121 is between the second memory state 102 and the third memory state 103. In the reading process, when the determined voltage is lower than the first threshold voltage 111, the storage state of the corresponding memory cell is a first storage state 101; when the determined voltage is higher than the first threshold voltage 111 and lower than the second threshold voltage 121, the storage state of the corresponding memory cell is the second storage state 102; and when the determined voltage is higher than the second threshold voltage 121, the memory state of the corresponding memory cell is the third memory state 103.
When programming the memory cell, the memory state of the memory cell can be changed from low to high step by increasing the programming voltage. Each step programming process for a memory cell can be divided into two phases of programming and verifying, which in turn can be divided into two phases of coarse sensing and fine sensing. FIG. 2 illustrates a method 200 for programming a memory cell in a memory according to an embodiment of the disclosure, wherein step 202 is a programming phase, steps 203 to 204 are coarse sensing phases, and step 205 is a fine sensing phase.
As shown in fig. 2, taking programming a memory cell to the third memory state 103 as shown in fig. 1 as an example, the programming method 200 of the memory according to the present disclosure may include obtaining a programming temperature (step 201). When programming a certain memory cell to be programmed in the memory, the memory cell temperature at the time of programming, which may be the current temperature of the cell to be programmed, may be obtained by, for example, a temperature sensor, which may be used to determine the temperature compensation time used in the subsequent steps. It should be noted that the step of obtaining the programmed temperature does not have to be performed first, but it may be performed after other steps as long as the temperature is determined before the temperature compensation time is determined.
In step 202, a programming voltage may be applied to the memory cell to be programmed, for example, a word line corresponding to the memory cell to be programmed, and a bit line corresponding to the memory cell to be programmed is set to a low voltage, so as to change the charge on the floating gate of the memory cell to be programmed, thereby storing the state information.
After the programming phase, it is necessary to verify whether the programmed memory cells have reached the desired memory state. To this end, the programming method 200 according to the present disclosure includes a coarse sensing phase (steps 203 and 204). In step 203, a verify voltage is applied to the memory cell to be programmed to turn on the memory cell to be programmed. For example, a verification voltage may be applied to a control electrode (i.e., a corresponding word line) of a memory cell to be programmed, wherein the stored charge is lost over time after the memory cell to be programmed is turned on, and accordingly, the bit line voltage sensed on the corresponding bit line of the memory cell to be programmed is reduced, which may last for a period of time, e.g., for a first sensing time.
After the first sensing time, it may be determined whether the bit line voltage verifying the memory cell to be programmed is higher than a first target voltage (step 204), which may correspond to the first threshold voltage 111 of FIG. 1. If the bit line voltage is higher than the first target voltage, a subsequent fine sensing phase is performed, otherwise, the programmed state does not reach the expected state, and the memory cell needs to be reprogrammed. When the bit line voltage is higher than the first target voltage, it indicates that the memory state of the memory cell to be programmed is, for example, the second memory state 102 or the third memory state 203 shown in fig. 1. Whether the current storage state is the second storage state 102 or the third storage state 203 may be further determined by a subsequent fine sensing phase.
Entering the fine verify phase, after a second sensing time, the bit line voltage of the memory cell to be programmed can be verified to be higher than a second target voltage (step 205). If the bit line voltage is higher than the second target voltage, the programming operation is completed, and the programming of the memory cell to be programmed can be stopped, otherwise, the programming state does not reach the expected state, the memory cell needs to be programmed again, and in the reprogramming operation, the programming voltage can be increased to reprogram the memory cell. In some embodiments, each time the program is re-programmed, a certain step voltage may be increased relative to the last program voltage, and the same step voltage may be used in successive re-programming processes, or different step voltages may be used. For example, after a first programming, coarse sensing and/or fine sensing cycle, if the desired storage state is not reached, the programming phase is entered again and the programming voltage used is increased by a predetermined step voltage compared to the last cycle, and if the desired storage state is still not reached by this cycle, the programming voltage is increased again by the predetermined step voltage in the next cycle until the desired storage state is reached.
In the above process, the first sensing time may include a first predetermined sensing time and a first temperature compensation time, and the second sensing time may include a second predetermined sensing time and a second temperature compensation time, wherein the first predetermined sensing time and the second predetermined sensing time may be predetermined, for example, may be obtained experimentally or set by a user, and the first predetermined sensing time may be less than the second predetermined sensing time; the first temperature compensation time and the second temperature compensation time are used for compensating the influence of the working temperature of the memory on the programming and reading operations, for example, the saturation current may be reduced due to low temperature, and the difference of current, voltage and the like due to the temperature difference is compensated by adding the temperature compensation time on the basis of the original preset sensing time so that the current flowing time is increased or decreased. In the conventional temperature compensation method, the same temperature compensation time is used for both the coarse sensing stage and the fine sensing stage, however, since the charge loss speed of the sensing stage is not always the same, if the same temperature compensation time is used for the coarse sensing stage and the fine sensing stage which are temporally sequential, the offset of the sensed voltages in the two stages may be unequal, so that the difference of the sensed voltages between the two stages changes, which leads to inaccurate verification and finally affects the accuracy of data storage.
Specifically, as shown in fig. 3, the current dropping speed caused by the charge loss when the memory cell is turned on is initially fast and then gradually slows down, and the relationship between the current I and the time t (e.g., the temperature compensation time) is approximately in fact in an inverse relationship. In thatUnder the current time relationship, if the sensing voltage change DeltaV of the coarse sensing stage caused by the charge loss in the temperature compensation time in FIG. 4 is to be madecoarseAnd a sense voltage variation DeltaV of a fine sense phasefineKeeping the same, it is necessary to ensure the current change Δ I caused by the temperature compensation time in the coarse sensing stage and the fine sensing stagecoarseAnd Δ IfineAnd the consistency is maintained. According to the curve shown in FIG. 3, different temperature compensation times are required to obtain the same current change Δ IcoarseAnd Δ Ifine. Since the current drops rapidly in the coarse sensing stage, the first temperature can be compensated for the time tcoarseSet to be shorter; since the falling speed of the current in the fine sensing phase is slow, the second temperature can be compensated for the time tfineIs set longer, i.e. satisfies tfine>tcoarse。
The temperature compensation time may be determined based on a difference between the temperature at which the memory operates and a reference temperature (e.g., 85 ℃). For example, the temperature compensation times for the coarse sensing phase and the fine sensing phase at the reference temperature may be determined in advance through experiments or statistics, etc., and when the operating temperature is different from the reference temperature, the temperature compensation times are changed accordingly according to the difference therebetween. In some embodiments, the temperature compensation time may be further adjusted according to a current variation versus time determined by the physical characteristics of the programming unit (number of carriers, etc.) while varying the temperature compensation time accordingly according to the difference between the operating temperature and the reference temperature.
According to the programming method of the memory, the temperature compensation time of the coarse sensing stage and the temperature compensation time of the fine sensing stage are adjusted differently, so that the actual temperature compensation effect of the coarse sensing stage and the actual temperature compensation effect of the fine sensing stage are the same, the accuracy of data storage is further ensured, and the reliability of the memory in response to various temperatures is improved.
In reading a memory cell programmed according to the above-described method, the memory cell can be read using only the read phase corresponding to the above-described fine sensing phase, i.e., the read process includes only one sensing phase. In the sensing phase, a read voltage may be applied to the memory cell to be read to turn on the memory cell to be read, for example, a read voltage may be applied to a word line corresponding to the memory cell to be read. The memory state of the memory cell to be read is determined after the read sensing time, for example, by sensing a bit line voltage corresponding to the memory cell to be read. In the reading phase, the reading sensing time comprises a preset reading sensing time and a reading temperature compensation time, and the reading temperature compensation time and a second temperature compensation time used when the memory cell to be read is programmed have the same relation curve relative to the temperature. That is, if the reading temperature is the same as the programming temperature, the reading temperature compensation time is the same as the second temperature compensation time, and if the reading temperature is different from the programming temperature, the reading temperature compensation time can be obtained along the same temperature-compensation time curve according to the reading temperature, and the temperature-compensation time curve can be obtained according to statistics, experiments, user settings, and the like.
FIG. 5 shows a schematic diagram of a memory according to an embodiment of the present disclosure.
As shown in fig. 5, a memory 500 according to an embodiment of the present disclosure may include an input/output (I/O) circuit 510 and a storage circuit 520. The I/O circuitry 510 is used for communication between the storage circuitry and external devices, and the I/O circuitry 510 may include a bus interface 512 (e.g., PCIE interface, NVMe interface, etc.) that may receive data from outside the memory and transmit data from and to outside the memory. The I/O circuit 510 also includes an input/output controller 511 that controls the operation of the bus interface. The memory circuit 520 is used for storing data and may include a memory array 531 and 534 and a memory controller 521, wherein each of the memory arrays 531 and 534 may include a plurality of memory cells, the memory controller 521 is used for controlling operations (e.g., read operations, write operations, etc.) of the plurality of memory arrays, and for example, the memory controller 521 may perform a programming method of the memory as described above in conjunction with fig. 1-4. It should be noted that although four memory arrays are shown in fig. 5, the present application is not limited thereto, and any number of memory arrays may be included in the memory 500.
The memory 500 according to the embodiment of the present application may further include a temperature sensor, which may be located in the I/O circuit 510 or the memory circuit 520. When the temperature sensor is located in the I/O circuit 510, the I/O controller 511 may transmit the current temperature of the memory sensed by the temperature sensor to the memory controller 521 as a programming temperature of the memory cell to be programmed. When the temperature sensor is located in the memory circuit 520, the memory controller 521 may be configured to take the current temperature of the memory cell to be programmed, which is sensed by the temperature sensor, as the programming temperature of the memory cell to be programmed. The memory controller, when programming a memory cell to be programmed of the plurality of memory cells, is configured to: acquiring the programming temperature of a memory unit to be programmed in a memory array; applying a programming voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed; applying a verification voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; if so, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time, and if so, stopping programming of the memory cell to be programmed, wherein the first sensing time comprises a first temperature compensation time adjusted according to the programming temperature, the second sensing time respectively comprises a second temperature compensation time adjusted according to the programming temperature, and the first temperature compensation time and the second temperature compensation time are different.
In one embodiment, the first sensing time includes a first predetermined sensing time and a first temperature compensation time, and the second sensing time includes a second predetermined sensing time and a second temperature compensation time, the first predetermined sensing time being less than the second predetermined sensing time.
In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between a programmed temperature and a predetermined reference temperature.
In one embodiment, the reference temperature is 85 ℃.
In one embodiment, the first temperature compensation time and the second temperature compensation time are respectively determined according to a variation curve of the sensing current with time when the memory cell to be programmed is turned on in a corresponding time period at the programming temperature.
In one embodiment, the first temperature compensation time is set to be less than the second temperature compensation time when the slope time of the change curve decreases.
In one embodiment, the faster the charge is drained off in the corresponding time period, the shorter the corresponding first temperature compensation time or second temperature compensation time.
In one embodiment, the first temperature compensation time and the second temperature compensation time are determined according to a difference between a programming temperature and a reference temperature and a variation curve of a sensing current with time when a memory cell to be programmed is turned on at the programming temperature.
In one embodiment, the controller is further configured to: reprogramming the memory cell to be programmed when the bit line voltage is less than or equal to a first target voltage after a first sensing time or when the bit line voltage is less than or equal to a second target voltage after a second sensing time, wherein the reprogramming comprises: changing the programming voltage; applying the changed program voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed; applying the verifying voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time; if yes, detecting whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage after the second sensing time, if yes, stopping programming the memory cell to be programmed, and if not, repeating the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage.
In one embodiment, the controller is further configured to: when the memory cell to be programmed is reprogrammed, the programming voltage is increased.
In one embodiment, the controller is further configured to: when the memory cell to be programmed is reprogrammed for multiple times, the programming voltage is gradually increased by the same step voltage.
In one embodiment, when reading a programmed memory cell to be read from a plurality of memory cells, the method comprises: applying a reading voltage to the memory cell to be read to enable the memory cell to be read to be conducted; and determining the storage state of the storage unit to be read after the reading sensing time, wherein the reading sensing time comprises reading temperature compensation time, and the reading temperature compensation time and second temperature compensation time used when the storage unit to be read is programmed have the same relation curve relative to the temperature.
At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present invention. Accordingly, the disclosed preferred embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (26)
1. A method of programming a memory, comprising:
acquiring a programming temperature of a to-be-programmed storage unit of the memory, wherein the programming temperature is the temperature of the to-be-programmed storage unit;
applying a programming voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed;
applying a verifying voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; and
if so, detecting whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time,
wherein the first sensing time comprises a first temperature compensation time adjusted according to the programming temperature, and the second sensing time comprises a second temperature compensation time adjusted according to the programming temperature, the first temperature compensation time and the second temperature compensation time being different.
2. The programming method of claim 1,
the first sensing time comprises a first predetermined sensing time and the first temperature compensation time, an
The second sensing time comprises a second predetermined sensing time and the second temperature compensation time,
the first predetermined sensing time is less than the second predetermined sensing time.
3. The programming method of claim 1 or 2, wherein the first temperature compensation time and the second temperature compensation time are determined according to a difference of the programming temperature and a predetermined reference temperature.
4. The programming method of claim 3, wherein the reference temperature is 85 ℃.
5. The programming method according to claim 1 or 2, wherein the first temperature compensation time and the second temperature compensation time are respectively determined according to a variation curve of a sensing current with time when the memory cell to be programmed is turned on in a corresponding time period at the programming temperature.
6. The programming method according to claim 5, wherein the first temperature compensation time is set to be smaller than the second temperature compensation time when a slope time of the change curve decreases.
7. The programming method according to claim 6, wherein the faster the loss rate of the charge in the corresponding time period, the shorter the corresponding first temperature compensation time or the second temperature compensation time.
8. The programming method according to claim 1 or 2, wherein the first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a reference temperature and a variation curve of a sensing current with time when the memory cell to be programmed is turned on at the programming temperature.
9. The programming method of claim 1, further comprising:
reprogramming the memory cell to be programmed when the bit line voltage is less than or equal to a first target voltage after the first sensing time or when the bit line voltage is less than or equal to a second target voltage after the second sensing time,
wherein the reprogramming comprises:
changing the programming voltage;
applying the changed program voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed;
applying the verifying voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time;
if yes, detecting whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage after the second sensing time, if yes, stopping programming the memory cell to be programmed, and if not, repeating the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage.
10. The programming method of claim 9, further comprising: and when the memory cell to be programmed is reprogrammed, increasing the programming voltage.
11. The programming method of claim 10, further comprising: and when the memory cell to be programmed is reprogrammed for multiple times, the programming voltage is gradually increased by the same stepping voltage.
12. The programming method of claim 1, further comprising:
applying a read voltage to a programmed memory cell to turn on the programmed memory cell;
determining a storage state of the programmed memory cell after a read sensing time, wherein the read sensing time comprises a read temperature compensation time, the read temperature compensation time is determined according to a temperature when the programmed memory cell is read, and has the same temperature dependence curve as the second temperature compensation time used when the programmed memory cell is programmed.
13. A memory, comprising:
a memory array comprising a plurality of memory cells; and
a memory controller configured to control operations of the plurality of memory arrays,
wherein the memory controller, when programming a memory cell to be programmed in the plurality of memory cells, is configured to:
acquiring the programming temperature of a memory unit to be programmed in the memory array;
applying a programming voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed;
applying a verifying voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than a first target voltage after a first sensing time; and
if so, determining whether the bit line voltage of the memory cell to be programmed is higher than a second target voltage after a second sensing time,
wherein the first sensing time comprises a first temperature compensation time adjusted according to the programming temperature, and the second sensing time comprises a second temperature compensation time adjusted according to the programming temperature, the first temperature compensation time and the second temperature compensation time being different.
14. The memory of claim 13, further comprising:
an input/output circuit comprising:
a bus interface configured to receive data from outside the memory and transmit data from the memory to outside; and
an input/output controller configured to control operation of the bus interface;
the input/output circuit further includes a temperature sensor configured to sense a temperature of the memory, an
The input/output controller is further configured to transmit the temperature of the memory to the memory controller as a programming temperature of the memory cell to be programmed.
15. The memory of claim 13, wherein the storage circuitry further comprises a temperature sensor configured to sense a temperature of the memory cell to be programmed, an
The memory controller is further configured to take the temperature of the memory cell to be programmed as the programming temperature of the memory cell to be programmed.
16. The memory according to claim 13, wherein,
the first sensing time comprises a first predetermined sensing time and the first temperature compensation time, an
The second sensing time comprises a second predetermined sensing time and the second temperature compensation time,
the first predetermined sensing time is less than the second predetermined sensing time.
17. The memory according to claim 12 or 16, wherein the first temperature compensation time and the second temperature compensation time are determined according to a difference of the programming temperature and a predetermined reference temperature.
18. The memory of claim 16, wherein the reference temperature is 85 ℃.
19. The memory according to claim 13 or 16, wherein the first temperature compensation time and the second temperature compensation time are respectively determined according to a variation curve of a sensing current with time when the memory cell to be programmed is turned on in a corresponding time period at the programming temperature.
20. The memory of claim 19, wherein the first temperature compensation time is set to be less than the second temperature compensation time when a slope time of the change curve decreases.
21. The memory of claim 19, wherein the faster the rate of charge loss during the corresponding time period, the shorter the corresponding first or second temperature compensation time.
22. The memory according to claim 13 or 16, wherein the first temperature compensation time and the second temperature compensation time are determined according to a difference between the programming temperature and a reference temperature and a variation curve of a sensing current with time when the memory cell to be programmed is turned on at the programming temperature.
23. The memory of claim 13, the controller further configured to:
reprogramming the memory cell to be programmed when the bit line voltage is less than or equal to a first target voltage after the first sensing time or when the bit line voltage is less than or equal to a second target voltage after the second sensing time
Wherein the reprogramming comprises:
changing the programming voltage;
applying the changed program voltage to the memory cell to be programmed to change a storage state of the memory cell to be programmed;
applying the verifying voltage to the memory cell to be programmed to turn on the memory cell to be programmed, and determining whether a bit line voltage of the memory cell to be programmed is higher than the first target voltage after the first sensing time;
if yes, detecting whether the bit line voltage of the memory cell to be programmed is higher than the second target voltage after the second sensing time, if yes, stopping programming the memory cell to be programmed, and if not, repeating the above steps until the bit line voltage of the memory cell to be programmed is higher than the second target voltage.
24. The memory of claim 23, the controller further configured to: and when the memory cell to be programmed is reprogrammed, increasing the programming voltage.
25. The memory of claim 24, the controller further configured to: and when the memory cell to be programmed is reprogrammed for multiple times, the programming voltage is gradually increased by the same stepping voltage.
26. The memory according to claim 13, wherein,
when reading the programmed memory cell to be read in the plurality of memory cells, the method is configured to:
applying a reading voltage to the memory cell to be read to enable the memory cell to be read to be conducted; and
and determining the storage state of the storage unit to be read after reading the sensing time, wherein the reading sensing time comprises reading temperature compensation time, the reading temperature compensation time is determined according to the temperature when the storage unit to be read is read, and the reading temperature compensation time and the second temperature compensation time used when the storage unit to be read is programmed have the same relation curve relative to the temperature.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111434128.5A CN114141295A (en) | 2021-11-29 | 2021-11-29 | Memory and programming method and reading method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111434128.5A CN114141295A (en) | 2021-11-29 | 2021-11-29 | Memory and programming method and reading method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114141295A true CN114141295A (en) | 2022-03-04 |
Family
ID=80388922
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111434128.5A Pending CN114141295A (en) | 2021-11-29 | 2021-11-29 | Memory and programming method and reading method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114141295A (en) |
-
2021
- 2021-11-29 CN CN202111434128.5A patent/CN114141295A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10811098B2 (en) | Programming of memory devices in response to programming voltages indicative of programming efficiency | |
| US7965562B2 (en) | Predictive programming in non-volatile memory | |
| CN101711414B (en) | Non-volatile memory and method for predictive programming | |
| US8971126B2 (en) | Charge loss compensation methods and apparatus | |
| US7551483B2 (en) | Non-volatile memory with predictive programming | |
| US20020027233A1 (en) | Semiconductor device, microcomputer and flash memory | |
| US9318210B1 (en) | Word line kick during sensing: trimming and adjacent word lines | |
| US9583207B2 (en) | Adaptive data shaping in nonvolatile memory | |
| US20160078958A1 (en) | Single Ended Word Line and Bit Line Time Constant Measurement | |
| CN111316364B (en) | Fine setting determination on memory devices | |
| US20210286722A1 (en) | Configurable trim settings on a memory device | |
| US8509001B2 (en) | Adaptive write procedures for non-volatile memory | |
| US7940117B2 (en) | Voltage generation circuit and flash memory device including the same | |
| CN113168879B (en) | Open block based read offset compensation in read operations of memory devices | |
| CN114141295A (en) | Memory and programming method and reading method thereof | |
| KR102119179B1 (en) | Semiconductor device and operating method thereof | |
| CN111462799B (en) | Reading method and device of memory and storage system | |
| CN105575432A (en) | Data reading method of split gate type double-bit memory cell flash memory | |
| CN112292729A (en) | Split gate flash memory cell with improved read performance | |
| JP7511689B2 (en) | Memory devices and their operation | |
| KR20190033429A (en) | Semiconductor storage device and method for controlling semiconductor storage device | |
| WO2005017910A1 (en) | Non-volatile semiconductor storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |