CN114141283A

CN114141283A - Memory, memory control method and system

Info

Publication number: CN114141283A
Application number: CN202111160079.0A
Authority: CN
Inventors: 张君敬; 陈立刚; 刘江
Original assignee: Xi'an Geyi Anchuang Integrated Circuit Co ltd; GigaDevice Semiconductor Beijing Inc
Current assignee: Xi'an Geyi Anchuang Integrated Circuit Co ltd; GigaDevice Semiconductor Beijing Inc
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2022-03-04

Abstract

A memory, a memory control method and a corresponding system are disclosed. The memory includes: an array of memory cells; and a memory cell array operation module including: the read operation module is enabled in response to the memory receiving a memory cell array read instruction and is used for performing read operation on the memory cell array; the erasing operation module is enabled in response to the memory receiving a memory cell array erasing instruction and is used for carrying out erasing operation on the memory cell array; and a program operation module enabled in response to the memory receiving the memory cell array program instruction and for performing a program operation on the memory cell array. Through the independently arranged read operation, programming operation and erasing operation control modules, and enabling the read operation, programming operation and erasing operation control modules only during the period of receiving the corresponding instruction and executing the instruction, the invention can reduce the number of logic control circuits which need to be enabled when executing the operation instruction of the memory array, thereby reducing the overall power consumption of the memory.

Description

Memory, memory control method and system

Technical Field

The present disclosure relates to the field of memories, and in particular, to a memory, a memory control method, and a corresponding system.

Background

Flash memory (Flash) is now widely used due to its high storage density, high reliability and low power consumption. The flash memory includes NAND flash memory and NOR flash memory. NOR flash memory, also called code type memory, is generally used In conjunction with a microcontroller, supports In-chip execution (XIP), and has wide application In the fields of automotive electronics, wearable devices, smart home appliances, home medical devices, and the like. NAND flash memory is widely used in various memory cards, usb disks, SSDs, emmcs, and other large-capacity devices. As the performance and integration of devices are improved and the characteristics of distributed applications are improved, it is inconvenient to replace batteries or frequently charge the batteries. Therefore, how to prolong battery life and reduce device power consumption is a major challenge facing flash memory applications.

Disclosure of Invention

One technical problem to be solved by the present disclosure is to provide an improved memory, a memory control method and a corresponding system. The memory of the present invention may include independently provided read, program, and erase operation modules, and each operation module is enabled only when a corresponding instruction is received. Thereby reducing the number of logic control circuits that need to be enabled when executing memory array operation instructions, thereby reducing the overall power consumption of the memory.

According to a first aspect of the present disclosure, there is provided a memory comprising: an array of memory cells; and a memory cell array operation module, the operation module including: a read operation module enabled in response to the memory receiving a memory cell array read instruction and configured to perform a read operation on the memory cell array; an erase operation module enabled in response to the memory receiving a memory cell array erase instruction and configured to perform an erase operation on the memory cell array; and a program operation module enabled in response to the memory receiving a memory cell array programming instruction and for performing a program operation on the memory cell array.

Optionally, the read operation module is disabled in response to completion of the read operation execution, the erase operation module is disabled in response to completion of the erase operation execution, and the program operation module is disabled in response to completion of the program operation execution.

Optionally, the read operation module includes: the read voltage pump is used for generating voltage required to be used in read operation; and a read control circuit for controlling a data read operation of the memory cell array.

Optionally, the read control circuit includes: and a read operation enable signal circuit for enabling control of a voltage used in a read operation.

Optionally, the read voltage pump is enabled in a verify sub-operation of an erase operation and/or a program operation.

Optionally, the program operation module includes: a program voltage pump for generating a voltage to be used in a program operation; and a program control circuit for controlling a data program operation of the memory cell array.

Optionally, the erase operation module includes: an erasing voltage pump for generating a voltage to be used in an erasing operation; and an erase control circuit for controlling a data erase operation of the memory cell array.

Optionally, the program voltage pump is enabled in a soft program sub-operation of the erase operation.

Optionally, the memory further includes: a power manager; and an instruction decoder for decoding the instruction data,

the power supply manager can supply power to the instruction decoder in a standby state, the power supply manager responds to the reading instruction of the storage unit array to supply power to the reading operation module, the power supply manager responds to the programming instruction of the storage unit array to supply power to the programming operation module, and the power supply manager responds to the erasing instruction of the storage unit array to supply power to the erasing operation module.

Optionally, the power manager is configured to: in response to receiving a low power state instruction, ceasing power to the instruction decoder to enter a low power state; and restoring power to the instruction decoder to return to the standby state in response to receiving a chip strobe signal.

According to a second aspect of the present disclosure, there is provided a memory control method including: enabling a read operation module in a storage unit array operation module after the memory receives a storage unit array read instruction, wherein the read operation module performs read operation on the storage unit array; enabling a programming operation module in the memory cell array control module after the memory receives a memory cell array programming instruction, wherein the programming operation module performs programming operation on the memory cell array; and enabling an erasing operation module in the storage unit array control module after the storage receives a storage unit array erasing instruction, wherein the erasing operation module carries out erasing operation on the storage unit array.

According to a third aspect of the present disclosure, there is provided a system comprising: a host controller; an interface bus; and a memory according to the first aspect coupled to a host controller by the interface bus.

Therefore, the memory of the invention reduces the size of a circuit which needs to be participated when each memory array operation instruction is executed by using the read, program and erase operation modules which are independently arranged and can be independently enabled and disabled, thereby further reducing the overall power consumption of the memory chip.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent by describing in greater detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.

FIG. 1 shows a simplified schematic diagram of a system including a memory according to one embodiment of the invention.

Fig. 2 shows a composition diagram of a related art memory.

FIG. 3 illustrates a schematic diagram of the composition of a memory according to one embodiment of the invention.

FIG. 4 shows a state switching diagram of a memory according to one embodiment of the invention.

FIG. 5 is a timing diagram illustrating entry from a standby state to a read state according to one embodiment of the present invention.

Detailed Description

Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

Various embodiments will be described in more detail with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the present disclosure, like reference numerals denote like parts in the respective drawings and embodiments of the present invention.

It is noted that the drawings are simplified schematic diagrams and are therefore not necessarily drawn to scale. In some instances, various portions of the drawings may have been exaggerated to more clearly illustrate certain features of the illustrated embodiments.

It is further noted that in the following description, specific details are set forth to facilitate an understanding of the invention, however, the invention may be practiced without some of these specific details. Additionally, it is noted that well-known structures and/or processes may be described only briefly, or not at all, in order to avoid obscuring the present disclosure with unnecessary well-known details.

It should also be noted that in some instances, it will be apparent to those skilled in the relevant art that elements (also referred to as features) associated with one embodiment described may be used alone or in combination with other elements of another embodiment unless specifically stated otherwise.

Various embodiments of the present invention will be described in detail below with reference to the drawings, and for ease of understanding, an application environment of the present invention will first be described with reference to fig. 1.

FIG. 1 shows a simplified schematic of a system including a non-volatile memory according to one embodiment of the invention. The system 10 may be implemented as an electronic device, and the device 10 may include a host 200 and a memory 300 as shown, and communicate via a bus 100.

Here, the host 200 refers to a part that realizes a key function of the device 10, that is, a main part of the device 10, and the host 200 (or the device 10) may be any appropriate electronic device. In one embodiment, the apparatus 10 may be an electronic device including, but not limited to, for example, portable electronic devices such as mobile phones, tablets, wearable devices (e.g., TWS headsets), and laptop computers or non-portable electronic devices such as desktop computers, gaming consoles, televisions, set-top boxes, and projectors, and even industrial internet of things devices such as independently located sensors. At this time, the memory 300 may be a device providing a storage service for the independent electronic apparatus.

In other embodiments, the apparatus 10 may also be an electronic device with relatively independent functions (these electronic devices are often key devices that make up an electronic device), such as a stand-alone smart screen, a master control chip, a camera assembly, and the like. These electronic devices typically need to be assembled, for example, a smart screen to a cell phone, in order to provide services to a consumer (e.g., a user purchasing the cell phone). At this time, the memory 300 may be a device that provides necessary storage services for the electronic device.

Here, the host 200 may be implemented as or include a microcontroller, a microprocessor, an Application Specific Integrated Circuit (ASIC), or an Application Specific Standard Product (ASSP), and is coupled to the memory 300 as a slave device via the bus 100 as shown. Here, the bus 100 may be implemented as a Serial Peripheral Interface (SPI) bus, for example, and includes a plurality of

connection lines

101 and 104 as shown to implement the transmission of instructions, addresses and data, so as to read out and execute the codes stored in the memory 300, and to perform erasing and writing, such as firmware over-the-air upgrading, when necessary.

In the illustrated example, the bus 100 may include at least a data input line 101, a data output line 102, a clock line 103, and a chip strobe line 104. In which data signals, which may include sequences of instructions and addresses, generated by host 200 and received by memory 300, are transmitted on data-in line 101. A data-out line 102 carries signals generated by the memory 300 and received by the host 200, such as data read from the memory 300, e.g., code executable on the host 200. The clock line 103 is used for transmitting the clock signal generated by the host 200 to the memory 300, thereby realizing the synchronous data transmission between the two parties. When data transmission is required between the host 200 and the memory 300, the chip strobe signal on the chip strobe line 104 is asserted, e.g., low. When the data transmission is completed, the chip strobe signal on the chip strobe line 104 is set to an inactive level, e.g., a high level. Although not shown, it should be understood that the bus 100 may also enable connection of the host 200 to other slave or peripheral devices, which may be provided with other chip strobe lines.

Host 200 and memory 300 may each include pins for making the connections described above. In a preferred embodiment, the memory 300 may be implemented as a flash memory device with an SPI interface, in particular NOR flash memory and NAND flash memory, capable of sequential access of data via a serial interface (pin) and suitable for many applications such as voice, image, program code and data storage. In particular, memory 300 can be enabled (e.g., a defined active "assert" signal) by a chip strobe signal received on a Chip Strobe (CS) pin, and data access can be achieved via a data in (SI) pin, a data out (SO) pin, and a Clock (CLK) pin.

The memory circuit 300 may include input and output interfaces for external connection, including a data input interface, a data output interface, a clock interface, and a chip strobe interface, and the input and output interfaces may be generally implemented with pins including an SI pin, an SO pin, a CLK pin, and a CS pin, wherein the SI pin corresponds to the data input interface, the SO pin corresponds to the data output interface, the CLK pin corresponds to the clock interface, and the CS pin corresponds to the chip strobe pin/interface. The pins can each exchange data with the outside, for example, a host, by using the data input line 101, the data output line 102, the clock line 103 and the chip strobe line 104 included in the bus 100 shown in fig. 1, particularly the SPI bus, so as to realize data reading, erasing or writing under the control of the host.

It is to be understood that, although the SI pin, the SO pin, the CLK pin, and the CS pin are collectively referred to as an input-output interface, in actual operation, the SI pin, the CLK pin, and the CS pin may be designated for acquiring an external signal; the SO pin is designated for outputting data to the outside, such as program codes read from the memory 300 or status signals registered in registers inside the memory 300. Further, the SI pin, the CLK pin, and the CS pin are each used to acquire signals of different properties from the outside. Specifically, the instruction sent by the host 200 to the memory 300 may be an operator, the operator including a plurality of bits (e.g., 8 bits), and the SI pin sequential fetch operator. The instruction fetched from the SI pin is generally not directly available for control of the memory, but needs to be translated into a control instruction recognizable in the memory by decoding means (e.g. via the instruction decoder 331 in fig. 2). The CLK pin is used to receive a clock signal (e.g., a clock pulse with a specific frequency) from the host for data synchronous transmission, for example, the host 200 sends data and the memory 300 receives data on the rising edge of the clock signal. The CS pin then acquires a chip strobe signal from host 200, which may be a strobe or an active level that lasts for a predetermined time (e.g., when the chip strobe signal is low, memory 300 is able to receive clocks and data from host 200, and when the chip strobe signal is high, memory 300 ignores the clocks and data on clock line 103 and data input line 101), and may generally modify the operation inside the memory directly based on the chip strobe signal.

Fig. 2 shows a composition diagram of a related art memory. The memory 300 includes an input/output buffer 211, a power manager 221, a voltage pump 222, an ID register 251, an instruction decoder 231, a controller 232, a memory array 241, a column decoder 242, a row decoder 243, and a readout circuit 245. The memory array 241 includes a plurality of memory cells arranged in an array and addressable by word lines and bit lines. The memory cell may be a transistor having a floating gate or an insulating layer capable of trapping charges. The memory cell also includes a substrate, a source, a drain, and a control gate. The floating gate and the substrate are separated by a tunneling insulating layer, and the floating gate and the control gate are separated by an insulating layer. The threshold voltage of a transistor is related to the amount of charge trapped in the floating gate. When the floating gate has a large amount of trapped charge, the memory cell stores logic 0, and when the floating gate does not have trapped charge, the memory cell stores logic 1. The row decoder 243 is used to select a word line according to an address. The column decoder 242 is used to select a bit line according to an address. The sense circuit 245 is used to perform read operations and verify operations of the storage array 241. The power manager 221 is used to power the voltage pump 222, the command decoder 231, the controller 232, the memory array 241, the column decoder 242, the row decoder 243, and the sensing circuit 245. The ID register 251 is used to store information such as a memory ID and a manufacturer ID of the memory. The memory 300 also includes an internal clock for providing a clock signal for operation of the memory array 241. Accordingly, the clock signal on clock line 103 may be referred to as an external clock. The charge pump 222 is used to provide voltages for the operation of the memory array 241. The charge pump 222 may include a plurality of charge pump circuits for generating voltages required for a read operation, a program operation, and an erase operation, respectively.

With further miniaturization of portable devices and wearable devices, and the popularity of distributed devices such as internet of things applications, it is expected that memory will further reduce power consumption. A common memory (e.g., a low power NOR flash memory) utilizes the same controller to execute all memory array operation instructions, including read instructions, program instructions, and erase instructions. The control module is implemented as a logic control circuit including a large number of devices due to the need for simultaneous read, program and erase operation control. When the logic control circuit executes the instruction operation, the devices contained in the circuit still have certain leakage current even though the devices are not gated, so that the power consumption of the memory becomes large.

To this end, the present invention provides a memory including independently arranged read, program and erase operation control modules. These modules may be enabled only when a corresponding instruction is received, and disabled for other periods. Thereby reducing the number of logic control circuits that need to be enabled when executing memory array operation instructions, thereby reducing the overall power consumption of the memory.

FIG. 3 illustrates a schematic diagram of the composition of a memory according to one embodiment of the invention. The memory 300 shown in fig. 3 includes an input/output buffer 311, a power manager 321, an operation block, an ID register 351, an instruction decoder 331, a memory array 341, a column decoder 342, a row decoder 343, and a readout circuit 345. However, unlike fig. 2, in the memory shown in fig. 3, the operation modules include a read operation module, an erase operation module, and a program operation module provided for a read operation, an erase operation, and a program operation, respectively, and may function as, for example, the controller 332 and the voltage pump 322 shown in fig. 2 as a whole and may each include a control circuit section and a voltage pump section.

The memory array 341 includes a plurality of memory cells arranged in an array and addressable by word lines and bit lines. The row decoder 343 is used to select a word line according to an address. The column decoder 342 is used to select a bit line according to an address. The sense circuit 345 is used to perform read and verify operations of the memory array 341. The data acquired from the input/output interface may be temporarily stored in the input/output buffer 311 and further transferred to the instruction decoder 331. The data input line 101 and the data output line 102 support a serial protocol. For example, in a read operation, data received via the data input line 101 to be written to the memory array 341 is first stored in the shift register of the input-output buffer 311 and then moved to the data register. Instructions received via data-in line 101 are first stored in a shift register of input-output buffer 311 and then provided to instruction decoder 331.

In some embodiments, the signals obtained from the SI pin, the CLK pin, and the CS pin may be buffered in a data input buffer, a clock buffer, and a chip strobe signal buffer, respectively, in the input-output buffer 311. Accordingly, a data output buffer may be further included in the input/output buffer 311 for buffering data to be output via the SO pin.

The instruction decoder 331 is configured to read an instruction signal received from the SI pin from the data input buffer of the input/output buffer 311, and decode the instruction signal into an internal instruction that can be executed by the memory. The internal command sends a control signal to the power manager 321, and the power manager 321 may supply power to the read operation module, the erase operation module, and the program operation module in response to the control signal.

Although not shown in the figures, the memory 300 may include a power interface for receiving an external power source, such as a pin for receiving an external voltage VCC (e.g., a first voltage), for example, which is supplied with power from a power supply device of a system (e.g., the electronic apparatus 10), and further, the memory 300 may further include a pin for connecting to a system ground. The input/output interface of the memory 300 can normally operate directly at an external voltage VCC, while the operation module, the command decoder 331, the memory array 341, the column decoder 342, the row decoder 343, the readout circuit 345, and the like normally operate at a voltage different from VCC (i.e., an operation voltage VDD of the memory, for example, a second voltage), and VDD is usually lower than VCC, so that a power manager 321 for supplying the operation voltage VDD to the components in the memory is required. In other embodiments, the external voltage VCC may be the same as the memory operating voltage VDD. The power manager 321 may be used to power various components operating at a VDD voltage.

As shown in fig. 3, the read operation module may perform a read operation on the memory cell array (the memory module in fig. 3) based on the memory cell array read instruction, for example, with the help of the column decoder 342, the row decoder 343, and the readout circuit 345 of the memory module, to realize data readout from the specified location of the memory array 341.

The read operation module may include a read control circuit 3321 and a read voltage pump 3221. The read control circuit 3321 may be used to control data read operations of the memory cell array. Specifically, in a read operation, when a voltage is applied, when the application is stopped, and the timing of the voltage requires control by an enable signal. To this end, the read control circuit 3321 may include a read operation enable signal circuit for enabling control of voltages used in a read operation, i.e., providing these enable signals. Further, the read control circuit 3321 includes a state machine that implements logical control of the various steps of the read operation. Further, in the read operation, parameters such as a data read rate need to be configured. To this end, the read control circuit 3321 may further include a read operation parameter selection circuit for performing parameter configuration for the read operation.

The read voltage pump 3221 may be used to generate the voltages needed for the read operation. For example, read voltage pump 3221 may generate a read voltage applied to a selected word line, a turn-on voltage applied to unselected word lines (for NAND flash memory) or a negative voltage (for NOR flash memory).

The program operation module may perform a program operation on the memory cell array (the memory module in fig. 3) based on the memory cell array program instruction, for example, with the help of the column decoder 342 and the row decoder 343 of the memory module, to implement data writing to a specified location of the memory array 341.

The program operation module may include a program control circuit 3322 and a program voltage pump 3222. The program control circuit 3322 may be used to control data write operations to the memory cell array. Specifically, in the programming operation, the magnitude and timing of the applied voltage also need to be controlled by the enable signal. To this end, the program control circuit 3322 may include a program operation enable signal circuit for enabling control of a voltage used in a program operation. Further, the program control circuit 3322 also includes a state machine that implements logical control of the steps of the program operation. Further, in a programming operation, parameters such as programming several bytes at a time may also be configured. The program control circuitry 3322 may also include program operation parameter selection circuitry for parameter configuration of the program operation.

The program voltage pump 3222 may be used to generate the voltages used in the program operation. More specifically, programming memory cells also involves the participation of multiple voltages. For example, in a NOR flash memory program operation, a word line program voltage is applied to a selected word line, and a bit line program voltage is applied to a selected bit line, thereby implementing 0 writing of a target memory cell. In the programming operation of the NAND flash memory, a programming voltage is applied to a word line (selected word line) corresponding to a target page, that is, a positive voltage (for example, 20V) may be applied to the control gates of all transistors in the page, and a programming turn-on voltage is applied to unselected word lines. Accordingly, a program enable voltage (e.g., ground voltage) and a program inhibit voltage (e.g., a positive voltage of 2.5V) are applied to the selected bit lines and the unselected bit lines, respectively, according to the distributions of the

target data

0 and 1. After the bit line corresponding to the memory cell is applied with the programming enable voltage, electrons enter the floating gate through the insulating layer under the attraction of the positive voltage applied to the control gate, and the writing of the memory cell 0 is completed. In both NOR and NAND implementations, the program voltage pump 3222 may be used only to generate the word line program voltage, bit line program voltage, program on voltage, program inhibit voltage. In some embodiments, the program operation further includes a verify sub-operation after the program voltage applying step, for example, reading the programmed memory cell to verify that the data is correctly stored. In this case, read charge pump 3221 is also called to generate the voltages required on the selected word line and the unselected word lines, thereby completing the verify sub-operation included in the program operation.

The operation module further includes an erase operation module, which can perform an erase operation on the memory cell array based on the memory cell array erase command, for example, with the help of the column decoder 342 and the row decoder 343 of the memory module, to erase data at a specified location of the memory array 341.

The erase operation module may include an erase control circuit 3323 and an erase voltage pump 3223. The erase control circuit 3323 may be used to control data erase operations of the memory cell array. In particular, the selection of the magnitude and application time of the erase voltage and the setting of the relevant parameters are also involved in the erase operation. To this end, the erase control circuit 3323 may include an erase operation enable signal circuit for enabling control of a voltage used in an erase operation, and an erase operation parameter selection circuit for parameter-configuring the erase operation. Further, the erase control circuit 3323 also includes a state machine that implements logical control of the steps of the erase operation.

Erase voltage pump 3223 may be used to generate the voltages needed for an erase operation. For example, for NAND flash, erase voltage pump 3223 is used to generate a positive voltage of up to 20V applied to the substrate; for NOR flash, the erase voltage pump 3223 includes a positive voltage pump for generating a positive voltage applied to the substrate and a negative voltage pump for generating a negative voltage applied to the word line. In some embodiments, the erase operation further includes a verify sub-operation after the erase voltage applying step, for example, reading the erased memory cell to verify whether the memory cell is in an erased state. In this case, read charge pump 3221 is also called to generate the voltages required on the selected word line and the unselected word lines, thereby completing the verify sub-operation included in the program operation. Further, in some NOR flash implementations, the erase operation also requires verifying whether the memory cell is over-erased, i.e., whether the threshold voltage of the memory cell is less than 0, and if the threshold voltage of the memory cell is less than 0, the threshold voltage needs to be raised to greater than 0 by soft programming. For this reason, the erase operation of the NOR flash memory may further include a soft program sub-operation. At this point, program charge pump 3222 also needs to be called to generate the required voltage, e.g., a word line program voltage.

The read control circuit 3321, the program control circuit 3322 and the erase control circuit 3323 shown in fig. 3 can achieve the same functions of the controller shown in fig. 2, and the read voltage pump 3221, the program voltage pump 3222 and the erase voltage pump 3223 can achieve the same functions of the charge pump shown in fig. 2, but are different in that the above-described circuits/voltage pumps are each independently provided, in other words, they may not be simultaneously enabled. Therefore, the memory can only enable the corresponding module to operate according to the specific instruction received from the outside, and the leakage current caused by enabling unnecessary circuits is avoided, so that the power consumption level of the memory chip is reduced.

It will be appreciated that read control circuit 3321, program control circuit 3322, and erase control circuit 3323 may be general purpose processors, DSPs, ASICs, FPGAs, or other programmable logic devices, discrete gate or transistor logic, discrete hardware components, or any combinations thereof. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

FIG. 4 shows a state switching diagram of a memory according to one embodiment of the invention. As shown, the operating states of the memory 300 may include a standby state (standby), a low power consumption state (PWD), and three separate active states: READ state (READ), program state (PGM), and ERASE state (ERASE).

The following table lists the enable and disable conditions for various states for each component in memory 300.

TABLE 1

"Enable" means that the component is in a state that allows use. "disabled" means that the component is in a state where use is not permitted. For example, the component is set in a state of permitting use by supplying power, and the component is set in a state of not permitting use by stopping supplying power.

In the standby state, the memory 300 may recognize an arbitrary instruction of the host 200. In the standby state, if there is no data transmission between the host 200 and the memory 300, the chip strobe signal is maintained at an inactive level. Compared with the prior art, the memory of the invention has fewer modules which are enabled in the standby state, the voltage pump and the control circuit (such as the read, program and erase control module shown in fig. 3) can be in the disabled state, and only the power supply of the instruction decoder, the input/output buffer and the ID register is reserved. In the standby state, an instruction partially requiring no memory array involvement, such as a read instruction for retrieving information from an ID register, can be directly executed.

When the memory further receives an operation command for the memory cell array in the standby state, the memory may enter a corresponding READ state (READ), program state (PGM), and ERASE state (ERASE) according to the type of the received command.

When the host 200 needs to send an operation command of the memory cell array to the memory 300, the host 200 sets the chip strobe signal to an active level, the memory 300 receives a command or data through the data input line SI and sets the busy signal to be active, and causes the power manager 321 to enable the corresponding operation module according to the decoding result of the command decoder 331, thereby entering one of a READ state (READ), a program state (PGM), and an ERASE state (ERASE).

The various states and state transitions involved in the memory of the present invention are described below in conjunction with fig. 3-4, and the subsequent state transition timing diagrams.

As described above in conjunction with table 1, in the standby state, the read operation module (the read control circuit 3321 and the read charge pump 3221), the program operation module (the program control circuit 3322 and the program charge pump 3222), and the erase operation module (the erase control circuit 3323 and the erase charge pump 3223) are all disabled.

In the standby state, when the chip strobe signal is active (e.g., pulled low) and an instruction for the memory cell array is received on the data input pin, the memory may enter a corresponding operating state from the standby state to perform an operation for the memory cell array.

FIG. 5 is a timing diagram illustrating entry from a standby state to a read state according to one embodiment of the present invention. First, a chip strobe signal of a low level is received on the CS pin of the memory, and then an input command of 8 bits is received on the SI pin. The instruction is buffered by the input/output buffer 311 and then provided to the instruction decoder 331. The instruction decoder 331 then decodes the received 8-bit instruction, recognizes that the input instruction is a read instruction read _ cmd for performing a read operation of the memory cell array, and provides the recognized result to the power manager 321. The power manager 321 decides to enable and supply power to the memory module, the read control circuit 3321, and the read charge pump 3221 based on the recognition result. As shown in fig. 5, at the passage t_RAfter the processing time of (3), the read control circuit 3321 and the read charge pump 3221 enter an operable state, whereby the memory enters a read state, and the current flowing into the memory is from I in a standby state_CC1Become in the read state_CC3. Subsequently, the read control circuit 3321 and the read charge pump 3221 control the memory array 341, the column decoder 342, the row decoder 343, and the readout circuit 345 to perform corresponding operations according to the read instruction (and subsequent related instructions, if any), thereby implementing reading of the target memory content. After the execution of the instructions described above is completed, the memory returns to standby mode, read control circuit 3321 and read charge pump 3221 are again disabled, and current is also driven from I_CC3Fall back to I_CC1。

Similarly, the program operation module (the program control circuit 3322 and the program charge pump 3222) is enabled under the control of the power manager 321 based on the decoded recognition result after the memory receives the memory cell array program instruction, so that the memory enters the program state and the current flowing into the memory is from the I of the standby state_CC1I changed to programmed state_CC4. The enabled program control circuit 3322 and the program charge pump 3222 are used to perform a program operation on the memory cell array. As previously described, a programming operation may involve a verify sub-operation. In this verify sub-operation, the read voltage pump 3221 may be separately enabled for generating the corresponding voltages. Thus in table 1, read voltage pump 3221 is shown as being enabled in the programmed state. The enabling may be entirelyEnable in a program operation, but preferably only in a corresponding verify sub-operation. After all programming operations are completed, the memory returns to standby mode, and program control circuit 3322 and program charge pump 3222 (and optionally read voltage pump 3221 that is enabled) are re-disabled.

The erase operation module (erase control circuit 3323 and erase charge pump 3223) is enabled under the control of the power manager 321 based on the decoded recognition result after the memory receives the memory cell array erase command, whereby the memory enters an erase state and the current flowing into the memory is from I of the standby state_CC1I changed to the erased state_CC5. The enabled erase control circuit 3323 and erase charge pump 3223 are used to perform an erase operation on the array of memory cells. As previously described, the erase operation may involve a verify sub-operation. In this verify sub-operation, the read voltage pump 3221 may be separately enabled for generating the corresponding voltages. Further, in an application scenario of NOR flash memory, the erase operation may involve a soft program sub-operation. In the soft program sub-operation, the program voltage pump 3222 may be separately enabled for generating a corresponding voltage. Thus in table 1, read voltage pump 3221 and program voltage pump 3222 are shown as being enabled in the erased state. The above-described enabling may be enabling in the entire erase operation, but is preferably only enabling in various corresponding verify sub-operations and soft program sub-operations. After the entire erase operation is completed, the memory returns to standby mode, and erase control circuit 3323 and erase charge pump 3223 (and optionally read voltage pump 3221 and program voltage pump 3222) are re-disabled.

Further, as shown in fig. 4, in the standby state, the memory 300 can directly enter the low power consumption state according to the low power consumption state instruction PWD _ cmd. In the low power consumption state, the power manager 321 may disable the memory modules, i.e., the memory array 341, the column decoder 342, the row decoder 343, and the readout circuit 345 (and the page buffer, etc. in some embodiments), thereby reducing the power consumption of the memory chip, and the current flowing into the memory flows from the I of the standby state_CC1Lower I to Low Power consumption State_CC2。

Any signal on the SI pin is ignored after transitioning to the low power state. When a valid chip strobe signal is received on the CS pin, for example, a low level valid signal is received (i.e., CS is pulled down), the memory in the low power consumption state may react to the chip strobe signal, thereby causing the memory to leave the low power consumption state and return to the standby state.

Although each operational block is shown in fig. 3 as including both control circuitry and a voltage pump, it should be understood that in some embodiments, only the logic control circuitry may be partitioned and still use a consolidated charge pump, e.g., a read operational block including only read control circuitry and not a separate read charge pump, and still fall within the scope defined by the present invention.

The present invention may also be embodied as a memory control method including: enabling a read operation module in a storage unit array operation module after the memory receives a storage unit array read instruction, wherein the read operation module performs read operation on the storage unit array; enabling a programming operation module in the memory cell array control module after the memory receives a memory cell array programming instruction, wherein the programming operation module performs programming operation on the memory cell array; and enabling an erasing operation module in the storage unit array control module after the storage receives a storage unit array erasing instruction, wherein the erasing operation module carries out erasing operation on the storage unit array.

Further, the present invention may also be embodied as a system, such as the electronic device shown in fig. 1, comprising a host, an interface bus, and a memory as described above. The memory is coupled to the host through its connection to the interface bus via its input-output interface (e.g., SPI interface).

The memory, the memory control method, and the system according to the present invention have been described in detail above with reference to the accompanying drawings.

The present disclosure updates the internal structure of a memory circuit (particularly, a flash memory chip) from the viewpoint of reducing power consumption, and divides a control circuit based on the type of an instruction. Aiming at different instructions, only a specific circuit required by the instruction is started, and other operating circuits are forbidden, so that a memory operating device is ensured not to be unnecessarily started, and the leakage current and the power consumption of the memory in a working state are reduced. Further, the detailed division of the active state avoids the need for turning on the charge pump and control circuitry in the standby state, thereby further reducing standby power consumption and increasing battery life.

Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A memory, comprising:

an array of memory cells; and

a memory cell array operation module, the operation module comprising:

a read operation module enabled in response to the memory receiving a memory cell array read instruction and configured to perform a read operation on the memory cell array;

a program operation module enabled in response to the memory receiving a memory cell array programming instruction and for performing a program operation on the memory cell array; and

an erase operation module enabled in response to the memory receiving a memory cell array erase instruction and configured to perform an erase operation on the memory cell array.

2. The memory of claim 1, wherein,

disabling the read operation module in response to completion of the read operation execution,

disabling the program operation module in response to the program operation execution completing, and

disabling the erase operation module is done in response to the erase operation execution.

3. The memory of claim 1, wherein the read operation module comprises:

the read voltage pump is used for generating voltage required to be used in read operation; and

and the read control circuit is used for controlling the data read operation of the memory cell array.

4. The memory of claim 3, wherein the read control circuit comprises:

and a read operation enable signal circuit for enabling control of a voltage used in a read operation.

5. The memory of claim 3, wherein the read voltage pump is enabled in a verify sub-operation of an erase operation and/or a program operation.

6. The memory of claim 1, wherein the program operation module comprises:

a program voltage pump for generating a voltage to be used in a program operation; and

and the programming control circuit is used for controlling the data programming operation of the memory cell array.

7. The memory of claim 1, wherein the erase operation module comprises:

an erasing voltage pump for generating a voltage to be used in an erasing operation; and

and the erasing control circuit is used for controlling the data erasing operation of the memory cell array.

8. The memory of claim 5, wherein the program voltage pump is enabled in a soft program sub-operation of an erase operation.

9. The memory of claim 1, further comprising:

a power manager; and

an instruction decoder for decoding the instruction data from the instruction data memory,

10. The memory of claim 9, wherein the power manager is to:

in response to receiving a low power state instruction, ceasing power to the instruction decoder to enter a low power state; and

in response to receiving a chip strobe signal, power to the instruction decoder is restored to return to the standby state.

11. A memory control method, comprising:

enabling a read operation module in a storage unit array operation module after the memory receives a storage unit array read instruction, wherein the read operation module performs read operation on the storage unit array;

enabling a programming operation module in the memory cell array control module after the memory receives a memory cell array programming instruction, wherein the programming operation module performs programming operation on the memory cell array; and

enabling an erasing operation module in the storage unit array control module after the storage receives a storage unit array erasing instruction, wherein the erasing operation module carries out erasing operation on the storage unit array.

12. A system, comprising:

a host controller;

an interface bus; and

the memory of claims 1-10, coupled to a host controller through the interface bus.