CN114138701B - I2C signal adjusting method, device, equipment and readable storage medium - Google Patents
I2C signal adjusting method, device, equipment and readable storage medium Download PDFInfo
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Abstract
The invention discloses an I2C signal adjusting method, which comprises the following steps: analyzing the received I2C signal adjustment request to obtain a target link to be signal adjusted; detecting an I2C signal waveform of the target link; judging whether the waveform of the I2C signal is monotonous; and if not, carrying out capacity value adjustment operation on the entity MOS tube in the target link. By applying the I2C signal adjusting method provided by the invention, the workload of signal adjustment is greatly reduced, the adjusting efficiency is greatly improved, the signal adjusting effect is improved, and the signal quality is effectively improved. The invention also discloses an I2C signal adjusting device, equipment and a storage medium, which have corresponding technical effects.
Description
Technical Field
The present invention relates to the field of signal adjustment technologies, and in particular, to a method, an apparatus, a device, and a computer-readable storage medium for adjusting an I2C signal.
Background
The I2C (Inter-Integrated Circuit) bus is a two-wire serial bus used to connect the microcontroller and its peripherals. The I2C bus is a bus standard widely used in the field of microelectronic communication control. The synchronous communication method is a special form of synchronous communication, and has the advantages of few interface lines, simple control mode, small device packaging form, high communication speed and the like. The I2C bus supports any IC (Integrated Circuit) manufacturing process, passing information between devices connected to the bus via a Serial Data (SDA) line and a Serial Clock (SCL) line. Each device has a unique address identification and can act as either a transmitter or a receiver.
When the I2C signal is found to be non-monotonic, the prior art typically starts with the resistor in the link, adjusts the resistance of the resistor and then makes the waveform as monotonic as possible. Sometimes, it is uncertain whether the resistance value should be adjusted to be larger or smaller, an attempt needs to be made by groping, and it is uncertain which resistance value is best to be modified, and there are more resistors in the link, which results in a complex signal adjusting process and low adjusting efficiency. The phenomenon of not adjusting after modifying the resistance value is improved, a slow step may still exist, and the signal adjusting effect is not good.
In summary, how to effectively solve the problems of complex signal adjustment process, low adjustment efficiency, poor signal adjustment effect, and the like is a problem that needs to be solved urgently by those skilled in the art at present.
Disclosure of Invention
The invention aims to provide an I2C signal adjusting method, which greatly reduces the workload of signal adjustment, greatly improves the adjusting efficiency, improves the signal adjusting effect and effectively improves the signal quality; it is another object of the present invention to provide an I2C signal conditioning apparatus, device and computer readable storage medium.
In order to solve the technical problems, the invention provides the following technical scheme:
an I2C signal conditioning method, comprising:
analyzing the received I2C signal adjustment request to obtain a target link to be signal adjusted;
detecting an I2C signal waveform of the target link;
judging whether the waveform of the I2C signal is monotonous;
and if not, carrying out capacity value adjustment operation on the entity MOS tube in the target link.
In a specific embodiment of the present invention, the performing a capacitance value adjustment operation on an entity MOS transistor in the target link includes:
switching an entity MOS tube in the target link from an access state to a short-circuit state;
judging whether the waveform of the I2C signal has changes or not;
and if so, switching the entity MOS tube from the short-circuit state to the access state, and carrying out capacity value adjustment operation on the entity MOS tube.
In an embodiment of the present invention, when it is determined that the I2C signal waveform is not monotonous, before switching the physical MOS transistor in the target link from the access state to the short-circuited state, the method further includes:
adjusting the series resistance value of the target link;
judging whether the I2C signal waveform is converted into a monotone waveform;
if not, the step of switching the entity MOS tube in the target link from the access state to the short-circuit state is executed.
In one embodiment of the present invention, detecting the I2C signal waveform of the target link includes:
the I2C signal waveform of the target link clock and data is probed.
In a specific embodiment of the present invention, switching the solid MOS transistor from the short-circuit state to the access state includes:
carrying out simulation operation on the entity MOS tube to obtain a simulation MOS tube;
correspondingly adding the simulation MOS tube to the original position in the target link before the entity MOS tube is short-circuited;
carrying out capacity value adjustment operation on the simulation MOS tube;
acquiring a target capacity value corresponding to the simulation MOS tube when the I2C signal waveform is converted into a monotone waveform;
switching the entity MOS tube from the short-circuit state to the access state so as to replace the simulation MOS tube with the entity MOS tube;
and setting the capacity value of the entity MOS tube as a target capacity value.
In an embodiment of the present invention, after setting the capacitance value of the solid MOS transistor as the target capacitance value, the method further includes:
acquiring a current actually measured I2C signal waveform;
judging whether the waveform of the actually measured I2C signal is monotonous;
if yes, recording the adjustment process and the adjustment result.
An I2C signal conditioning device, comprising:
the request analysis module is used for analyzing the received I2C signal adjustment request to obtain a target link to be adjusted by the signal;
the waveform detection module is used for detecting the I2C signal waveform of the target link;
the first judgment module is used for judging whether the waveform of the I2C signal is monotonous or not;
and the capacitance value adjusting module is used for performing capacitance value adjusting operation on the entity MOS tube in the target link when the I2C signal waveform is determined not to be monotonous.
In an embodiment of the present invention, the capacity adjustment module includes:
the state switching submodule is used for switching the entity MOS tube in the target link from an access state to a short-circuit state;
the first judgment submodule is used for judging whether the waveform of the I2C signal changes or not;
and the capacitance value adjusting submodule is used for switching the entity MOS tube from the short-circuit state to the access state and carrying out capacitance value adjusting operation on the entity MOS tube when the I2C signal waveform is determined to have variation.
An I2C signal conditioning device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the I2C signal conditioning method as described above when the computer program is executed.
A computer-readable storage medium having stored thereon a computer program which, when executed by a processor, carries out the steps of the I2C signal conditioning method as set forth above.
The I2C signal adjusting method provided by the invention analyzes the received I2C signal adjusting request to obtain a target link to be adjusted by a signal; detecting an I2C signal waveform of the target link; judging whether the waveform of the I2C signal is monotonous; and if not, carrying out capacity value adjustment operation on the entity MOS tube in the target link.
According to the technical scheme, after the I2C signal waveform of the target link needing I2C signal adjustment is detected, if the I2C signal waveform is not monotonous, the capacitance value of the solid MOS transistor in the target link is adjusted, and then the monotonicity adjustment of the I2C signal waveform is achieved. The number of the solid MOS tubes in the link is greatly reduced compared with the number of the resistors in the link, so that the capacity value adjusting direction of the MOS tubes is conveniently determined, the workload of signal adjustment is greatly reduced, the adjusting efficiency is greatly improved, the signal adjusting effect is improved, and the signal quality is effectively improved.
Accordingly, the present invention further provides an I2C signal adjusting apparatus, a device and a computer readable storage medium corresponding to the I2C signal adjusting method, which have the above technical effects and are not described herein again.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flowchart illustrating an implementation of a method for adjusting an I2C signal according to an embodiment of the present invention;
FIG. 2 is an equivalent circuit diagram of a MOS transistor according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating another embodiment of a method for adjusting an I2C signal according to the present invention;
FIG. 4 is a block diagram of a partial branch result of an I2C link according to an embodiment of the present invention;
FIG. 5 is a partial schematic diagram of an I2C link according to an embodiment of the present invention;
FIG. 6 is a high frequency small signal equivalent circuit diagram of a common source n-channel MOSFET in an embodiment of the present invention;
FIG. 7 is a block diagram of an I2C signal adjustment apparatus according to an embodiment of the present invention;
FIG. 8 is a block diagram of an I2C signal conditioning apparatus according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of an I2C signal adjusting device provided in this embodiment.
Detailed Description
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating an implementation of a method for adjusting an I2C signal according to an embodiment of the present invention, where the method may include the following steps:
s101: and analyzing the received I2C signal adjustment request to obtain a target link to be signal adjusted.
When the I2C signal in the I2C link needs to be adjusted, an I2C signal adjustment request is sent to the signal adjustment control center, and the I2C signal adjustment request comprises a target link to be signal adjusted. And the signal adjustment control center receives the I2C signal adjustment request, and analyzes the received I2C signal adjustment request to obtain a target link to be adjusted by the signal.
The signal conditioning control center may be a pre-configured processor capable of receiving an I2C signal conditioning request and responding to an I2C signal conditioning request.
S102: the I2C signal waveform of the target link is probed.
After the signal adjustment control center analyzes and obtains a target link to be signal adjusted, a device (device) endpoint capable of supporting an I2C signal waveform in the target link is searched, and the I2C signal waveform of the target link is detected at the corresponding device endpoint.
S103: it is determined whether the I2C signal waveform is monotonous, if not, step S104 is executed, and if so, step S105 is executed.
The signal integrity specification states that the signal waveform is monotonic. After the I2C signal waveform of the target link is detected, determining whether the I2C signal waveform is monotonous, if not, indicating that the I2C signal of the target link does not meet the signal integrity specification requirement, executing step S104, if so, indicating that the I2C signal of the target link meets the signal integrity specification requirement, and executing step S105.
S104: and carrying out capacity value adjustment operation on the entity MOS tube in the target link.
Referring to fig. 2, fig. 2 is an equivalent circuit diagram of a MOS transistor according to an embodiment of the present invention. The important role of the MOS transistor is isolation, and the isolation is important in worrying that a current of a previous pole leaks into a subsequent circuit, so that misjudgment is caused on the power-on timing sequence of a circuit system and the operation of a processor or a logic device, and finally the system cannot normally operate. Therefore, in practical circuitry, the role of isolation is very important. The capacitance value of the MOS transistor has influence on the I2C signal of the target link, but because the isolation effect of the MOS transistor cannot be directly removed, a proper capacitance value can be found to improve the signal quality.
When the I2C signal waveform of the target link is determined not to be monotonous, which indicates that the I2C signal of the target link does not meet the requirement of the signal integrity specification, the capacity value adjustment operation is carried out on the entity MOS tube in the target link.
S105: and outputting an I2C signal normal prompt message.
When the I2C signal waveform of the target link is determined to be monotonous, the I2C signal of the target link is shown to meet the signal integrity specification requirement, and the I2C signal is output to be normal prompt information, so that the user is prompted that the I2C signal of the target link meets the signal integrity specification requirement.
The monotonicity of the I2C signal waveform is adjusted by adjusting the capacitance value of the entity MOS tube in the target link. The number of the solid MOS tubes in the link is greatly reduced compared with the number of the resistors in the link, so that the capacity value adjusting direction of the MOS tubes is conveniently determined, the workload of signal adjustment is greatly reduced, the adjusting efficiency is greatly improved, the signal adjusting effect is improved, and the signal quality is effectively improved.
According to the technical scheme, after the I2C signal waveform of the target link needing I2C signal adjustment is detected, if the I2C signal waveform is not monotonous, the capacitance value of the solid MOS transistor in the target link is adjusted, and then the monotonicity adjustment of the I2C signal waveform is achieved. The number of the solid MOS tubes in the link is greatly reduced compared with the number of the resistors in the link, so that the capacity value adjusting direction of the MOS tubes is conveniently determined, the workload of signal adjustment is greatly reduced, the adjusting efficiency is greatly improved, the signal adjusting effect is improved, and the signal quality is effectively improved.
It should be noted that, based on the above embodiments, the embodiments of the present invention also provide corresponding improvements. In the following embodiments, steps that are the same as or correspond to those in the above embodiments may be referred to one another, and corresponding advantageous effects may also be referred to one another, which is not described in detail in the following modified embodiments.
Referring to fig. 3, fig. 3 is a flowchart of another implementation of a method for adjusting an I2C signal according to an embodiment of the present invention, where the method may include the following steps:
s301: and analyzing the received I2C signal adjustment request to obtain a target link to be signal adjusted.
S302: the I2C signal waveform of the target link clock and data is probed.
The I2C signal waveforms of the target link include the signal waveform of the clock (clk) signal and the signal waveform of the data (data) signal. And after analyzing the target link to be subjected to signal adjustment, the signal adjustment control center detects the I2C signal waveform of the target link clock and data. By detecting the signal waveform of the clock signal and the signal waveform of the data signal respectively, the evaluation of the I2C signal quality can be comprehensively carried out by combining the waveform conditions of the clock signal and the data signal.
Referring to fig. 4 and 5, fig. 4 is a partial branch result block diagram of an I2C link according to an embodiment of the present invention, and fig. 5 is a partial schematic diagram of an I2C link according to an embodiment of the present invention. The test points of the clock signal and the data signal of I2C in FIG. 4 are on a probe device (sensor), and the branch comprises two solid MOS tubes of MOS1 and MOS 2. Only one solid MOS transistor is included in fig. 5 for isolation.
S303: it is determined whether the I2C signal waveform is monotonous, if so, step S304 is performed, and if not, step S305 is performed.
S304: and outputting an I2C signal normal prompt message.
S305: and adjusting the series resistance value of the target link.
When the waveform of the I2C signal is determined not to be monotonous, the I2C signal of the target link does not meet the requirement of the signal integrity specification, and the adjustment operation of the series resistance value of the target link is attempted.
S306: it is determined whether the I2C signal waveform is converted into a monotone waveform, and if not, step S307 is executed, and if so, no processing is performed.
After the adjustment of the series resistance value of the target link is attempted, whether the waveform of the I2C signal is converted into a monotonic waveform is judged, if not, it is indicated that the I2C signal of the target link cannot meet the signal integrity specification through the series resistance value adjustment, step S307 is executed, if so, it is indicated that the I2C signal of the target link meets the signal integrity specification through the series resistance value adjustment, and no processing is performed.
S307: and switching the entity MOS tube in the target link from an access state to a short-circuit state.
The preset signal adjustment control center can switch the access state and the short-circuit state of the entity MOS tube in the target link according to the control requirement. If the waveform of the I2C signal obtained after the attempt to adjust the resistance value of the series resistor of the target link is still not a monotone waveform, it indicates that it is difficult to make the I2C signal of the target link meet the signal integrity specification through the resistance value adjustment of the series resistor, and the solid MOS transistor in the target link is switched from the access state to the short-circuit state, that is, the attempt is made to rework the solid MOS transistor in the target link and fly.
S308: and judging whether the waveform of the I2C signal is changed or not, if so, executing the step S309, and if not, outputting link abnormity prompting information.
After switching an entity MOS transistor in a target link from an access state to a short-circuit state, judging whether a waveform of an I2C signal changes, if so, indicating that a capacitive reactance can affect the signal quality of the I2C signal, executing a step S309, otherwise, indicating that the capacitive reactance cannot affect the signal quality of the I2C signal, and outputting link abnormity prompting information, thereby prompting a user to perform link detection.
S309: and switching the solid MOS tube from the short-circuit state to the access state, and adjusting the capacitance value of the solid MOS tube.
If the waveform of the I2C signal changes after the solid MOS transistor in the target link is switched from the access state to the short-circuit state, it is indicated that the capacitive reactance may affect the signal quality of the I2C signal, the solid MOS transistor is switched from the short-circuit state to the access state, and the capacitance value of the solid MOS transistor is adjusted, and the waveform is adjusted by adjusting the capacitance value of the solid MOS transistor, so that the signal quality of the I2C signal is improved.
Referring to fig. 6, fig. 6 is a high-frequency small-signal equivalent circuit diagram of a common-source n-channel MOSFET according to an embodiment of the present invention. When a signal is input from the port G, S, two capacitors exist in the link, one capacitor is an inter-stage capacitor CgsT between the G terminal and the S terminal and plays a similar filtering role, the other capacitor is a capacitor CgdT to the D terminal, the capacitor is used for signal transmission, the capacitor acts on signal quality, and the size of the capacitor has a large influence on the signal.
In a specific embodiment of the present invention, switching the solid MOS transistor from the short-circuit state to the access state may include the following steps:
the method comprises the following steps: carrying out simulation operation on the entity MOS tube to obtain a simulation MOS tube;
step two: correspondingly adding the simulation MOS tube to the original position in the target link before the entity MOS tube is short-circuited;
step three: carrying out capacity value adjustment operation on the simulation MOS tube;
step four: acquiring a target capacity value corresponding to the simulation MOS tube when the I2C signal waveform is converted into a monotone waveform;
step five: switching the solid MOS tube from a short-circuit state to an access state so as to replace the simulation MOS tube with the solid MOS tube;
step six: and setting the capacity value of the entity MOS tube as a target capacity value.
For convenience of description, the above six steps may be combined for illustration.
If there is a change in the waveform of the I2C signal after the solid MOS transistor in the target link is switched from the access state to the short-circuited state, it is indicated that the capacitive reactance may affect the signal quality of the I2C signal. The method comprises the steps of presetting simulation software, carrying out simulation operation on an entity MOS tube by utilizing the simulation software to obtain a simulation MOS tube, correspondingly adding the simulation MOS tube to an original position in a target link before the entity MOS tube is short-circuited, carrying out capacity value adjustment operation on the simulation MOS tube, obtaining a target capacity value corresponding to the simulation MOS tube when an I2C signal waveform is converted into a monotonic waveform, switching the entity MOS tube from a short-circuited state to an accessed state, replacing the simulation MOS tube by utilizing the entity MOS tube, and setting the capacity value of the entity MOS tube as a target capacity value. The capacitance value adjustment is carried out through the simulation MOS tube obtained by simulation of the simulation software, the convenience of the capacitance value adjustment is improved, damage to the entity MOS due to misoperation is avoided, and the signal adjustment efficiency is improved.
In an embodiment of the present invention, after setting the capacitance value of the solid MOS transistor as the target capacitance value, the method may further include the following steps:
the method comprises the following steps: acquiring a current actually measured I2C signal waveform;
step two: judging whether the waveform of the actually measured I2C signal is monotonous, if so, executing a step three, and if not, outputting re-simulation indication information;
step three: and recording the adjustment process and the adjustment result.
For convenience of description, the above three steps may be combined for illustration.
After the capacity value of the entity MOS tube is set as a target capacity value, acquiring a current actual measurement I2C signal waveform, judging whether the actual measurement I2C signal waveform is monotonous, if so, the current simulation result conforms to the actual condition, recording the current adjustment process and the adjustment result, otherwise, indicating that the current simulation result does not conform to the actual condition and simulation deviation possibly exists, and outputting re-simulation indication information, so that a user determines a proper capacity value by performing re-simulation. Therefore, effective verification of the influence of the capacity value adjustment on the signal quality is realized by carrying out upper-board real test on the selected most appropriate target capacity value. By recording the adjustment process and the adjustment result, the rule summary of capacity value adjustment is facilitated, and a reference basis is provided for subsequent signal adjustment.
Corresponding to the above method embodiments, the present invention further provides an I2C signal adjusting apparatus, and the I2C signal adjusting apparatus described below and the I2C signal adjusting method described above are referred to with each other.
Referring to fig. 7, fig. 7 is a block diagram of an I2C signal adjusting apparatus according to an embodiment of the present invention, where the apparatus may include:
the request analysis module 71 is configured to analyze the received I2C signal adjustment request to obtain a target link to be signal-adjusted;
a waveform detection module 72 for detecting the I2C signal waveform of the target link;
the first judging module 73 is used for judging whether the waveform of the I2C signal is monotonous;
and the capacitance adjusting module 74 is configured to perform a capacitance adjusting operation on the solid MOS transistor in the target link when it is determined that the I2C signal waveform is not monotonous.
According to the technical scheme, after the I2C signal waveform of the target link needing I2C signal adjustment is detected, if the I2C signal waveform is not monotonous, the capacitance value of the solid MOS transistor in the target link is adjusted, and then the monotonicity adjustment of the I2C signal waveform is achieved. The number of the solid MOS tubes in the link is greatly reduced compared with the number of the resistors in the link, so that the capacity value adjusting direction of the MOS tubes is conveniently determined, the workload of signal adjustment is greatly reduced, the adjusting efficiency is greatly improved, the signal adjusting effect is improved, and the signal quality is effectively improved.
In one embodiment of the present invention, the capacity adjustment module 74 includes:
the state switching submodule is used for switching the entity MOS tube in the target link from an access state to a short-circuit state;
the first judgment submodule is used for judging whether the waveform of the I2C signal changes or not;
and the capacitance value adjusting submodule is used for switching the entity MOS tube from a short-circuit state to an access state and carrying out capacitance value adjusting operation on the entity MOS tube when the I2C signal waveform is determined to have variation.
In one embodiment of the present invention, the apparatus may further include:
the resistance value adjusting module is used for adjusting the series resistance value of the target link before switching the entity MOS tube in the target link from the access state to the short-circuit state when the I2C signal waveform is determined not to be monotonously adjusted;
the second judging module is used for judging whether the I2C signal waveform is converted into a monotone waveform;
the state switching submodule is specifically a module for switching the solid MOS transistor in the target link from an access state to a short-circuit state when it is determined that the I2C signal waveform is not transformed into a monotonic waveform.
In one embodiment of the present invention, the waveform detection module 72 is a module for detecting the I2C signal waveform of the target link clock and data.
In an embodiment of the present invention, the capacity adjustment submodule includes:
the simulation unit is used for carrying out simulation operation on the entity MOS tube to obtain a simulation MOS tube;
the adding unit is used for correspondingly adding the simulation MOS tube to the original position in the target link before the entity MOS tube is short-circuited;
the capacitance value adjusting unit is used for adjusting the capacitance value of the simulation MOS tube;
the capacitance value acquisition unit is used for acquiring a target capacitance value corresponding to the simulation MOS tube when the I2C signal waveform is converted into a monotone waveform;
the replacing unit is used for switching the entity MOS tube from a short-circuit state to an access state so as to replace the simulation MOS tube with the entity MOS tube;
and the capacity value setting unit is used for setting the capacity value of the entity MOS tube as a target capacity value.
In one embodiment of the present invention, the apparatus may further include:
the waveform acquisition module is used for acquiring the current actually-measured I2C signal waveform after setting the capacity value of the entity MOS tube as a target capacity value;
the third judging module is used for judging whether the waveform of the actually measured I2C signal is monotonous;
and the result recording module is used for recording the current adjusting process and the adjusting result when the measured I2C signal waveform is confirmed to be monotonous.
Corresponding to the above method embodiment, referring to fig. 8, fig. 8 is a schematic diagram of an I2C signal adjusting apparatus provided in the present invention, where the apparatus may include:
a memory 332 for storing a computer program;
the processor 322 is configured to implement the steps of the I2C signal adjustment method of the above method embodiment when executing the computer program.
Specifically, referring to fig. 9, fig. 9 is a schematic diagram illustrating a specific structure of an I2C signal adjusting apparatus provided in this embodiment, the I2C signal adjusting apparatus may generate a larger difference due to different configurations or performances, and may include a processor (CPU) 322 (e.g., one or more processors) and a memory 332, where the memory 332 stores one or more computer applications 342 or data 344. Memory 332 may be, among other things, transient or persistent storage. The program stored in memory 332 may include one or more modules (not shown), each of which may include a sequence of instructions operating on a data processing device. Further, processor 322 may be configured to communicate with memory 332 to execute a series of instruction operations in memory 332 on I2C signal conditioning device 301.
The I2C signal conditioning device 301 may also include one or more power sources 326, one or more wired or wireless network interfaces 350, one or more input-output interfaces 358, and/or one or more operating systems 341.
The steps in the I2C signal adjustment method described above may be implemented by the structure of the I2C signal adjustment device.
Corresponding to the above method embodiment, the present invention further provides a computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the steps of:
analyzing the received I2C signal adjustment request to obtain a target link to be signal adjusted; detecting an I2C signal waveform of the target link; judging whether the waveform of the I2C signal is monotonous; and if not, carrying out capacity value adjustment operation on the entity MOS tube in the target link.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
For the introduction of the computer-readable storage medium provided by the present invention, please refer to the above method embodiments, which are not described herein again.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device, the apparatus and the computer-readable storage medium disclosed in the embodiments correspond to the method disclosed in the embodiments, so that the description is simple, and the relevant points can be referred to the description of the method.
The principle and the implementation of the present invention are explained in the present application by using specific examples, and the above description of the embodiments is only used to help understanding the technical solution and the core idea of the present invention. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.
Claims (10)
1. An I2C signal conditioning method, comprising:
analyzing the received I2C signal adjustment request to obtain a target link to be signal adjusted;
detecting an I2C signal waveform of the target link;
judging whether the waveform of the I2C signal is monotonous;
and if not, carrying out capacity value adjustment operation on the entity MOS tube in the target link.
2. The I2C signal adjusting method of claim 1, wherein performing a capacitance value adjustment operation on a solid MOS transistor in the target link comprises:
switching an entity MOS tube in the target link from an access state to a short-circuit state;
judging whether the waveform of the I2C signal has changes or not;
and if so, switching the entity MOS tube from the short-circuit state to the access state, and carrying out capacity value adjustment operation on the entity MOS tube.
3. The I2C signal conditioning method of claim 2, wherein when it is determined that the I2C signal waveform is not monotonous, before switching a physical MOS transistor in the target link from an access state to a shorted state, further comprising:
adjusting the series resistance value of the target link;
judging whether the I2C signal waveform is converted into a monotone waveform;
if not, the step of switching the entity MOS tube in the target link from the access state to the short-circuit state is executed.
4. The I2C signal conditioning method of claim 1, wherein probing the I2C signal waveform of the target link comprises:
the I2C signal waveform of the target link clock and data is probed.
5. The I2C signal adjusting method of claim 2 or 3, wherein switching the solid MOS transistor from the shorted state to the accessed state comprises:
carrying out simulation operation on the entity MOS tube to obtain a simulation MOS tube;
correspondingly adding the simulation MOS tube to the original position in the target link before the entity MOS tube is short-circuited;
carrying out capacity value adjustment operation on the simulation MOS tube;
acquiring a target capacity value corresponding to the simulation MOS tube when the I2C signal waveform is converted into a monotone waveform;
switching the entity MOS tube from the short-circuit state to the access state so as to replace the simulation MOS tube with the entity MOS tube;
and setting the capacity value of the entity MOS tube as a target capacity value.
6. The I2C signal adjusting method of claim 5, wherein after setting the capacitance of the solid MOS transistor to a target capacitance, further comprising:
acquiring a current actually measured I2C signal waveform;
judging whether the waveform of the actually measured I2C signal is monotonous;
if yes, recording the adjustment process and the adjustment result.
7. An I2C signal conditioning device, comprising:
the request analysis module is used for analyzing the received I2C signal adjustment request to obtain a target link to be adjusted by the signal;
the waveform detection module is used for detecting the I2C signal waveform of the target link;
the first judgment module is used for judging whether the waveform of the I2C signal is monotonous or not;
and the capacitance value adjusting module is used for performing capacitance value adjusting operation on the entity MOS tube in the target link when the I2C signal waveform is determined not to be monotonous.
8. The I2C signal conditioning device of claim 7, wherein the capacity adjustment module comprises:
the state switching submodule is used for switching the entity MOS tube in the target link from an access state to a short-circuit state;
the first judgment submodule is used for judging whether the waveform of the I2C signal changes or not;
and the capacitance value adjusting submodule is used for switching the entity MOS tube from the short-circuit state to the access state and carrying out capacitance value adjusting operation on the entity MOS tube when the I2C signal waveform is determined to have variation.
9. An I2C signal conditioning device, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the I2C signal conditioning method according to any one of claims 1 to 6 when executing the computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, carries out the steps of the I2C signal conditioning method according to any one of claims 1 to 6.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106353583A (en) * | 2016-08-03 | 2017-01-25 | 武汉本杰明自动化设备工程有限公司 | Small infrared power factor monitoring device for high-power industrial equipment |
| US10540466B1 (en) * | 2018-02-09 | 2020-01-21 | Cadence Design Systems, Inc. | Systems and methods for streaming waveform data during emulation run |
| CN111969986A (en) * | 2020-07-17 | 2020-11-20 | 苏州浪潮智能科技有限公司 | System and method for adjusting signal delay and slope |
| CN112038091A (en) * | 2020-08-04 | 2020-12-04 | 厚元技术（香港）有限公司 | Adjustable capacitor based on MEMS structure |
| CN213024379U (en) * | 2020-10-22 | 2021-04-20 | 太仓市同维电子有限公司 | Clamp for verifying I2C bus clock back-channel tolerance |
| CN112732502A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Method and device for detecting I2C signal, detection equipment and storage medium |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3844120B2 (en) * | 2001-10-19 | 2006-11-08 | 株式会社ルネサステクノロジ | Semiconductor device |
| KR100910446B1 (en) * | 2007-12-03 | 2009-08-04 | 주식회사 동부하이텍 | A circuit for data synchronizing of I2C time controller in display device and method thereof |
| US10585834B2 (en) * | 2017-06-21 | 2020-03-10 | Linear Technology Holding Llc | I2C device extender for inter-board communication over a single-channel bidirectional link |
-
2022
- 2022-01-29 CN CN202210110057.1A patent/CN114138701B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106353583A (en) * | 2016-08-03 | 2017-01-25 | 武汉本杰明自动化设备工程有限公司 | Small infrared power factor monitoring device for high-power industrial equipment |
| US10540466B1 (en) * | 2018-02-09 | 2020-01-21 | Cadence Design Systems, Inc. | Systems and methods for streaming waveform data during emulation run |
| CN111969986A (en) * | 2020-07-17 | 2020-11-20 | 苏州浪潮智能科技有限公司 | System and method for adjusting signal delay and slope |
| CN112038091A (en) * | 2020-08-04 | 2020-12-04 | 厚元技术（香港）有限公司 | Adjustable capacitor based on MEMS structure |
| CN213024379U (en) * | 2020-10-22 | 2021-04-20 | 太仓市同维电子有限公司 | Clamp for verifying I2C bus clock back-channel tolerance |
| CN112732502A (en) * | 2021-01-07 | 2021-04-30 | 苏州浪潮智能科技有限公司 | Method and device for detecting I2C signal, detection equipment and storage medium |
Non-Patent Citations (3)
| Title |
|---|
| ESD protection of open-drain I2C using fragile devices in embedded systems;FARZAN FARBIZ;《IEEE》;20151102;第1-4页 * |
| I2C设备调试及波形分析;GOODTALENT;《CSDN》;20150408;第1-3页 * |
| 带有I2C端口的电压可调DC/DC设计;梁国辉;《中国优秀硕士学位论文全文数据库》;20130615(第2013年06期);C042-151 * |
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