CN114138203A - Data access method, data storage method and data access controller - Google Patents
Data access method, data storage method and data access controller Download PDFInfo
- Publication number
- CN114138203A CN114138203A CN202111476472.0A CN202111476472A CN114138203A CN 114138203 A CN114138203 A CN 114138203A CN 202111476472 A CN202111476472 A CN 202111476472A CN 114138203 A CN114138203 A CN 114138203A
- Authority
- CN
- China
- Prior art keywords
- code
- stored
- codes
- original
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000013500 data storage Methods 0.000 title claims abstract description 19
- 230000000295 complement effect Effects 0.000 claims description 92
- 230000007613 environmental effect Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Human Computer Interaction (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The application discloses a data access method, a data storage method and a data access controller, wherein the data access method comprises the following steps: the method comprises the steps of firstly obtaining X stored codes corresponding to written data, then comparing and selecting all mode users with the same code values in the X stored codes, then determining all mode users as target codes according to the bit sequences of the stored codes, and then obtaining target read data corresponding to the written data based on the target codes, so that inaccuracy of data reading caused by electrical performance and/or environmental factors and the like can be reduced or avoided, and further the reliability of a memory is improved.
Description
Technical Field
The present application relates to the field of data access technologies, and in particular, to a data access method, a data storage method, and a data access controller.
Background
Some data in the memory, such as critical parameters, are important, and if the data read and/or written by the memory is incorrect, the normal operation of the memory is affected, and even the memory cannot operate, so that the reliability of the memory is reduced.
Therefore, it is desirable to provide a data access method, a data storage method and a data access controller, so as to improve the reliability of the memory.
Disclosure of Invention
The application provides a data access method, a data storage method and a data access controller, which are used for relieving the technical problem of low reliability of a memory.
In a first aspect, the present application provides a data access method, comprising: acquiring X stored codes corresponding to written data, wherein X is an odd number greater than or equal to 3; comparing and selecting X stored codes with the same code values; determining codes with various modes as targets according to the stored coded bit sequences; target read data corresponding to the written data is obtained based on the target encoding.
In some embodiments, the post-storage encoding comprises any one of post-storage base code, post-storage complement code, and post-storage complement code; the data access method further comprises the following steps: if the stored codes are the stored complement codes or the stored inverse codes, converting the stored complement codes or the stored inverse codes into corresponding original codes; comparing and selecting a plurality of corresponding original codes or all the modes with the same code values on the same positions in the stored original codes; determining the original code of which each mode is the target according to the stored coded bit sequence; target read data corresponding to the written data is obtained based on the target original code.
In some embodiments, the post-storage encoding includes any two of post-storage original code, post-storage complement code, and post-storage complement code; the data access method further comprises the following steps: if any two codes comprise the stored complement codes and/or the stored complement codes, converting the stored complement codes and/or the stored complement codes into corresponding first corresponding original codes and/or second corresponding original codes; if any two codes comprise the stored original code, determining the stored original code as a third corresponding original code; comparing and selecting two kinds of mode with consistent code values on the same bit in the first corresponding original code, the second corresponding original code and the third corresponding original code; determining the original code of which each mode is the target according to the stored coded bit sequence; target read data corresponding to the written data is obtained based on the target original code.
In some embodiments, the post-storage code includes a first code, a second code, and a third code, and when the first code and the second code are identical, the obtained first comparison result is used as the target read data; when the first code is inconsistent with the second code, recording a first comparison result; comparing one of the first code/the second code with the third code, and recording a second comparison result; comparing the other of the first code/the second code with a third code, and recording a third comparison result; determining the same one of the first comparison result, the second comparison result and the third comparison result as the target read data; the first code is one of a source code, a complement code and an inverse code, the second code is the other of the source code, the complement code and the inverse code, and the third code is the other of the source code, the complement code and the inverse code.
In some embodiments, the post-storage encoding comprises a post-storage original code, a post-storage complement code, and a post-storage complement code; the data access method further comprises the following steps: the number of the stored original codes, the number of the stored complement codes and the number of the stored inverse codes are J, K and L respectively, wherein J, K and L are odd numbers which are more than or equal to 3; comparing and selecting J stored mode with same code value in original code; determining each mode as a first target sub-original code according to the bit sequence of the stored original code; comparing and selecting the mode with the same code value in the K stored complementary codes; determining each mode as a target sub-complement according to the bit sequence of the stored complement; converting the sub complement codes of the targets into corresponding second sub original codes of the targets; comparing and selecting the mode with the same code value in the same bit in the L stored inverse codes; determining each mode as a target subcode according to the bit sequence of the stored code after the code is reversed; converting the sub-inverse code of the target into a corresponding third sub-original code of the target; comparing and selecting the mode with the same code value in the same bit in the first target sub-original code, the second target sub-original code and the third target sub-original code; determining the original code of which each mode is the target according to the stored coded bit sequence; target read data corresponding to the written data is obtained based on the target original code.
In some embodiments, the data access method further comprises: transcoding the data to be written into X pre-storage codes corresponding to the data to be written; store X pre-storage codes to obtain X post-storage codes.
In a second aspect, the present application provides a data storage method, including: transcoding the data to be written into X pre-storage codes corresponding to the data to be written, wherein X is an odd number greater than or equal to 3; storing each of the X pre-memory codes to a different storage space to obtain X post-memory codes.
In some embodiments, the data storage method further comprises: configuring X pre-storage codes comprising J pre-storage original codes, K pre-storage complementary codes and L pre-storage inverse codes, wherein J, K, L are odd numbers which are greater than or equal to 3; storing each pre-storage original code in a different first storage space; storing each pre-stored complement in a different second storage space; storing each pre-amble in a different third storage space.
In some embodiments, each of the first storage space, the second storage space, or the third storage space includes one or more mutually discrete storage addresses, and each storage address corresponds to one storage unit.
In a third aspect, the present application provides a data access controller, which includes an obtaining module, a comparing and selecting module, a determining module, and a decoding module, where the obtaining module is configured to obtain X stored codes corresponding to written data, where X is an odd number greater than or equal to 3; the comparison selection module is used for comparing and selecting X stored codes with the same code values and the same mode; the determining module is used for determining the codes of all the mode persons as targets according to the stored coded bit sequences; the decoding module is used for obtaining target read data corresponding to the written data based on the target coding.
According to the data access method and the data access controller, a plurality of stored codes corresponding to written data are obtained, then the mode numbers with the same code value in the X stored codes are compared and selected, then the mode numbers are arranged according to the bit sequence of the stored codes and serve as target codes, finally the target codes are correspondingly decoded, target read data corresponding to the written data are obtained, inaccuracy of data reading caused by electrical performance and/or environmental factors can be reduced or avoided, and reliability of a storage is improved.
In addition, according to the data storage method provided by the application, the data to be written are transcoded to obtain X pre-storage codes corresponding to the data to be written, and each of the X pre-storage codes is stored in different storage spaces, so that even though a small part of wrong writing results caused by electrical performance, environmental factors and the like exist, most of correct writing results still exist, and compared with single-code single-time writing and/or continuous writing, the writing accuracy is improved, and further the reliability of the storage is improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic flowchart of a data storage method according to an embodiment of the present application.
Fig. 2 is another schematic flow chart of a data storage method according to an embodiment of the present application.
Fig. 3 is a flowchart illustrating a data access method according to an embodiment of the present application.
Fig. 4 is a schematic flowchart of another data access method according to an embodiment of the present disclosure.
Fig. 5 is a schematic structural diagram of a data access controller according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In view of the disadvantage of low reliability of the existing memory, in one embodiment, as shown in fig. 1, the present embodiment provides a data storage method, which includes the following steps:
step S100: transcoding the data to be written into X pre-storage codes corresponding to the data to be written, wherein X is an odd number greater than or equal to 3.
Step S200: storing each of the X pre-memory codes to a different storage space to obtain X post-memory codes.
It can be understood that, in the data storage method of this embodiment, X pre-storage codes corresponding to the data to be written can be obtained by transcoding the data to be written, and each of the X pre-storage codes is stored in a different storage space, so that even if there are some erroneous writing results caused by electrical performance and/or environmental factors, most of the correct writing results still exist, and compared with single-code single-write and/or continuous writing, the writing accuracy is improved, and further the reliability of the memory is improved.
It should be noted that the pre-storage code may be at least one of a pre-storage original code, a pre-storage complementary code, and a pre-storage inverse code, where the pre-storage original code may belong to an original code, the pre-storage complementary code may belong to a complementary code, and the pre-storage inverse code may belong to an inverse code. The original code may be machine number or binary data corresponding to data to be written. The code reversal can be obtained by reversing the values of the bits in the original code, or the data to be written can be directly transcoded into the corresponding code reversal. The complementary code can be obtained by adding '1' on the basis of the inverse code, or the data to be written can be directly transcoded into the corresponding complementary code.
And the corresponding original code is the original code before storage before being stored in the corresponding storage address or storage space. The corresponding complement is the complement before storage before being stored in the corresponding storage address or storage space. Before the corresponding code negatives are stored in the corresponding storage addresses or storage spaces, the code negatives are stored.
In one embodiment, the data storage method may further include: configuring X pre-storage codes comprising J pre-storage original codes, K pre-storage complementary codes and L pre-storage inverse codes, wherein J, K, L are odd numbers which are greater than or equal to 3; storing each pre-storage original code in a different first storage space; storing each pre-stored complement in a different second storage space; storing each pre-amble in a different third storage space.
One storage space may include at least one storage unit, each storage unit corresponds to one storage address, and each storage unit may store 1byte of data.
The storage addresses of the storage units in each storage space can be continuous or discrete. Wherein the same code may preferably be stored in one or more memory locations with consecutive memory addresses.
It should be noted that, in this embodiment, configuring each code in a different storage address or storage space can effectively avoid that the data to be written changes in the storage process due to interference in the storage process, so that the working reliability of the memory chip is reduced.
Specifically, as shown in fig. 2, the process of data storage may be as follows:
firstly, transcoding: the Data to be written is converted into a Data0 original code, the Data0 original code is a machine number, and preferably, a Data0 inverse code can be obtained by inverting the Data0 original code, and then Data0 complementary code is obtained by adding 1 to the lowest bit of the Data0 inverse code.
Then, Data0 original code can be stored in Addr0, Addr1 complementary code of Data0, and Addr2 inverse code of Data 0. Wherein Addr0, Addr1 and Addr2 can each characterize at least one memory address.
Preferably, the Data0 original code may be stored again in Addr0+ n, the Data0 complement code may be stored again in Addr1+ n, and the Data0 complement code may be stored again in Addr2+ n. Similarly, Addr0+ n, Addr1+ n, and Addr2+ n may each represent at least one memory address. Wherein n is a positive integer, and the value can be reasonably configured according to the storage space to avoid different Data0 original codes, Data0 complement codes and Data0 inverse codes from being stored in repeated address units.
Preferably, the Data0 original code may be stored again in Addr0+2n, the Data0 complement code may be stored again in Addr1+2n, and the Data0 inverse code may be stored again in Addr2+2n, so that multiple times of storage may be performed as needed, and it should be noted that the multiple times of storage may be performed after the storage is completed in one time or may be performed in multiple times as needed. The Addr0+2n, Addr1+2n and Addr2+2n can also represent at least one storage address.
Generally, when a memory cell is disturbed or fails, the memory cells adjacent to the memory cell are also affected. In the embodiment, for example, the sequential storage form of the original code, the complement code and the complement code is adopted, so that the influence on the adjacent storage unit to cause the integral error of the data when one storage unit is interfered or has a fault can be effectively avoided. Especially when the storage is carried out for multiple times, the influence on the adjacent storage units can be effectively avoided.
In view of the disadvantage of low reliability of the conventional memory, the present embodiment provides a data access method, as shown in fig. 3, which includes the following steps:
step S10: x stored codes corresponding to the written data are obtained, wherein X is an odd number which is larger than or equal to 3.
Step S20: comparing and selecting X kinds of mode with identical code value in stored code.
Step S30: and determining the codes with the modes as targets according to the stored coded bit sequences.
Step S40: target read data corresponding to the written data is obtained based on the target encoding.
It can be understood that, in the data access method provided in this embodiment, by obtaining a plurality of stored codes corresponding to written data, comparing and selecting the mode with the same code value in the X stored codes, arranging the mode as a target code according to the bit sequence of the stored codes, and finally performing corresponding decoding on the target code, the target read data corresponding to the written data is obtained, which can reduce or avoid inaccuracy in data reading caused by electrical performance and/or environmental factors, and further improve reliability of the memory.
And the corresponding original code before storage is the original code after storage after being stored in the corresponding storage address or storage space. Similarly, the corresponding pre-storage complement code is stored in the corresponding storage address or storage space, and then is the post-storage complement code. And storing the corresponding code reversal before storage into the corresponding storage address or storage space, namely storing the code reversal after storage.
In some embodiments, when the first code and the second code are identical, the first comparison result is obtained as the target read data; when the first code is inconsistent with the second code, recording a first comparison result, comparing the first code/the second code with the third code, recording a second comparison result, comparing the second code/the first code with the third code, and recording a third comparison result; the first, second and third comparison results are compared, and the same result is taken as read data. The first, second and third codes may be one of a source code, a complement code and an inverse code, respectively. Because the data is stored for three times, the logic dead cycle is avoided, the comparison efficiency is improved, and the accuracy of the data is also ensured.
In one embodiment, the post-storage encoding includes any one of post-storage original code, post-storage complement code, and post-storage inverse code; the data access method further comprises the following steps: if the stored codes are the stored complement codes or the stored inverse codes, converting the stored complement codes or the stored inverse codes into corresponding original codes; comparing and selecting a plurality of corresponding original codes or all the modes with the same code values on the same positions in the stored original codes; determining the original code of which each mode is the target according to the stored coded bit sequence; target read data corresponding to the written data is obtained based on the target original code.
For example, if the X stored codes are 3 stored original codes, and the 3 stored original codes are all 001, for example, the mode with the consistent code values at the lowest position in the 3 stored original codes is 1, the mode with the consistent code values at the next lower position in the 3 stored original codes is 0, the mode with the consistent code values at the highest position in the 3 stored original codes is 0, and the target original code is 001 according to the bit order of the stored codes, that is, the corresponding code value is reset to the corresponding lowest position, next lower position, and highest position.
Similarly, if the X stored codes are 3 stored inverses, each of the 3 stored inverses is, for example, 110, and the corresponding original code obtained after the stored inverses is correspondingly converted is 001, then the mode with the consistent code values at the lowest position in the 3 corresponding original codes is 1, the mode with the consistent code values at the next lower position in the 3 corresponding original codes is 0, the mode with the consistent code values at the highest position in the 3 corresponding original codes is 0, and the target original code is 001 according to the bit sequence of the stored codes, that is, the corresponding code value is reduced to the corresponding lowest position, next lower position.
Similarly, if the X stored codes are 3 stored complementary codes, each of the 3 stored complementary codes is 111, for example, the corresponding original code is 001 after the stored complementary codes are correspondingly converted, then the mode with the consistent code values at the lowest position in the 3 corresponding original codes is 1, the mode with the consistent code values at the next lower position in the 3 corresponding original codes is 0, the mode with the consistent code values at the highest position in the 3 corresponding original codes is 0, and the target original code is 001 after the stored coded bit sequence, that is, the corresponding code value is reduced to the corresponding lowest position, next lower position.
In one embodiment, the post-storage code includes any two of a post-storage original code, a post-storage complement code, and a post-storage inverse code; the data access method further comprises the following steps: if any two codes comprise the stored complement codes and/or the stored complement codes, converting the stored complement codes and/or the stored complement codes into corresponding first corresponding original codes and/or second corresponding original codes; if any two codes comprise the stored original code, determining the stored original code as a third corresponding original code; comparing and selecting two kinds of mode with consistent code values on the same bit in the first corresponding original code, the second corresponding original code and the third corresponding original code; determining the original code of which each mode is the target according to the stored coded bit sequence; target read data corresponding to the written data is obtained based on the target original code.
For example, if the X stored codes are 1 stored original code 001 and 2 stored inverse codes 110, the stored inverse code 110 is converted into the second corresponding original code 001, the mode with the consistent code values at the lowest bits in the 1 stored original code 001 and the 2 second corresponding original codes 001 is 1, the mode with the consistent code values at the next lowest bits in the 1 stored original code 001 and the 2 second corresponding original codes 001 is 0, the mode with the consistent code values at the highest bits in the 1 stored original code 001 and the 2 second corresponding original codes 001 is 0, and the target original code 001 is obtained according to the bit order of the stored codes, i.e., the corresponding code values are returned to the corresponding lowest bits, next lowest bits.
Similarly, if the X stored codes are 1 stored original code 001 and 2 stored complementary codes 111, the stored complementary code 111 is converted into the first corresponding original code 001, the mode with the consistent code values at the lowest bits in the 1 stored original code 001 and the 2 first corresponding original codes 001 is 1, the mode with the consistent code values at the next lowest bits in the 1 stored original code 001 and the 2 first corresponding original codes 001 is 0, the mode with the consistent code values at the highest bits in the 1 stored original code 001 and the 2 first corresponding original codes 001 is 0, and the target original code 001 is obtained according to the bit order of the stored codes, i.e., the corresponding code values are returned to the corresponding lowest bits, next lowest bits.
Similarly, if the X stored codes are 1 stored inverse code 110 and 2 stored complementary codes 111, the stored complementary code 111 is converted into the first corresponding original code 001, the stored inverse code 110 is converted into the second corresponding original code 001, the mode with the consistent code values at the lowest positions in the 1 second corresponding original code 001 and the 2 first corresponding original codes 001 is 1, the mode with the consistent code values at the lowest positions in the 1 second corresponding original code 001 and the 2 first corresponding original codes 001 is 0, the mode with the consistent code values at the highest positions in the 1 second corresponding original code 001 and the 2 first corresponding original codes 001 is 0, and the corresponding code values are restored to the corresponding lowest positions, next lower positions and highest positions according to the bit sequence of the stored codes, that is, the target original code 001 is obtained.
In one embodiment, the stored codes comprise stored original codes, stored complement codes and stored inverse codes; the data access method further comprises the following steps: the number of the stored original codes, the number of the stored complement codes and the number of the stored inverse codes are J, K and L respectively, wherein J, K and L are odd numbers which are more than or equal to 3; comparing and selecting J stored mode with same code value in original code; and determining the mode as the first target sub-original code according to the bit sequence of the stored original code.
For example, if J is 3, the stored original codes are all 001, the mode with the consistent code values at the lowest position in the 3 stored original codes is 1, the mode with the consistent code values at the next lower position in the 3 stored original codes is 0, the mode with the consistent code values at the highest position in the 3 stored original codes is 0, and the first target child original code is 001 according to the bit sequence of the stored original code, that is, the corresponding code value is reset to the corresponding lowest position, next lower position.
In one embodiment, the data access method further comprises: comparing and selecting the mode with the same code value in the K stored complementary codes; determining each mode as a target sub-complement according to the bit sequence of the stored complement; and converting the sub complement codes of the targets into corresponding second sub original codes of the targets.
For example, if K is 3, the stored complementary codes are all 111, then the mode with the consistent code values at the lowest position in the 3 stored complementary codes is 1, the mode with the consistent code values at the next lowest position in the 3 stored complementary codes is 1, the mode with the consistent code values at the highest position in the 3 stored complementary codes is 1, the target sub-complementary code is 111 according to the bit sequence of the stored complementary code, that is, the corresponding code value is returned to the corresponding lowest position, next lowest position, and highest position, and then the target sub-complementary code is converted into 111, which is the corresponding second target sub-original code of 001.
In one embodiment, the data access method further comprises: comparing and selecting the mode with the same code value in the same bit in the L stored inverse codes; determining each mode as a target subcode according to the bit sequence of the stored code after the code is reversed; and converting the sub-inverse code of the target into a corresponding third sub-original code of the target.
For example, if L is 3, all the stored inverses are 110, then the mode with the consistent code values at the lowest position in the 3 stored inverses is 0, the mode with the consistent code values at the next lowest position in the 3 stored inverses is 1, the mode with the consistent code values at the highest position in the 3 stored inverses is 1, the target child inversed code is 110 according to the bit order of the stored inverses, that is, the corresponding code value is reset to the corresponding lowest position, next lowest position, and highest position, and then the target child inversed code is converted into the third target child original code corresponding to 110 as 001.
In one embodiment, the data access method further comprises: comparing and selecting the mode with the same code value in the same bit in the first target sub-original code, the second target sub-original code and the third target sub-original code; determining the original code of which each mode is the target according to the stored coded bit sequence; target read data corresponding to the written data is obtained based on the target original code.
For example, it is assumed that the first target sub-original code, the second target sub-original code, and the third target sub-original code are all 001, the mode with the consistent code values at the lowest bits in the first target sub-original code, the second target sub-original code, and the third target sub-original code is 1, the mode with the consistent code values at the next lowest bits in the first target sub-original code, the second target sub-original code, and the third target sub-original code is 0, the mode with the consistent code values at the highest bits in the first target sub-original code, the second target sub-original code, and the third target sub-original code is 0, and the target original code is 001 according to the stored coded bit sequence, i.e., the corresponding code value.
Based on the above, even if a few of all the post-storage codes have write or read errors, the target original code can still be determined to be the original code before storage after the corresponding processing of the present application, and therefore, the probability of occurrence of data storage errors can be reduced or avoided.
As shown in fig. 4, the specific process of the data access may be as follows:
the Data0 original codes correspondingly stored in the Addr0, Addr3 and Addr0+ n can be read out simultaneously. Each of Addr0, Addr3, and Addr0+ n may include at least one memory address.
Comparing the 0 th bit of the Data0 original codes correspondingly stored in the Addr0, Addr3 and Addr0+ n, wherein the 0 th bit is compared to obtain more 1 values because the number of the acquired Data0 original codes is odd, and then 1 is acquired; if the 0 th bit comparison yields more "0" values, then 0 is taken.
Then Addr0, Addr3, Addr0+ n are compared for the 1 st, 2 nd etc. 7 th bits of the corresponding stored Data0 original code, and so on.
New raw Data0_ cmp can then be obtained.
Similarly, Data0 complement codes correspondingly stored by Addr1, Addr4 and Addr1+ n can be read out simultaneously. Each of Addr1, Addr4, and Addr1+ n may include at least one memory address.
Comparing 0 th bits of the Data0 complement codes correspondingly stored in the Addr1, Addr4 and Addr1+ n, wherein the 0 th bits are compared to obtain more 1 values because the obtained Data0 complement codes are odd numbers, and then 1 is obtained; if the 0 th bit comparison yields more "0" values, then 0 is taken.
The 1 st, 2 nd, 7 th, etc. bits of the Data0 complement of Addr1, Addr4, Addr1+ n, respectively, are then compared, and so on.
Then, new complement Data can be obtained, and the new complement Data is transcoded to obtain corresponding new original Data0_ cmp _ p.
Similarly, the Data0 anticode stored correspondingly to Addr2, Addr5 and Addr2+ n can be read out simultaneously. Each of Addr2, Addr5, and Addr2+ n may include at least one memory address.
Comparing the 0 th bit of the Data0 inverses correspondingly stored in the Addr2, Addr5 and Addr2+ n, wherein the 0 th bit is compared to obtain more 1 values because the number of the Data0 inverses is odd, and then 1 is obtained; if the 0 th bit comparison yields more "0" values, then 0 is taken.
Then Addr2, Addr5, and Addr2+ n are compared for the 1 st, 2 nd, 7 th, etc. bits of the corresponding stored Data0 anticode, and so on.
Then, new decoded Data can be obtained, and the new decoded Data is transcoded to obtain corresponding new original Data0_ cmp _ i.
Finally, comparing and selecting the mode with the same code value in the original code Data0_ cmp, the original code Data0_ cmp _ p and the original code Data0_ cmp _ i, integrating the mode according to the stored coded bit sequence to obtain the target original code, and outputting Data which is target reading Data to be read corresponding to the target original code.
In one embodiment, as shown in fig. 5, the present embodiment provides a data access controller, which includes an obtaining module 100, a comparing and selecting module 200, a determining module 300, and a decoding module 400, where the obtaining module 100 is configured to obtain X stored codes corresponding to written data, where X is an odd number greater than or equal to 3; the comparison selection module 200 is used for comparing and selecting X stored codes with the same code values; the determining module 300 is configured to determine, according to the stored coded bit sequence, that each mode is the target code; the decoding module 400 is used for obtaining target read data corresponding to the written data based on the target code.
The output end of the obtaining module 100 may be electrically connected to the input end of the comparing and selecting module 200, the output end of the comparing and selecting module 200 may be electrically connected to the input end of the determining module 300, the output end of the determining module 300 may be electrically connected to the input end of the decoding module 400, and the output end of the decoding module 400 is used for outputting the target read data.
It can be understood that, in the data access controller provided in this embodiment, by obtaining a plurality of stored codes corresponding to written data, comparing and selecting X number of mode generators having the same code values in the stored codes, arranging the mode generators as target codes according to the bit sequence of the stored codes, and finally performing corresponding decoding on the target codes, target read data corresponding to the written data is obtained, which can reduce or avoid inaccuracy in data reading caused by electrical performance and/or environmental factors, and further improve reliability of the memory.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The data access method, the data storage method, and the data access controller provided in the embodiments of the present application are described in detail above, and specific examples are applied herein to explain the principles and implementations of the present application, and the descriptions of the above embodiments are only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. A method for accessing data, comprising:
acquiring X stored codes corresponding to written data, wherein X is an odd number greater than or equal to 3;
comparing and selecting the mode with the same code value in the same bit in the X stored codes;
determining the codes of which the mode is targeted according to the bit sequence of the stored codes;
target read data corresponding to the written data is obtained based on the target code.
2. The data access method of claim 1, wherein the stored code comprises any one of a stored original code, a stored complement code, and a stored complement code; the data access method further comprises:
if the stored code is the stored complement code or the stored inverse code, converting the stored complement code or the stored inverse code into a corresponding original code;
comparing and selecting a plurality of corresponding original codes or all the mode with the same code value on the same position in the stored original codes;
determining the original code of which the mode is the target according to the bit sequence of the stored code;
and obtaining target read data corresponding to the written data based on the target original code.
3. The data access method of claim 1, wherein the stored codes comprise any two of stored original codes, stored complement codes, and stored complement codes; the data access method further comprises:
if the two codes comprise the stored complementary codes and/or the stored inverse codes, converting the stored complementary codes and/or the stored inverse codes into corresponding first corresponding original codes and/or second corresponding original codes;
if the any two codes comprise the stored original codes, determining the stored original codes as third corresponding original codes;
comparing and selecting two modes with consistent code values on the same bit, which exist in the first corresponding original code, the second corresponding original code and the third corresponding original code;
determining the original code of which the mode is the target according to the bit sequence of the stored code;
and obtaining target read data corresponding to the written data based on the target original code.
4. The data access method of claim 1, wherein the stored code comprises a first code, a second code, and a third code, and when the first code and the second code are identical, a first comparison result is obtained as the target read data;
when the first code is inconsistent with the second code, recording a first comparison result; comparing one of the first code/the second code with the third code, and recording a second comparison result; comparing the other of the first code/the second code with the third code, and recording a third comparison result; determining that the same one of the first comparison result, the second comparison result, and the third comparison result is the target readout data;
the first code is one of an original code, a complementary code and a complementary code, the second code is another one of the original code, the complementary code and the complementary code, and the third code is another one of the original code, the complementary code and the complementary code.
5. The data access method of claim 1, wherein the stored codes comprise stored original codes, stored complement codes, and stored complement codes; the data access method further comprises:
configuring the numbers of the stored original code, the stored complement code and the stored inverse code to be J, K and L in sequence, wherein J, K and L are odd numbers which are more than or equal to 3;
comparing and selecting J modes with the same code values in the stored original code;
determining the mode as a first target sub-source code according to the bit sequence of the stored source code;
comparing and selecting the mode with the same code value in the K stored complementary codes;
determining the mode as the target sub-complement according to the bit sequence of the stored complement;
converting the target sub-complement code into a corresponding second target sub-original code;
comparing and selecting the mode with the same code value in the same bit in the stored inverse code;
determining the mode person as the target subcode according to the bit sequence of the stored subcode;
converting the target sub-inverse code into a corresponding third target sub-original code;
comparing and selecting the mode with the same code value on the same bit in the first target sub-primitive code, the second target sub-primitive code and the third target sub-primitive code;
determining the original code of which the mode is the target according to the bit sequence of the stored code;
and obtaining target read data corresponding to the written data based on the target original code.
6. The data access method of any one of claims 1 to 5, further comprising:
transcoding the data to be written into X pre-storage codes corresponding to the data to be written;
storing the X pre-storage codes to obtain the X post-storage codes.
7. A method of storing data, comprising:
transcoding the data to be written into X pre-storage codes corresponding to the data to be written, wherein X is an odd number greater than or equal to 3;
and storing each of the X pre-storage codes into different storage spaces to obtain the X post-storage codes.
8. The data storage method of claim 7, further comprising:
configuring the X pre-storage codes to comprise J pre-storage original codes, K pre-storage complementary codes and L pre-storage inverse codes, wherein J, K, L are odd numbers which are greater than or equal to 3;
storing each pre-storage original code in a different first storage space;
storing each of the pre-stored complements in a different second storage space;
storing each of the stored pre-ambles in a different third storage space.
9. The data storage method according to claim 8, wherein each of the first storage space, the second storage space, or the third storage space comprises one or more mutually discrete storage addresses, and each storage address corresponds to a storage unit.
10. A data access controller, comprising:
the acquisition module is used for acquiring X stored codes corresponding to written data, wherein X is an odd number greater than or equal to 3;
a comparison selection module for comparing and selecting the mode with the same code value in the same bit in the X stored codes;
the determining module is used for determining the codes of the modes as targets according to the bit sequences of the stored codes;
and the decoding module is used for obtaining target read data corresponding to the written data based on the target code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111476472.0A CN114138203B (en) | 2021-12-06 | 2021-12-06 | Data access method, data storage method and data access controller |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111476472.0A CN114138203B (en) | 2021-12-06 | 2021-12-06 | Data access method, data storage method and data access controller |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114138203A true CN114138203A (en) | 2022-03-04 |
| CN114138203B CN114138203B (en) | 2024-02-06 |
Family
ID=80383994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111476472.0A Active CN114138203B (en) | 2021-12-06 | 2021-12-06 | Data access method, data storage method and data access controller |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114138203B (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003051952A (en) * | 2001-08-06 | 2003-02-21 | Fuji Xerox Co Ltd | Image processing apparatus |
| US20030185442A1 (en) * | 2002-03-29 | 2003-10-02 | Koninklijke Philips Electronics N.V. | Method and apparatus for detecting scene changes in video using a histogram of frame differences |
| US7102544B1 (en) * | 2005-05-31 | 2006-09-05 | Altera Corporation | Method and system for improving memory interface data integrity in PLDs |
| US20090319867A1 (en) * | 2008-06-24 | 2009-12-24 | Kabushiki Kaisha Toshiba | Memory system and memory access method |
| US20150089317A1 (en) * | 2013-09-20 | 2015-03-26 | Seagate Technology Llc | Storage device with multiple coding redundancies |
| CN109196479A (en) * | 2016-04-05 | 2019-01-11 | 美光科技公司 | Error-correcting code (ECC) operation in memory |
| CN110309014A (en) * | 2019-07-05 | 2019-10-08 | 西安微电子技术研究所 | A kind of full row encoding and decoding SRAM encoder data read-write structure and data read-write method |
| US20210173777A1 (en) * | 2019-12-10 | 2021-06-10 | Pony Al Inc. | Dynamic memory address encoding |
-
2021
- 2021-12-06 CN CN202111476472.0A patent/CN114138203B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003051952A (en) * | 2001-08-06 | 2003-02-21 | Fuji Xerox Co Ltd | Image processing apparatus |
| US20030185442A1 (en) * | 2002-03-29 | 2003-10-02 | Koninklijke Philips Electronics N.V. | Method and apparatus for detecting scene changes in video using a histogram of frame differences |
| US7102544B1 (en) * | 2005-05-31 | 2006-09-05 | Altera Corporation | Method and system for improving memory interface data integrity in PLDs |
| US20090319867A1 (en) * | 2008-06-24 | 2009-12-24 | Kabushiki Kaisha Toshiba | Memory system and memory access method |
| US20150089317A1 (en) * | 2013-09-20 | 2015-03-26 | Seagate Technology Llc | Storage device with multiple coding redundancies |
| CN109196479A (en) * | 2016-04-05 | 2019-01-11 | 美光科技公司 | Error-correcting code (ECC) operation in memory |
| CN110309014A (en) * | 2019-07-05 | 2019-10-08 | 西安微电子技术研究所 | A kind of full row encoding and decoding SRAM encoder data read-write structure and data read-write method |
| US20210173777A1 (en) * | 2019-12-10 | 2021-06-10 | Pony Al Inc. | Dynamic memory address encoding |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114138203B (en) | 2024-02-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6279133B1 (en) | Method and apparatus for significantly improving the reliability of multilevel memory architecture | |
| US7644348B2 (en) | Method and apparatus for error detection and correction | |
| US8331168B2 (en) | Increased capacity heterogeneous storage elements | |
| CN1099165C (en) | Viterbi decoder | |
| TWI484497B (en) | Enhanced multilevel memory, method for operating the same, and computer system | |
| US8635508B2 (en) | Systems and methods for performing concatenated error correction | |
| US7047478B2 (en) | Multipurpose method for constructing an error-control code for multilevel memory cells operating with a variable number of storage levels, and multipurpose error-control method using said error-control code | |
| EP4071762B1 (en) | Error correction system | |
| EP4050608A1 (en) | Comparison system | |
| US7721177B2 (en) | Device and method for determining a position of a bit error in a bit sequence | |
| CN110535476B (en) | Method, device, computer equipment and storage medium for optimizing soft information storage of LDPC soft decoder | |
| JPH01158698A (en) | Semiconductor memory | |
| CN103137213B (en) | Storage control device with low density parity check code coding capacity and method | |
| KR102355082B1 (en) | Efficient survivor memory architecture for successive cancellation list decoding of channel polarization codes | |
| CN114138203A (en) | Data access method, data storage method and data access controller | |
| KR100304193B1 (en) | Inverse circuit of reed-solomon decoder | |
| CN1787386A (en) | Method for path measuring me mory of viterbi decoder | |
| US5091910A (en) | Information processing device | |
| US6467064B1 (en) | Viterbi decoder | |
| EP1160668B1 (en) | Semiconductor integrated circuit and method of testing semiconductor integrated circuit | |
| US20020102030A1 (en) | Arithmetic decoding method and device and storage medium | |
| JPH11212876A (en) | Coding method and memory using the same | |
| CN115329397A (en) | Monotonic counter memory system | |
| RU2297034C2 (en) | Fault-tolerant information storage device | |
| WO2022151721A1 (en) | Error correction system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |