CN114137327A - Phase sequence detection system, method, equipment and storage medium - Google Patents
Phase sequence detection system, method, equipment and storage medium Download PDFInfo
- Publication number
- CN114137327A CN114137327A CN202111418751.1A CN202111418751A CN114137327A CN 114137327 A CN114137327 A CN 114137327A CN 202111418751 A CN202111418751 A CN 202111418751A CN 114137327 A CN114137327 A CN 114137327A
- Authority
- CN
- China
- Prior art keywords
- phase sequence
- channel
- phase
- channels
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000819 phase cycle Methods 0.000 title claims abstract description 237
- 238000001514 detection method Methods 0.000 title claims abstract description 89
- 238000000034 method Methods 0.000 title description 15
- 108091006146 Channels Proteins 0.000 claims abstract description 197
- 230000015654 memory Effects 0.000 claims description 33
- 238000010586 diagram Methods 0.000 description 8
- 239000003990 capacitor Substances 0.000 description 6
- 230000001360 synchronised effect Effects 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004378 air conditioning Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R29/00—Arrangements for measuring or indicating electric quantities not covered by groups G01R19/00 - G01R27/00
- G01R29/18—Indicating phase sequence; Indicating synchronism
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/02—General constructional details
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Remote Monitoring And Control Of Power-Distribution Networks (AREA)
Abstract
The invention relates to a phase sequence detection system, a phase sequence detection method, phase sequence detection equipment and a storage medium, wherein the phase sequence detection system comprises a phase sequence detector and a channel switching device, the phase sequence detector is connected with a plurality of pieces of equipment to form a plurality of phase sequence channels, the channel switching device is arranged on the plurality of phase sequence channels, the phase sequence detector is used for detecting working state data of the opened phase sequence channels, the channel switching device is used for sequentially controlling the opening of each phase sequence channel according to preset conditions, and the equipment corresponding to the opened phase sequence channel is controlled to work according to the working state data of the opened phase sequence channel. Therefore, the invention realizes the detection protection of one phase sequence detector on the phase sequences of a plurality of devices, reduces the number of the phase sequence detectors, and improves the utilization rate of the phase sequence detectors, thereby achieving the purposes of saving energy and reducing cost.
Description
Technical Field
The embodiment of the invention relates to the technical field of power supply protection, in particular to a phase sequence detection system, a phase sequence detection method, phase sequence detection equipment and a storage medium.
Background
The equipment using three-phase power (such as a three-phase fixed-frequency air conditioning unit and the like) can cause the power supply in the equipment to be damaged when running in a phase-missing state or a reverse phase state, so the equipment using three-phase power needs to be provided with a corresponding phase sequence detector, and when the power supply is abnormal, the equipment can timely detect the fault and feed the fault back to the controller of the equipment to carry out power supply protection in the equipment.
At present, in the related art, a phase sequence detector is usually connected with a power supply of one device, and only the phase sequence detector can perform phase sequence detection protection on the power supply of one device, but cannot protect the power supplies of a plurality of devices, so that the utilization rate of the phase sequence detector is low.
Disclosure of Invention
In view of this, embodiments of the present invention provide a phase sequence detection system, method, device and storage medium to solve the technical problem of low utilization rate of a phase sequence detector in the prior art.
In a first aspect, an embodiment of the present invention provides a phase sequence detection system, including:
the phase sequence detector is respectively connected with a plurality of devices to form a plurality of phase sequence channels and is used for detecting the working state data of the opened phase sequence channels;
and the channel switching device is used for sequentially controlling the opening of each phase sequence channel according to a preset condition and controlling the equipment corresponding to the opened phase sequence channel to work according to the working state data of the opened phase sequence channel.
In an optional embodiment, the channel switching device includes:
the signal detection module is connected with the phase sequence detector and used for reading the working state data of the opened phase sequence channel;
the control module is connected with the signal detection module and used for issuing a control instruction according to the working state data and the preset condition;
the on-off modules are connected with the control module, each on-off module is arranged on the corresponding phase sequence channel, and each on-off module is used for controlling the on-off of the corresponding phase sequence channel according to the control instruction;
and the signal output module is connected with the control module and the plurality of equipment and is used for sending the control instruction to the corresponding equipment so as to control the equipment to work.
In an alternative embodiment, the switching module comprises: the device comprises a detection unit, a plurality of protection units and a plurality of on-off units;
the first end of the detection unit is connected with the control module, the second end of the detection unit is connected with the first ends of the plurality of protection units, the second end of each protection unit is connected with the corresponding first end of the on-off unit, and the second end of each on-off unit is connected with the corresponding phase line which is on or off in the phase sequence.
In an alternative embodiment, the preset conditions include: and the detection time of the phase sequence channel reaches the preset time.
In an optional embodiment, the channel switching device further includes:
and the channel selection module is connected with the control module and is used for presetting the number of the phase sequence channels required to be detected.
In an optional embodiment, the channel switching device is further configured to:
and when the detected number of the phase sequence channels is more than or equal to the number of the preset channels, sequentially controlling the opening of each phase sequence channel according to the opening sequence of the preset channels and the preset conditions.
In an optional embodiment, the channel switching device is further configured to:
and controlling all the phase sequence channels to be closed, and sequentially controlling the opening of each phase sequence channel according to the preset condition after all the phase sequence channels are closed.
In a second aspect, an embodiment of the present invention further provides a phase sequence detection method, which is applied to the phase sequence detection system described above, where the phase sequence detection method includes:
controlling the opening of the corresponding phase sequence channel according to a preset condition;
acquiring working state data of the opened phase sequence channel;
and controlling the equipment corresponding to the opened phase sequence channel to work according to the working state data of the opened phase sequence channel.
In a third aspect, an embodiment of the present invention further provides an electronic device, including: a processor and a memory, the processor being configured to execute a phase sequence detection method program stored in the memory to implement the phase sequence detection method as described above.
In a fourth aspect, an embodiment of the present invention further provides a storage medium, where the storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement the phase sequence detection method described above.
The phase sequence detection system provided by the embodiment of the invention comprises a phase sequence detector and a channel switching device, wherein the phase sequence detector is respectively connected with a plurality of devices to form a plurality of phase sequence channels, the channel switching device is arranged on the plurality of phase sequence channels, the phase sequence detector is used for detecting the working state data of the opened phase sequence channels, the channel switching device is used for sequentially controlling the opening of each phase sequence channel according to a preset condition, and the devices corresponding to the opened phase sequence channels are controlled to work according to the working state data of the opened phase sequence channels. The embodiment of the invention realizes the detection protection of one phase sequence detector on the phase sequences of a plurality of devices through the phase sequence detection system, reduces the number of the phase sequence detectors, and improves the utilization rate of the phase sequence detectors, thereby achieving the purposes of saving energy and reducing cost.
Drawings
Fig. 1 is a schematic structural diagram of a phase sequence detection system according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another phase sequence detection system provided in the embodiment of the present invention;
fig. 3 is a schematic structural diagram of a switching module according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a switching module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a working flow of a phase sequence detection system according to an embodiment of the present invention;
FIG. 6 is a flow chart of a phase sequence detection method according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention;
in the above drawings:
10. a phase sequence detector; 20. a channel switching device; 21. a signal detection module; 22. a control module; 23. a switching module; 231. a detection unit; 232. a protection unit; 233. the on-off unit 24 and the signal output module; 25. a channel selection module; 30. equipment;
400. an electronic device; 401. a processor; 402. a memory; 4021. an operating system; 4022. an application program; 403. a user interface; 404. a network interface; 405. a bus system.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to solve the technical problem of low utilization rate of the phase sequence detector in the prior art, the phase sequence detection system provided by the embodiment of the invention realizes the detection protection of one phase sequence detector on the phase sequences of a plurality of devices, reduces the number of the phase sequence detectors, and improves the utilization rate of the phase sequence detectors, thereby achieving the purposes of saving energy and reducing cost.
For the convenience of understanding of the embodiments of the present invention, the following description will be further explained with reference to specific embodiments, which are not to be construed as limiting the embodiments of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a phase sequence detection system according to an embodiment of the present invention. The phase sequence detection system provided by the embodiment of the invention comprises a phase sequence detector 10 and a channel switching device 20, wherein the phase sequence detector 10 is connected with a plurality of devices 30 to form a plurality of phase sequence channels, each phase sequence channel comprises four phase lines, namely L1, L2, L3 and N, the number of the devices 30 is consistent with that of the phase sequence channels, and the channel switching device 20 is arranged on the plurality of phase sequence channels.
The phase sequence detector 10 is used for detecting the working state data of the opened phase sequence channel. The working state data includes phase-missing state data, reverse phase state data, normal state data, and the like. When the phase sequence detector 10 detects the working state data corresponding to the opened phase sequence channel, the working state data is output through the output port of the phase sequence detector 10.
The channel switching device 20 is used for controlling the on-off of the phase sequence channel. Specifically, the channel switching device 20 sequentially controls the opening of each phase-sequence channel according to a preset condition, and controls the device corresponding to the opened phase-sequence channel to operate according to the operating state data of the opened phase-sequence channel.
In this embodiment, the preset condition is that the detection time of the phase sequence channel reaches a preset time, where the preset time may be set according to actual needs, and this embodiment does not specifically limit this. The preset time in this embodiment is preferably 500 ms. Specifically, in the present embodiment, a time-division multiplexing manner is adopted, and one phase-sequence channel is opened every other preset time, that is, when the detection time of the opened first phase-sequence channel reaches the preset time, the channel switching device 20 controls the closing of the phase-sequence channel, and the channel switching device 20 controls the opening of the next phase-sequence channel, so as to implement the detection of the working state data of one phase-sequence channel by the phase-sequence detector 10 within the preset time.
In this embodiment, the channel switching device 20 is further configured to: and controlling the plurality of phase sequence channels to be closed completely, and after the plurality of phase sequence channels are closed completely, sequentially controlling the opening of each phase sequence channel according to preset conditions.
Specifically, in order to ensure that each phase sequence channel is accurately opened, after the phase sequence detection system is powered on, the plurality of phase sequence channels are completely closed, and then the opening of each phase sequence channel is sequentially controlled according to preset conditions.
In this embodiment, referring to fig. 2, the channel switching device 20 includes a signal detection module 21, a control module 22, a plurality of on-off modules 23, and a signal output module 24, where the signal detection module 21 is connected to the phase sequence detector 10, the control module 22 is connected to the signal detection module 21, the plurality of on-off modules 23 are all connected to the control module 22, each on-off module 23 is disposed on a corresponding phase sequence channel, the number of the on-off modules 23 is the same as the number of the devices 30, the signal output module 24 is connected to the control module 22, and the signal output module 24 is further connected to the plurality of devices 30.
The signal detection module 21 is configured to read working state data of the opened phase-sequence channel. Specifically, the signal detection module 21 is connected to an output port of the phase sequence detector 10, and the signal detection module 21 reads the operating state data of the opened phase sequence channel from an output port of the phase sequence detector 10 and sends the read operating state data to the control module 22. The working state data may be default phase state data, inverse phase state data, normal state data, etc. In this embodiment, the signal detection module 21 mainly includes electronic components such as a capacitor, a resistor, and an optical coupler.
The control module 22 is used for receiving data and issuing commands. Specifically, the control module 22 is configured to receive the working state data sent by the signal detection module 21, and issue a control instruction according to the working state data and a preset condition. Specifically, the control instruction includes a first control instruction and a second control instruction, and the control module 22 issues the first control instruction according to the received working state data and issues the second control instruction according to a preset condition. The first control instruction may specifically be a stop work instruction, a continue work instruction, and the like, and when the control module 22 receives fault state data (that is, phase-lacking state data, reverse phase state data, and the like), that is, when the opened phase sequence channel fails, the control module 22 issues the stop work instruction; when the control module 22 receives the normal state data, that is, the opened phase sequence channel does not have a fault, the control module 22 issues a continuous working instruction. The second control command may be a channel opening command and a channel closing command. More specifically, the control module 22 is further configured to issue a third control instruction, and after the phase sequence detection system is powered on, control all of the multiple phase sequence channels in the phase sequence detection system to be closed according to the third control instruction, where the third control instruction is a channel all-closing instruction. In this embodiment, the control module 22 is mainly composed of a single chip, a crystal oscillator, an I/O port, a peripheral driving circuit, and the like.
Each switching module 23 is used for controlling the switching of the corresponding phase sequence channel. Specifically, when the on-off module 23 receives a channel opening instruction issued by the control module 22, the phase sequence channel corresponding to the on-off module 23 is controlled to be opened (that is, the connection between the phase sequence detector 10 and the corresponding device 30 is conducted); when the on-off module 23 receives the channel closing instruction sent by the control module 22, the phase sequence channel corresponding to the on-off module 23 is controlled to be closed (i.e. the connection between the phase sequence detector 10 and the corresponding device 30 is turned off).
In this embodiment, referring to fig. 3, each on-off module 23 includes a detection unit 231, a plurality of protection units 232, and a plurality of on-off units 233, wherein a first end of the detection unit 231 is connected to the control module 22, a second end of the detection unit 231 is connected to first ends of the plurality of protection units 232, a second end of each protection unit 232 is connected to a first end of the corresponding on-off unit 233, and a second end of each on-off unit 233 is connected to a phase line of the corresponding phase-sequential channel. Specifically, each phase sequence channel includes L1 phase lines, L2 phase lines, L3 phase lines, and N phase lines, each on-off module 23 includes four protection units 232 and four on-off units 233, and the four on-off units 233 are connected to the L1 phase lines, the L2 phase lines, the L3 phase lines, and the N phase lines, respectively. The detecting unit 231 is configured to detect a signal of a second control instruction output by the control module 22, and is configured to control the corresponding on-off module 23 to operate or stop operating according to the signal of the second control instruction, the on-off unit 233 is configured to open or close a corresponding phase sequence channel, and the protecting unit 232 is configured to protect the on-off unit 233.
Specifically, referring to fig. 4, the detection unit 231 includes a first switch K1A first resistor R1A first triode Q1A second resistor R2A third resistor R3And a second triode Q2Wherein the first triode is NPN type triode, the second triode is PNP type triode, and the first switch K1Is connected to the control module 22, a first switch K1Second terminal of and first triode Q1Is connected to the base of a first triode Q1Is connected to ground, a first triode Q1Collector and second resistor R2Is connected to a first terminal of a first resistor R1Is connected to the first switch K1Second terminal of and first triode Q1On the connection line of the base electrode, a first resistor R1Is connected to ground, a second resistor R2Second end of and a second triode Q2Is connected to the base of a second triode Q2The emitting electrode of the second triode Q is connected with the positive electrode of a VCC power supply2Is connected to first terminals of a plurality of protection units 232, and a third resistor R3Is connected to the second resistor R2Second terminal of the second transistor and a second triode Q2On the connection line of the base, a third resistor R3And the second terminal of the second diode is connected with the positive electrode of the VCC power supply.
Each protection unit 232 includes a fourth resistor R4A fifth resistor R5A sixth resistor R6Diode D1Capacitor C1And a zener diode ZD1Wherein the second triode Q2Collector and diode D1First terminal and fourth resistor R4Is connected to a first terminal of a diode D1Second terminal and fifth resistor R5Is connected to the zener diode ZD1Capacitor C1And a sixth resistor R6Connected in parallel, a fourth resistor R4And a fifth resistor R5Second terminal of and zener diode ZD1Capacitor C1And a sixth resistor R6Is connected to the zener diode ZD1Capacitor C1And a sixth resistor R6And also with the on-off unit 233.
The on-off unit 233 is a field effect transistor in this embodiment, wherein the on-off unit 233 first terminal and zener diode ZD1Capacitor C1And a sixth resistor R6The second terminal of the on-off unit 233 is connected to the input terminal (L1_ IN, L2_ IN, L3_ IN, or N _ IN) of the corresponding phase line, and the third terminal of the on-off unit 233 is connected to the output terminal (L1_ OUT, L2_ OUT, L3_ OUT, or N _ OUT) of the corresponding phase line. When the first switch K1 receives a high signal, the second terminal and the third terminal between each on-off unit 233 are connected, so that the input terminal and the input terminal of the corresponding phase line are connected. In this embodiment, the on-off unit 233 may also use an IGBT instead of a field effect transistor, and may be specifically set according to actual needs.
More specifically, the on-off module 23 controls the corresponding phase sequence channel to be opened according to the following working principle:
first switch K1When receiving a high level signal of a turn-on control instruction issued by the control module 22, the first resistor R is enabled to be connected to the first resistor R1A voltage difference occurs between both ends of the first transistor Q1Is turned on to make the second resistor R2A voltage difference occurs between both ends of the second transistor Q, thereby making the second transistor Q2And conducting, so that a voltage difference occurs between two ends of each fet Q3, Q4, Q5 and Q6, and the L1 phase line, L2 phase line, L3 phase line and N phase line are conducted with the phase sequence detector 10, so that the corresponding phase sequence channel is conducted.
The signal output module 24 is configured to send the control instruction sent by the control module 22 to the corresponding device 30, so as to control the device 30 to work. The signal output module 24 sends the first control instruction to the corresponding device 30 through the signal output module 24. Specifically, the signal output module 24 may be a +12V signal line, an RS485 communication line, a UART communication line, and the like, and the signal output module 24 may be set according to actual needs, which is not limited in this embodiment.
In this embodiment, the channel switching device 20 further includes: and a channel selection module 25, wherein the channel selection module 25 is connected to the control module 22 and is used for presetting the number of phase sequence channels to be detected. Specifically, the channel selection module 25 may be a dial switch, specifically, the selection of the channel selection module 25 may be selected according to actual needs, and this embodiment is not particularly limited. In this embodiment, by providing the channel selection module 25, the flexibility of using the phase sequence detection system is improved, so that a user can select the number of phase sequence channels to be detected according to actual needs, thereby facilitating the use of the user.
In this embodiment, the channel switching device 20 is further configured to: and when the number of the detected phase sequence channels is larger than the number of the preset channels, sequentially controlling the opening of each phase sequence channel according to the opening sequence of the preset channels and the preset conditions. Specifically, the control module 22 in the channel switching device 20 sequentially controls the opening of each phase-sequence channel according to the preset channel opening sequence and the preset condition when the number of detected phase-sequence channels is greater than the preset channel number.
In this embodiment, it should be noted that, when the number of the detected phase-sequence channels is greater than or equal to the number of the preset channels, the opening of each phase-sequence channel may be sequentially controlled according to the opening sequence of the sequential channels or the opening sequence of the reverse-sequence channels and the preset condition. The preset number of channels may be selected according to the channel selection module 25, or may be a fixed value stored therein.
As an example, referring to fig. 5, a process of sequentially detecting the operating state data of each phase-sequence channel is described as follows:
if the number of the preset channels is N, after the phase sequence detection system is powered on, the control module 22 issues a third control instruction to all the on-off modules 23, so that each on-off module 23 controls the corresponding phase sequence channel to be closed, that is, the control module 22 initializes to make the detection time T equal to 0, and the number N of the detected channels equal to 0.
When detecting each phase sequence channel in turn, when the detecting time T does not reach the preset time, increasing the detecting time T (T + +) according to the preset time interval, when the detecting time T reaches the preset time, judging whether the number of the detected phase sequence channels is greater than N, when the number of the detected phase sequence channels is less than N, increasing the number of the phase sequence channels by 1 (namely N + +), the control module 22 issuing a channel opening instruction to the on-off module 23 corresponding to the first phase sequence channel, so that the on-off module 23 controls the first phase sequence channel to be opened, and in the preset time, the phase sequence detector 10 detecting the working state data of the first phase sequence channel, the control module 22 generating a first control instruction according to the working state data, and sending the first control instruction to the corresponding equipment 30 through the signal output module 24, when the detecting time T of the first phase sequence channel reaches the preset time, the control module 22 issuing a channel closing instruction to close the first phase sequence channel, and sequentially detecting the working state data of the N-1 phase sequence channels according to the detection method of the first phase sequence channel. When the number of the detected phase sequence channels is larger than or equal to N, detecting the working state data of the corresponding phase sequence channel according to the channel opening sequence (sequence opening sequence) from the first phase sequence channel to the Nth phase sequence channel or detecting the working state data of the corresponding phase sequence channel according to the channel opening sequence (reverse sequence opening sequence) from the Nth phase sequence channel to the first phase sequence channel.
The phase sequence detection system provided by the embodiment of the invention realizes the detection and protection of one phase sequence detector 10 on the phase sequences of a plurality of devices 30, reduces the number of the phase sequence detectors 10, and improves the utilization rate of the phase sequence detectors 10, thereby achieving the purposes of saving energy and reducing cost.
An embodiment of the present invention further provides a phase sequence detection method, which is applied to the phase sequence detection system described above, and referring to fig. 6, the phase sequence detection method provided in this embodiment includes:
s1: controlling the opening of the corresponding phase sequence channel according to a preset condition;
s2: acquiring working state data of the opened phase sequence channel;
s3: and controlling the equipment 30 corresponding to the opened phase-sequence channel to work according to the working state data of the opened phase-sequence channel.
The preset condition is specifically that the detection time of the phase sequence channel reaches the preset time, the preset time in this embodiment can be selected according to actual needs, and this embodiment is not specifically limited. The preset time in this embodiment is preferably 500 ms.
In this embodiment, the step S1 specifically includes:
and when the number of the detected phase sequence channels is larger than or equal to the number of the preset channels, sequentially controlling the opening of each phase sequence channel according to the opening sequence of the preset channels and preset conditions.
In this embodiment, it should be noted that, when the number of the detected phase-sequence channels is greater than or equal to the number of the preset channels, the opening of each phase-sequence channel may be sequentially controlled according to the opening sequence of the sequential channels or the opening sequence of the reverse-sequential channels and the preset condition.
The phase sequence detection method provided by the embodiment realizes the detection protection of one phase sequence detector on the phase sequences of a plurality of devices 30, reduces the number of the phase sequence detectors, and improves the utilization rate of the phase sequence detectors, thereby achieving the purposes of saving energy and reducing cost.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, where the electronic device 400 shown in fig. 7 includes: at least one processor 401, memory 402, at least one network interface 404, and other user interfaces 403. The various components in the electronic device 400 are coupled together by a bus system 405. It is understood that the bus system 405 is used to enable connection communication between these components. The bus system 405 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 405 in fig. 7.
The user interface 403 may include, among other things, a display, a keyboard, or a pointing device (e.g., a mouse, trackball, touch pad, or touch screen, among others.
It will be appreciated that memory 402 in embodiments of the invention may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (ddr Data Rate SDRAM, ddr SDRAM), Enhanced Synchronous SDRAM (ESDRAM), synchlronous SDRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 402 described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In some embodiments, memory 402 stores the following elements, executable units or data structures, or a subset thereof, or an expanded set thereof: an operating system 4021 and application programs 4022.
The operating system 4021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, and is configured to implement various basic services and process hardware-based tasks. The application programs 4022 include various application programs, such as a Media Player (Media Player), a Browser (Browser), and the like, for implementing various application services. A program for implementing the method according to the embodiment of the present invention may be included in the application 4022.
In this embodiment of the present invention, by calling a program or an instruction stored in the memory 402, specifically, a program or an instruction stored in the application 4022, the processor 401 is configured to execute the method steps provided by the method embodiments, for example, including: controlling the opening of the corresponding phase sequence channel according to a preset condition; acquiring working data of the opened phase sequence channel; and controlling equipment corresponding to the opened phase-sequence channel to work according to the working state data of the opened phase-sequence channel.
The method disclosed in the above embodiments of the present invention may be applied to the processor 401, or implemented by the processor 401. The processor 401 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 401. The Processor 401 may be a general-purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software elements in the decoding processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in the memory 402, and the processor 401 reads the information in the memory 402 and completes the steps of the method in combination with the hardware.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the Processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented by means of units performing the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
The embodiment of the invention also provides a storage medium (computer readable storage medium). The storage medium herein stores one or more programs. Among others, the storage medium may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, a hard disk, or a solid state disk; the memory may also comprise a combination of memories of the kind described above.
When one or more programs in the storage medium are executable by one or more processors to implement the phase sequence detection method described above as being performed on the phase sequence detection apparatus side.
The processor is configured to execute a phase sequence detection program stored in the memory to implement the following steps of the phase sequence detection method executed on the phase sequence detection apparatus side: controlling the opening of the corresponding phase sequence channel according to a preset condition; acquiring working data of the opened phase sequence channel; controlling the equipment corresponding to the opened phase-sequence channel to work according to the working state data of the opened phase-sequence channel
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (10)
1. A phase sequence detection system, comprising:
the phase sequence detector is respectively connected with a plurality of devices to form a plurality of phase sequence channels and is used for detecting the working state data of the opened phase sequence channels;
and the channel switching device is used for sequentially controlling the opening of each phase sequence channel according to a preset condition and controlling the equipment corresponding to the opened phase sequence channel to work according to the working state data of the opened phase sequence channel.
2. The phase sequence detection system according to claim 1, wherein the channel switching device comprises:
the signal detection module is connected with the phase sequence detector and used for reading the working state data of the opened phase sequence channel;
the control module is connected with the signal detection module and used for issuing a control instruction according to the working state data and the preset condition;
the on-off modules are connected with the control module, each on-off module is arranged on the corresponding phase sequence channel, and each on-off module is used for controlling the on-off of the corresponding phase sequence channel according to the control instruction;
and the signal output module is connected with the control module and the plurality of equipment and is used for sending the control instruction to the corresponding equipment so as to control the equipment to work.
3. The phase sequence detection system of claim 2, wherein the on-off module comprises: the device comprises a detection unit, a plurality of protection units and a plurality of on-off units;
the first end of the detection unit is connected with the control module, the second end of the detection unit is connected with the first ends of the plurality of protection units, the second end of each protection unit is connected with the corresponding first end of the on-off unit, and the second end of each on-off unit is connected with the corresponding phase line of the phase sequence channel.
4. The phase sequence detection system according to claim 2, wherein the preset condition comprises: and the detection time of the phase sequence channel reaches the preset time.
5. The phase sequence detection system according to claim 2, wherein the channel switching device further comprises:
and the channel selection module is connected with the control module and is used for presetting the number of the phase sequence channels required to be detected.
6. The phase sequence detection system of claim 5, wherein the channel switching device is further configured to:
and when the detected number of the phase sequence channels is more than or equal to the number of the preset channels, sequentially controlling the opening of each phase sequence channel according to the opening sequence of the preset channels and the preset conditions.
7. The phase sequence detection system of claim 2, wherein the channel switching device is further configured to:
and controlling all the phase sequence channels to be closed, and when all the phase sequence channels are closed, sequentially controlling the opening of each phase sequence channel according to the preset condition.
8. A phase sequence detection method applied to the phase sequence detection system according to any one of claims 1 to 7, the phase sequence detection method comprising:
controlling to open a corresponding phase sequence channel according to a preset condition;
acquiring working state data of the opened phase sequence channel;
and controlling the equipment corresponding to the opened phase sequence channel to work according to the working state data of the opened phase sequence channel.
9. An electronic device, comprising: a processor and a memory, the processor being configured to execute a phase sequence detection method program stored in the memory to implement the phase sequence detection method recited in claim 8.
10. A storage medium storing one or more programs, the one or more programs being executable by one or more processors to implement the phase sequence detection method of claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111418751.1A CN114137327A (en) | 2021-11-25 | 2021-11-25 | Phase sequence detection system, method, equipment and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111418751.1A CN114137327A (en) | 2021-11-25 | 2021-11-25 | Phase sequence detection system, method, equipment and storage medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN114137327A true CN114137327A (en) | 2022-03-04 |
Family
ID=80388742
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111418751.1A Pending CN114137327A (en) | 2021-11-25 | 2021-11-25 | Phase sequence detection system, method, equipment and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114137327A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE9206307U1 (en) * | 1992-05-11 | 1992-07-23 | Ch. Beha GmbH Technische Neuentwicklungen, 7804 Glottertal | Rotary field direction measuring device |
| CN104297698A (en) * | 2013-11-29 | 2015-01-21 | 中国航空工业集团公司洛阳电光设备研究所 | Detection device for power supply assembly |
| US20190072596A1 (en) * | 2017-09-06 | 2019-03-07 | Fluke Corporation | Multiple phase measurement device |
| CN211554276U (en) * | 2020-01-07 | 2020-09-22 | 佛山市顺德区骏达电子有限公司 | Multifunctional auxiliary detection tool circuit |
| CN112731216A (en) * | 2020-12-07 | 2021-04-30 | 江阴长仪集团有限公司 | Electric power monitoring terminal for realizing automatic correction of phase sequence and correction method |
-
2021
- 2021-11-25 CN CN202111418751.1A patent/CN114137327A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE9206307U1 (en) * | 1992-05-11 | 1992-07-23 | Ch. Beha GmbH Technische Neuentwicklungen, 7804 Glottertal | Rotary field direction measuring device |
| CN104297698A (en) * | 2013-11-29 | 2015-01-21 | 中国航空工业集团公司洛阳电光设备研究所 | Detection device for power supply assembly |
| US20190072596A1 (en) * | 2017-09-06 | 2019-03-07 | Fluke Corporation | Multiple phase measurement device |
| CN211554276U (en) * | 2020-01-07 | 2020-09-22 | 佛山市顺德区骏达电子有限公司 | Multifunctional auxiliary detection tool circuit |
| CN112731216A (en) * | 2020-12-07 | 2021-04-30 | 江阴长仪集团有限公司 | Electric power monitoring terminal for realizing automatic correction of phase sequence and correction method |
Non-Patent Citations (1)
| Title |
|---|
| 杜通波 等: "嵌入式相电检测及相序调整系统设计", 《中国计量学院学报》 * |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR950009735A (en) | Nonvolatile Semiconductor Memory | |
| US5781485A (en) | Apparatus and method for controlling operating mode in semiconductor memory device | |
| KR970063265A (en) | Semiconductor memory | |
| KR980005018A (en) | How to Program Binary States in Nonvolatile Memory Cells and Nonvolatile Memory | |
| CN105677546A (en) | Method for displaying BIOS debugging information and computer equipment applying method | |
| US20140281630A1 (en) | Electronic device with two driving structures | |
| CN114137327A (en) | Phase sequence detection system, method, equipment and storage medium | |
| US7420866B2 (en) | Method and system of operating mode detection | |
| CN113223566A (en) | Control system and control method of memory | |
| JPS5855591B2 (en) | Power supply for bubble memory unit | |
| CN102866864B (en) | Realize method and the memory device of One Time Programmable storage | |
| CN113127246B (en) | Watchdog circuit, control method and watchdog chip | |
| JPS6217852A (en) | Device for protecting data contents in eeprom | |
| CN110620424B (en) | Power supply switching circuit and method for backup power supply domain | |
| CN109210688A (en) | Multi fan clarifier control method and device, clarifier | |
| JP3888571B2 (en) | Mode switching circuit | |
| KR910003471A (en) | Circuit arrangement for the control of several electrical receivers, which may be in at least two states | |
| US20230230641A1 (en) | Data storage device having over-voltage detection and protection | |
| CN104750502B (en) | A kind of wire jumping method and device | |
| KR970063274A (en) | Test method of semiconductor memory device having redundant cell array | |
| KR950025505A (en) | Computer Power Management Device and Method | |
| KR100277901B1 (en) | One chip micro computer | |
| SU1012207A1 (en) | Stepping motor program control device | |
| KR920007908B1 (en) | The eeprom increased double in the life cycle and the control device | |
| CN117318540A (en) | Motor control method, device, equipment and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20220304 |
|
| RJ01 | Rejection of invention patent application after publication |