CN114127915A

CN114127915A - Detection circuit and sensor

Info

Publication number: CN114127915A
Application number: CN201980098408.8A
Authority: CN
Inventors: 曾秋玲; 刘燕翔; 陈赞锋; 夏禹
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-07-15
Filing date: 2019-07-15
Publication date: 2022-03-01
Also published as: WO2021007737A1

Abstract

A detection circuit for detecting the effect of stress on an electrical characteristic, the detection circuit comprising: the device comprises a PMOS (P-channel metal oxide semiconductor) tube main self-oscillation ring (101), an NMOS (N-channel metal oxide semiconductor) tube main self-oscillation ring (102) and a frequency reading module (103); the number of PMOS tubes in a signal path of the PMOS tube main self-oscillation ring (101) is larger than that of NMOS tubes; the number of NMOS tubes in a signal path of the NMOS tube main self-oscillation ring (102) is larger than that of PMOS tubes; the frequency reading module (103) is used for reading a frequency signal output by the PMOS tube main self-oscillation ring (101) or the NMOS tube main self-oscillation ring (102). The frequency signal output by the NMOS transistor main self-oscillation ring (102) represents the influence of stress on the electrical characteristics of the NMOS transistor, and the frequency signal output by the PMOS transistor main self-oscillation ring (101) represents the influence of stress on the electrical characteristics of the PMOS transistor. The manufacturing process of the circuit can be improved according to the influence of the stress on the NMOS tube and the influence of the PMOS tube, so that the influence of the stress on the electrical characteristics of the circuit is reduced.

Description

Detection circuit and sensor

Technical Field

The invention relates to the field of electricity, in particular to a detection circuit and a sensor.

Background

Stress is inevitably generated in the manufacturing and packaging processes of the integrated circuit, and particularly, the influence of the stress on the semiconductor device can have a significant influence on the carrier mobility of the semiconductor device, and further, the behavior of analog and digital circuits can be influenced, and even the circuit can be failed.

In a self-oscillation ring of a Complementary Metal Oxide Semiconductor (CMOS) inverter based on a 45-degree active region direction, the influence of stress at the position where the CMOS inverter is placed on the frequency can be obtained through the ratio of the frequencies of the self-oscillation ring of the CMOS inverter in two different directions of R0 and R45, and the influence of the stress at the position where the CMOS inverter is placed on the electrical characteristics of a device can be reflected.

The above embodiments reflect the effect of stress on the electrical characteristics of the placed CMOS inverter. The CMOS phase inverter comprises an NMOS transistor and a PMOS transistor, the influence of stress on the electrical characteristics of the NMOS transistor and the influence of stress on the electrical characteristics of the PMOS transistor can be different, and the scheme cannot distinguish the influence of stress on the electrical characteristics of the NMOS transistor from the influence of stress on the electrical characteristics of the PMOS transistor.

Disclosure of Invention

The embodiment of the application provides a detection circuitry and sensor, and this detection circuitry is used for detecting the influence of stress to the electric current of NMOS pipe and PMOS pipe in the circuit, and this detection circuitry includes:

the PMOS tube main self-oscillation ring, the NMOS tube main self-oscillation ring and the frequency reading module are arranged in the circuit board; the number of PMOS tubes in a signal path of the PMOS tube main self-oscillation ring is larger than that of NMOS tubes; the number of NMOS tubes in a signal path of the NMOS tube main self-oscillation ring is greater than that of PMOS tubes; the frequency reading module is used for reading the frequency signal output by the PMOS tube main self-oscillation ring or the NMOS tube main self-oscillation ring. In a first aspect, the detection circuit provided by this embodiment includes a PMOS transistor main self-oscillation ring and an NMOS transistor main self-oscillation ring, where a frequency signal output by the NMOS transistor main self-oscillation ring represents an influence of stress on an electrical characteristic of the NMOS transistor, and a frequency signal output by the PMOS transistor main self-oscillation ring represents an influence of stress on an electrical characteristic of the PMOS transistor. The manufacturing process of the circuit can be improved according to the influence of the stress on the NMOS tube and the influence of the PMOS tube, so that the influence of the stress on the electrical characteristics of the circuit is reduced.

Based on the first aspect of the embodiments of the present application, in a first implementation manner of the first aspect of the embodiments of the present application, the PMOS transistor main self-oscillating ring includes an even number of nor gates connected in series, and the number of PMOS transistors connected in series on a signal path in each nor gate of the even number of nor gates is greater than the number of NMOS transistors; the NMOS tube main self-oscillation ring comprises even number of NAND gates which are connected in series, and the number of NMOS tubes which are connected in series on a signal path in each NAND gate in the even number of NAND gates is larger than that of PMOS tubes.

Based on the first implementation manner of the first aspect of the embodiment of the present application, in the second implementation manner of the first aspect of the embodiment of the present application, the PMOS transistor main self-oscillation ring includes a first nand gate, an output of the first nand gate is coupled to an input terminal of the even number of nor gates in the series, the first nand gate includes a first input terminal and a second input terminal, the first input terminal is connected to the control signal, and the second input terminal is connected to an output terminal of the even number of nor gates in the series.

Based on the second implementation manner of the first aspect of the embodiment of the present application, in a third implementation manner of the first aspect of the embodiment of the present application, each nor gate of the even number of nor gates includes P input terminals, where P is an integer greater than or equal to 2; a third input end of the P input ends is connected with an output end of the first nand gate, and other input ends of the P input ends except the third input end are connected with a low level, and the third input end is any one of the P input ends.

Based on the first possible implementation manner of the first aspect of the embodiment of the present application, in a fourth implementation manner of the first aspect of the embodiment of the present application, the NMOS transistor main self-oscillating ring includes a second nand gate, an output of the second nand gate is coupled to an input terminal of the even number of nand gates in series, the second nand gate includes a fourth input terminal and a fifth input terminal, the fourth input terminal is connected to the control signal, and the fifth input terminal is connected to an output terminal of the even number of nand gates in series.

Based on the fourth possible implementation manner of the first aspect of the embodiment of the present application, in a fifth implementation manner of the first aspect of the embodiment of the present application, each nand gate in the even number of nand gates includes L input ends, where L is an integer greater than or equal to 2; a sixth input end of the L input ends is connected to an output of the second nand gate, and other input ends of the L input ends except the sixth input end are connected to a high level, and the sixth input end is any one of the L input ends.

Based on the second possible implementation manner of the first aspect to the fifth possible implementation manner of the first aspect of the embodiment of the present application, in a sixth possible implementation manner of the first aspect, the circuit further includes an inverter, where the inverter is configured to couple the control signal to the first input terminal of the first nand gate after inverting the control signal.

Based on the first aspect of the present application to the fifth possible implementation manner of the first aspect, in a seventh possible implementation manner of the first aspect, the circuit further includes a multiplexer MUX, where the MUX is configured to select to provide an output of the PMOS-dominant self-oscillation loop or the NMOS-dominant self-oscillation loop to the frequency reading module.

Based on the seventh possible implementation manner of the first aspect of the embodiment of the present application, in an eighth possible implementation manner of the first aspect, the frequency reading module includes a frequency divider, a register, and a system clock, the frequency divider is connected to output ends of the PMOS transistor main self-oscillation ring and the NMOS transistor main self-oscillation ring, and the frequency divider is further connected to the register and the system clock, respectively.

A second aspect of an embodiment of the present application provides a sensor, where the sensor includes the detection circuit in the first aspect and any one of the possible implementation manners of the first aspect.

A third aspect of an embodiment of the present application provides a chip, where the chip includes the first aspect and a detection circuit in any possible implementation manner of the first aspect.

The present embodiment provides a detection circuit for detecting an influence of stress on an electrical characteristic, the detection circuit including: the PMOS tube main self-oscillation ring, the NMOS tube main self-oscillation ring and the frequency reading module are arranged in the circuit board; the number of PMOS tubes in a signal path of the PMOS tube main self-oscillation ring is larger than that of NMOS tubes; the number of NMOS tubes in a signal path of the NMOS tube main self-oscillation ring is greater than that of PMOS tubes; the frequency reading module is used for reading the frequency signal output by the PMOS tube main self-oscillation ring or the NMOS tube main self-oscillation ring. The detection circuit provided by the embodiment comprises a PMOS tube main self-oscillation ring and an NMOS tube main self-oscillation ring, wherein the frequency signal output by the NMOS tube main self-oscillation ring represents the influence of stress on the electrical characteristics of the NMOS tube, and the frequency signal output by the PMOS tube main self-oscillation ring represents the influence of stress on the electrical characteristics of the PMOS tube. The manufacturing process of the circuit can be improved according to the influence of the stress on the NMOS tube and the influence of the PMOS tube, so that the influence of the stress on the electrical characteristics of the circuit is reduced.

Drawings

FIG. 1 is a schematic diagram of a circuit for detecting the effect of stress on electrical characteristics according to an embodiment of the present disclosure;

fig. 2 is a schematic structural diagram of a nor gate 1012 according to an embodiment of the present disclosure;

fig. 3 is a schematic structural diagram of a nand gate 1022 according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

The terms "first," "second," "third," "fourth," and the like in the description and in the claims of the present application and in the drawings described above, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It will be appreciated that the data so used may be interchanged under appropriate circumstances such that the embodiments described herein may be practiced otherwise than as specifically illustrated or described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

The embodiment of the application provides a detection circuit and a sensor, wherein the detection circuit generates a high-frequency signal through a PMOS tube main self-oscillation ring and an NMOS main self-oscillation ring, the high-frequency signal is subjected to frequency reduction through a frequency divider, a system clock counts the signal after the frequency reduction, and a frequency value obtained by counting is stored in a register. The detection circuit can compare the change of the frequency value before and after the detected circuit is packaged, thereby detecting the influence of the packaging process on the stress of the detected circuit.

According to the embodiment of the application, the detection circuit can be placed in the detected integrated circuit, and when the PMOS tube main self-oscillation ring in the detection circuit is in a working state, the detection circuit is used for detecting the influence of stress on the PMOS tube in the integrated circuit. When the NMOS tube main self-oscillation ring in the detection circuit is in a working state, the detection circuit is used for detecting the influence of stress on the NMOS tube in the integrated circuit.

Referring to fig. 1, fig. 1 is a schematic diagram of a detection circuit according to an embodiment of the present disclosure, as shown in fig. 1, the detection circuit includes: a PMOS master oscillator ring 101, an NMOS master oscillator ring 102, and a frequency reading module 103, in this embodiment, the PMOS master oscillator ring 101 refers to a number of PMOS self oscillator rings on a signal path that is greater than the number of NMOS self oscillator rings, and the NMOS master oscillator ring 102 refers to a number of NMOS self oscillator rings on a signal path that is greater than the number of PMOS self oscillator rings.

The PMOS master oscillator ring 101 and the NMOS master oscillator ring 102 provided in the embodiments of the present application are described in detail below.

As shown in fig. 1, the PMOS master oscillator loop 101 includes an even number of nor gates 1012 and a first nand gate 1011 connected in series, where each of the even number of nor gates 1012 includes P inputs, P is an integer greater than or equal to 2, one of the P inputs is connected to an output of the first nand gate 1011, the first nand gate 1011 includes a first input and a second input, the first input is connected to a control signal, and an inverter may be provided between the first input and the control signal. The second input terminal of the first nand gate 1011 is connected to the output terminal Z1 of an even number of nor gates connected in series, only 2 nor gates 1012 with 4 input terminals are illustrated in the PMOS master self-oscillating ring 101 shown in fig. 1, and the 4 input terminals of the nor gates 1012 are a1, a2, A3 and a4, respectively. It should be noted that in practical applications, the number of the nor gates 1012 connected in series is even, for example, 4 nor gates 1012 or 8 nor gates 1012 may also be used, and is not limited herein. Meanwhile, the even number of nor gates 1012 are connected in series, and only the a1 input terminal of each nor gate 1012 is connected to the output terminal of the last nor gate 1012 in the figure, but in actual production, the other input terminal of each nor gate 1012 may be connected to the output terminal of the last nor gate 1012.

In the present embodiment, the number of PMOS serially connected on a signal path in each of the even nor gates 1012 is greater than the number of NMOS, specifically, please refer to fig. 2, fig. 2 is a schematic diagram of one nor gate 1012 of the even nor gates 1012 provided in the present embodiment, as shown in fig. 2, the nor gate 1012 provided in the present embodiment is composed of NMOS and PMOS, it can be understood that there are a plurality of nor gates in a digital cell library, including different numbers of input pins and different numbers of N/P MOS, wherein in the present embodiment, only the 4-input nor gate 1012 shown in fig. 2 is used for illustration, and of course, in practical applications, the nor gate 1012 may also be an even number of inputs such as 2 input or 8 input. It should be noted that, in this embodiment, the other input of the input terminals of each nor gate in the even number of nor gates, except for one input for connecting the adjacent nor gate, is switched to the low level.

Specifically, three input pins a2, A3, a4 of the nor gate 1012 shown in fig. 2 are switched to low level 0, 3 PMOS transistors whose gates are connected to a2, A3, a4 are in an open state, and 3 NMOS transistors whose gates are connected to a2, A3, a4 are in a closed state.

When a1 inputs a low level of 0, all PMOS transistors in the nor gate 1012 of fig. 2 are turned on, and all NMOS transistors are turned off. When a1 inputs high level 1, the PMOS tube with the grid connected with A1 is in a closed state, and the NMOS tube with the grid connected with A1 is in an open state. At this time, 3 PMOS transistors and 1 NMOS transistor in the nor gate 1012 shown in fig. 2 are in an open state. Therefore, in both cases, the number of PMOS transistors in the nor gate 1012 in the open state is more than the number of NMOS transistors.

Therefore, in this embodiment, when the electrical characteristics of the PMOS transistor change due to stress, the electrical characteristics of the PMOS transistor reflected by the frequency signal output by the PMOS transistor main self-oscillation ring 101 change, obviously, the circuit for detecting the influence of stress on the electrical characteristics provided by this embodiment may determine the influence of stress on the PMOS transistor according to the frequency signal output by the PMOS transistor main self-oscillation ring 101, so as to improve the manufacturing process of the integrated circuit according to the influence of stress on the PMOS transistor, improve the manufacturing process accuracy of the integrated circuit, and reduce the influence of stress on the electrical characteristics of the PMOS transistor of the integrated circuit.

As shown in fig. 1, the NMOS master self-oscillating ring 102 includes an even number of nand gates 1022 and a second nand gate 1021 in series, where each nand gate 1022 in the even number of nand gates 1022 includes L inputs, L is an integer greater than or equal to 2, one of the L inputs is connected to an output of the second nand gate 1021, and the second nand gate 1021 includes a fourth input and a fifth input. The fourth input terminal is connected with the control signal, the fifth input terminal is connected with the output terminal Z2 of an even number of NAND gates connected in series, only 2 NAND gates 1022 with 4 input segments are illustrated in the NMOS master self-oscillating ring 102 shown in FIG. 1, and 4 inputs of the NAND gates 1022 are respectively A1, A2, A3 and A4 as shown in FIG. 1. Note that in practical applications, the number of the nand gates 1022 in series is an even number, for example, 4 nand gates 1022 or 8 nand gates 1022 may also be used, and is not limited herein. Meanwhile, the even number of nand gates 1022 are connected in series, and only the a1 input terminal of each nand gate 1022 is connected to the output terminal of the previous nand gate 1022 in the figure, in actual production, the other input terminal of each nor gate 1012 may be connected to the output terminal of the previous nor gate 1012.

The inverter 104, the first nand 1011 in the PMOS transistor master oscillator ring 101, and the second nand 1021 in the NMOS transistor master oscillator ring 102 control the entire detection circuit. When the control signal is at a high level, the inverter 104 sets the first input of the first nand-gate 1011 to a low level, and the fourth input of the second nand-gate 1021 to a high level. In this case, only the NMOS dominant oscillation ring 102 of the detection circuit is operated, and the PMOS dominant oscillation ring 101 is not operated. At this time, the detection circuit can detect the influence of the stress on the NMOS tube.

Similarly, when the control signal is at a low level, the inverter 104 sets the first input of the first nand-gate 1011 to a high level, and the fourth input of the second nand-gate 1021 is at a low level. In this case, only the PMOS transistor dominant oscillation ring 101 is operated in the detection circuit, and the NMOS transistor dominant oscillation ring 102 is not operated. At this time, the detection circuit can detect the influence of the stress on the PMOS tube.

In this embodiment, the number of the NMOS serially connected to the signal path in each nand gate of the even number of nand gates 1022 is greater than the number of the PMOS, fig. 3 is a schematic diagram of one nand gate 1022 of the even number of nand gates 1022 provided in this embodiment, as shown in fig. 3, the nand gate 1022 provided in this embodiment is composed of an NMOS transistor and a PMOS transistor, it can be understood that there are a plurality of nor gates in the digital cell bank, including different numbers of input pins and different numbers of N/P MOS transistors, where in this embodiment, only the 4-input nand gate 1022 shown in fig. 3 is used for illustration, and certainly, in practical applications, the nand gate 1022 may also be 2-input or 8-input. In this embodiment, except for one input for connecting to an adjacent nand gate, the other input of each nand gate in the even number of nand gates is connected to a high level.

Specifically, three input pins a2, A3, a4 of the nand gate 1022 shown in fig. 3 are connected to high level 1, 3 PMOS transistors whose gates are connected to a2, A3, a4 are in an off state, and 3 NMOS transistors whose gates are connected to a2, A3, a4 are in an on state.

When a1 inputs a low level 0, all NMOS transistors and all PMOS transistors in the nand gate 1022 shown in fig. 3 are turned on, and all PMOS transistors are turned off. When a1 inputs high level 1, the NMOS transistor with the grid connected with A1 is in a closed state, and the PMOS transistor with the grid connected with A1 is in an open state. At this time, in the nand gate 1022 shown in fig. 2, 3 NMOS transistors are in an open state, and 1 PMOS transistor is in an open state. Therefore, in both cases, the number of NMOS transistors in the nor gate 1012 in the open state is more than the number of PMOS transistors.

Therefore, in this embodiment, when the electrical characteristics of the NMOS transistor change due to stress, the electrical characteristics of the NMOS transistor reflected by the frequency signal output by the NMOS transistor main self-oscillation ring 102 change, obviously, the circuit for detecting the influence of stress on the electrical characteristics provided by this embodiment may determine the influence of stress on the NMOS transistor according to the frequency signal output by the NMOS transistor main self-oscillation ring 102, so as to improve the manufacturing process of the integrated circuit according to the influence of stress on the PMOS transistor, improve the manufacturing process accuracy of the integrated circuit, and reduce the influence of stress on the electrical characteristics of the NMOS transistor of the integrated circuit.

The PMOS master oscillator ring 101 and the NMOS master oscillator ring 102 provided in this embodiment are described in detail above, and the frequency reading module 103 provided in this embodiment is described below.

As shown in fig. 1, the frequency reading module 103 includes a frequency divider 1032, a register 1031 and a system clock 1033, wherein the frequency divider 1032 is connected to the output terminals of the PMOS self-oscillation ring 101 and the NMOS self-oscillation ring 102 through the multiplexer MUX105, and the frequency divider 1032 is further connected to the register 1031 and the system clock 1033, respectively, in this embodiment, the frequency divider 1032 is configured to reduce the frequency of the output frequency signals of the PMOS self-oscillation ring 101 and the NMOS self-oscillation ring 102, and the frequency divider 1032 outputs the frequency signals with reduced frequency, and the frequency signals are converted into digital signals, which are stored in the register 1031 array and can be read in real time by using the system clock 1033.

It should be noted that the MUX105 provided in this embodiment is used to select to provide the outputs of the PMOS master oscillator loop 101 and the NMOS master oscillator loop 102 to the frequency reading module. For example, when the control signal is high level 1, the high level 1 is input to the NMOS master oscillator ring 102, and simultaneously, the high level 1 is input to the MUX105, and the MUX105 can thus select to provide the output of the NMOS master oscillator ring 102 to the frequency reading module.

The circuit for detecting the influence of stress on the electrical characteristics provided by this embodiment may further include an inverter 104, when the control signal is a low level 0, the low level 0 passes through the inverter 104, the inverter 104 outputs a high level 1, the high level 1 output by the inverter 104 is input to the PMOS master oscillator loop 101, the low level 0 is input to the MUX105, and the MUX105 thus selects to provide the output of the PMOS master oscillator loop 101 to the frequency reading module.

In practical applications, the circuit for detecting the influence of the stress on the electrical characteristics can be placed at different positions of the semiconductor chip, so as to determine the distribution of the stress on the semiconductor chip according to the frequency signal read by the frequency reading module 103 when the circuit is at different positions of the semiconductor chip. For example, the circuit is placed in the center or around the semiconductor chip, and the distribution of stress in the semiconductor chip is determined according to the frequency signal read by the frequency reading module 103 at the center of the semiconductor chip and the frequency signal read around the semiconductor chip.

Of course, the present embodiment may also determine the influence of the packaging process on the electrical characteristics through a wafer (CP) test and a Functional Test (FT) test. For example, the frequency signal read by the frequency reading module 103 is obtained through a CP test, the frequency signal read by the frequency reading module 103 is obtained through an FT test, and the influence of the packaging process on the electrical characteristics of the device is obtained by comparing the frequency signal read by the frequency reading module 103 obtained through the CP test with the frequency signal read by the frequency reading module 103 obtained through the FT test. Note that the CP test is performed before the semiconductor is packaged, and the FT test is performed after the semiconductor is packaged.

In this embodiment, the influence of the stress of different package forms on the electrical characteristics of the device may also be obtained by comparing the frequency signals read by the frequency reading modules 103 of different package forms, or by comparing the frequency signals read by the frequency reading modules 103 at positions where the circuit is respectively placed right below the Bump and near the Bump, the influence of the stress of the package Bump on the electrical characteristics of the device is obtained, or in a scenario such as chip dropping, the influence of the stress on the electrical characteristics may also be analyzed by a difference between the frequency signals read by the frequency reading modules 103 before and after the chip dropping.

The circuit for detecting the influence of stress on the electrical characteristics provided in this embodiment may also be applied in a 3D Integrated Circuit (IC), for example, a 3D IC including a Through Silicon Via (TSV) or a Through Dielectric Via (TDV), to detect the influence of stress in the TSV or TDV on the electrical characteristics of the surrounding devices.

The circuit for detecting the influence of stress on the electrical characteristics provided by the embodiments of the present application is described above, and the sensor provided by the embodiments of the present application is described below.

An embodiment of the present application further provides a sensor, where the sensor includes the circuit for detecting an influence of stress on an electrical characteristic shown in fig. 1, where a function and a structure of the circuit for detecting an influence of stress on an electrical characteristic included in the sensor are similar to those described in the foregoing fig. 1, fig. 2, and fig. 3, and reference is specifically made to fig. 1, fig. 2, and fig. 3, and details are not repeated here.

An embodiment of the present application further provides a chip, where the chip includes the circuit for detecting an influence of stress on an electrical characteristic shown in fig. 1, where a function and a structure of the circuit for detecting an influence of stress on an electrical characteristic included in the chip are similar to those described in the foregoing fig. 1, fig. 2, and fig. 3, and reference is specifically made to fig. 1, fig. 2, and fig. 3, and details are not repeated here.

In the embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one logical division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.

The above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

A detection circuit, comprising:

the PMOS tube main self-oscillation ring, the NMOS tube main self-oscillation ring and the frequency reading module are arranged in the circuit board;

the number of PMOS tubes in a signal path of the PMOS tube main self-oscillation ring is larger than that of NMOS tubes;

the number of NMOS tubes in a signal path of the NMOS tube main self-oscillation ring is greater than that of PMOS tubes;

the frequency reading module is used for reading the frequency signal output by the PMOS tube main self-oscillation ring or the NMOS tube main self-oscillation ring.
The circuit of claim 1, wherein the PMOS transistor main self-oscillating ring comprises an even number of nor gates connected in series, the number of PMOS transistors connected in series on the signal path in each of the even number of nor gates being greater than the number of NMOS transistors; the NMOS tube main self-oscillation ring comprises even number of NAND gates which are connected in series, and the number of NMOS tubes which are connected in series on a signal path in each NAND gate in the even number of NAND gates is larger than that of PMOS tubes.
The circuit of claim 2, wherein the PMOS transistor master self-oscillating ring comprises a first nand gate, an output of the first nand gate being coupled to inputs of the even number of nor gates in the series, the first nand gate comprising a first input connected to the control signal and a second input connected to an output of the even number of nor gates in the series.
The circuit of claim 3, wherein each of the even number of NOR gates includes P inputs, P being an integer greater than or equal to 2;

a third input end of the P input ends is connected with an output end of the first nand gate, and other input ends of the P input ends except the third input end are connected with a low level, and the third input end is any one of the P input ends.
The circuit of claim 2, wherein the NMOS transistor-dominant oscillatory ring comprises a second nand gate, an output of the second nand gate being coupled to inputs of the even number of nand gates in the series, the second nand gate comprising a fourth input connected to the control signal and a fifth input connected to an output of the even number of nand gates in the series.
The circuit of claim 5, wherein each NAND gate of the even number of NAND gates includes L inputs, L being an integer greater than or equal to 2;

a sixth input end of the L input ends is connected to an output of the second nand gate, and other input ends of the L input ends except the sixth input end are connected to a high level, and the sixth input end is any one of the L input ends.
The circuit of any of claims 3 to 6, further comprising an inverter for inverting the control signal before coupling to the first input of the first NAND gate.
The circuit of any of claims 1 to 6, further comprising a Multiplexer (MUX) for selecting whether to provide the output of the PMOS master oscillator loop or the NMOS master oscillator loop to the frequency read block.
The circuit of claim 8, wherein the frequency reading module comprises a frequency divider, a register, and a system clock, the frequency divider being connected to the output terminals of the PMOS transistor-dominant self-oscillating ring and the NMOS transistor-dominant self-oscillating ring, the frequency divider being further connected to the register and the system clock, respectively.
A sensor, characterized in that it comprises a detection circuit according to any one of claims 1 to 9.