CN114124341A - Synchronization method suitable for high-bit-rate frequency modulation signal - Google Patents

Synchronization method suitable for high-bit-rate frequency modulation signal Download PDF

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CN114124341A
CN114124341A CN202210069398.9A CN202210069398A CN114124341A CN 114124341 A CN114124341 A CN 114124341A CN 202210069398 A CN202210069398 A CN 202210069398A CN 114124341 A CN114124341 A CN 114124341A
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interpolation
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CN114124341B (en
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潘云强
徐杰
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Beijing Rongwei Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W56/00—Synchronisation arrangements
    • H04W56/0055—Synchronisation arrangements determining timing error of reception due to propagation delay
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention provides a synchronization method suitable for a high-code-rate frequency modulation signal, which comprises the following steps: the input signal is subjected to signal resampling through an interpolation filter; performing multi-symbol detection (MSD) detection on the resampled signal to obtain an output signal; performing cross product frequency discrimination and Automatic Gain Control (AGC) on the resampled signals, respectively performing leading accumulation and lagging accumulation, then performing timing error calculation on the leading accumulated value and the lagging accumulated value to obtain a timing error, and sending the timing error to a loop filter to obtain a loop control error; the loop control error is sent to a numerical control oscillator, the numerical control oscillator generates interpolation time and interpolation phase, and the interpolation time and the interpolation phase are sent to an interpolation filter; the numerical control oscillator sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal which are used for resetting the leading accumulation module and the lagging accumulation module.

Description

Synchronization method suitable for high-bit-rate frequency modulation signal
Technical Field
The invention relates to the technical field of wireless communication, in particular to a synchronization method suitable for high-code-rate frequency modulation signals.
Background
In the field of missile and arrow telemetering, telemetering signals of a frequency modulation system have high reliability and good anti-interference capability, and are widely applied. The rate of the frequency modulation telemetry baseband which is mainstream in China at present is between 10Kbps and 20 Mbps. The development trend of remote measurement products in the future mainly develops towards the directions of strong environmental adaptability, high code rate, high-efficiency spectrum utilization rate, product miniaturization and the like so as to adapt to different transmitting tasks.
In a common fm signal synchronization scheme, an integration method is used in a symbol loop to reduce the speed of an oversampled signal to a symbol rate, and the signal-to-noise ratio of the signal is improved by integration. To achieve better performance, a larger number of integration points is required, and thus a higher sampling rate is required. Under the limiting conditions of hardware sampling rate and processing clock, the common frequency modulation signal synchronization scheme has limited applicable code rate and cannot be applicable to higher code rate.
In the prior art of frequency modulation signal synchronization, a patent 'PCM/FM signal early-late loop frequency synchronization method based on multi-symbol detection' discloses an early-late gate frequency synchronization method for fast capturing and high-precision tracking of large dynamic PCM/FM signal carrier frequency, the method adopts 2 MSD modules in a synchronization loop to realize high complexity, and meanwhile, an integral averaging method is adopted in the loop and is not suitable for high-code-rate frequency modulation signals. The patent 'a low complexity bit synchronization method for PCM/FM multi-symbol detection' discloses a bit synchronization method for saving 1 MSD, which firstly carries out MSD calculation and then adopts Gardner timing synchronization, thereby reducing the realization complexity and being suitable for high code rate frequency modulation signals. Although this method saves 1 MSD module, the MSD used in this method is placed before bit synchronization, timing errors cause MSD correlation loss, and thus this method has poor estimation accuracy.
Disclosure of Invention
The object of the present invention is to solve at least one of the technical drawbacks mentioned.
Therefore, the present invention is directed to a synchronization method for high-bit-rate frequency modulated signals, so as to solve the problems mentioned in the background art and overcome the disadvantages of the prior art.
In order to achieve the above object, an embodiment of the present invention provides a synchronization method for a high-rate fm signal, including:
step S1, the input signal is re-sampled by an interpolation filter; performing multi-symbol detection (MSD) detection on the resampled signal to obtain an output signal;
step S2, after cross product frequency discrimination and automatic gain control AGC are carried out on the resampled signals, respectively carrying out leading accumulation and lagging accumulation to obtain leading accumulated values and lagging accumulated values, then carrying out timing error calculation on the leading accumulated values and the lagging accumulated values to obtain timing errors, and sending the timing errors to a loop filter to obtain loop control errors;
step S3, sending the loop control error to a numerically controlled oscillator, generating an interpolation time and an interpolation phase by the numerically controlled oscillator, and sending the interpolation time and the interpolation phase to the interpolation filter for controlling the generation of the required resampling signal;
in step S4, the dco sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal for resetting the leading accumulation module and the lagging accumulation module.
Preferably, in any of the above schemes, the interpolation filter is a polyphase filter, and includes a plurality of filters, each of the filters having a set of filter coefficients obtained by polyphase decomposition.
Preferably, in any of the above solutions, in the step S2,
the output signal at the nth time is
Figure 459475DEST_PATH_IMAGE001
The accumulated reset signal is
Figure 12685DEST_PATH_IMAGE002
Then, the value is accumulated
Figure 491071DEST_PATH_IMAGE003
Is composed of
Figure 806646DEST_PATH_IMAGE004
According to the calculated advance accumulated value
Figure 79495DEST_PATH_IMAGE005
And lag accumulation value
Figure 510214DEST_PATH_IMAGE006
Calculating the timing error
Figure 526712DEST_PATH_IMAGE007
Is composed of
Figure 696793DEST_PATH_IMAGE008
The timing error passes through a loop filter to obtain a loop control error.
Preferably, in any of the above schemes, the loop filter uses a second order loop or a third order loop.
Preferably, in any of the above schemes, when the loop filter adopts a second order loop, the loop control error is
Figure 140544DEST_PATH_IMAGE009
Is composed of
Figure 589717DEST_PATH_IMAGE010
Wherein the coefficients
Figure 409906DEST_PATH_IMAGE011
Are second order loop parameters.
Preferably, in step S3, the method for generating an interpolation time and an interpolation phase by the digitally controlled oscillator includes:
Figure 700073DEST_PATH_IMAGE012
wherein the content of the first and second substances,
Figure 580304DEST_PATH_IMAGE013
is the accumulated value of the NCO,
Figure 188878DEST_PATH_IMAGE014
the amount of the carbon dioxide is the intermediate amount,
Figure 343916DEST_PATH_IMAGE015
for interpolating the time enable signal when
Figure 488589DEST_PATH_IMAGE016
The time is the interpolation time instant,
Figure 274143DEST_PATH_IMAGE017
in order to interpolate the phase of the phase,
Figure 104433DEST_PATH_IMAGE018
is NCO control word and the calculation method is
Figure 876211DEST_PATH_IMAGE019
；
Wherein the content of the first and second substances,
Figure 577189DEST_PATH_IMAGE020
in order to sample the signal with a frequency of,
Figure 533643DEST_PATH_IMAGE021
i is the number of filters for the signal bit rate.
In any of the above embodiments, preferably, in step S4, the advance bit clock and the retard bit clock are generated as the accumulation reset signal based on the interpolation time. The specific implementation method comprises the following steps: enabling loop counting of interpolation instants, i.e. count values
Figure 149432DEST_PATH_IMAGE022
Clock with alarm
Figure 348070DEST_PATH_IMAGE023
Is shown as
Figure 670598DEST_PATH_IMAGE024
Lagging clock
Figure 63534DEST_PATH_IMAGE025
Is shown as
Figure 665154DEST_PATH_IMAGE026
。
Compared with the prior art, the invention has the following beneficial effects:
1. the applicable symbol rate is high. According to the scheme of the invention, the maximum supported code rate is known to be
Figure 637789DEST_PATH_IMAGE027
The code rate supported by the conventional method is generally
Figure 345982DEST_PATH_IMAGE028
The following. Therefore, the invention is suitable for frequency modulation signals with higher code rate and is also suitable for frequency modulation signals with low code rate.
2. The synchronization precision is high. The invention resamples the input signal into the resample signal with fixed sampling multiple through the interpolation filter, and simultaneously ensures the stability of loop gain by combining with an AGC module; the loop is adopted to track the timing error, and NCO is adopted to adjust the interpolation time and the interpolation phase, so that the synchronization error is reduced; and the loop synchronization is performed firstly, and then the MSD detection is performed, so that the MSD detection performance is obviously improved. Therefore, the invention has extremely high synchronization precision.
3. The synchronization threshold is low. The invention adopts an interpolation filter to resample an input signal to obtain a resampled signal of 4 times of sampling times, and the resampled signal is processed by a synchronous loop to still have good synchronous signal at low signal-to-noise ratio and have low synchronous threshold.
4. The complexity is low. The invention only adopts 1 MSD module, and other modules (transversal filter, cross product frequency discrimination, AGC, loop filter) only consume more than 10 multipliers, and has the advantage of low realization complexity.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a flow chart of a synchronization method for high-rate fm signals according to an embodiment of the invention;
fig. 2 is a diagram of a synchronization method architecture for high-rate fm signals according to an embodiment of the invention;
fig. 3 is a schematic diagram of an interpolation filter according to an embodiment of the present invention.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.
The invention provides a synchronization method suitable for high-code-rate frequency modulation signals, which can solve the problems that the existing synchronization technology is not suitable for the high-code-rate frequency modulation signals or the synchronization precision is poor. The method is realized by interpolation filter, multi-symbol detection MSD detection, cross product frequency discrimination, automatic gain control AGC, leading accumulation, lagging accumulation, timing error calculation, loop filter, numerically controlled oscillator NCO, leading bit clock generation, lagging bit clock generation and the like.
As shown in fig. 1 and fig. 2, the synchronization method for high-rate frequency modulated signals according to the embodiment of the present invention includes the following steps:
step S1, the input signal is re-sampled by an interpolation filter; and MSD (multi-symbol detection) detection is performed on the resampled signal to obtain an output signal.
In particular, assume that the input signal sampling frequency is
Figure 909819DEST_PATH_IMAGE020
At a signal bit rate of
Figure 529894DEST_PATH_IMAGE021
. Firstly, an input signal is resampled by an interpolation filter to obtain a resampled signal, and the resampled signal is 4 times of an oversampled signal, namely the resampled signal has a sampling rate of
Figure 306220DEST_PATH_IMAGE029
。
In an embodiment of the present invention, the interpolation filter may be a polyphase filter, including a plurality of filters, each filter having a set of filter coefficients obtained by polyphase decomposition. With particular reference to FIG. 3, the interpolation filter employs a polyphase filter, including
Figure 400078DEST_PATH_IMAGE030
A filter, is
Figure 499531DEST_PATH_IMAGE031
Each filter contains a set of filter coefficients resulting from a polyphase decomposition.
Assuming that the order of the polyphase filter is M, the M +1 filter coefficients of the ith filter are M
Figure 46050DEST_PATH_IMAGE032
. The interpolation filter first of all is based on the interpolation phase
Figure 734389DEST_PATH_IMAGE033
Selecting
Figure 384551DEST_PATH_IMAGE034
And the group of filter coefficients are loaded into the transverse filter, and filtering processing is carried out on the input signal at the interpolation moment to obtain a resampled signal.
Suppose that the input signal at the nth time is
Figure 290190DEST_PATH_IMAGE035
Then resampling the signal
Figure 120743DEST_PATH_IMAGE036
Is shown as
Figure 35609DEST_PATH_IMAGE037
（1）
Output signal calculation process: the resampled signal is subjected to MSD detection and 4-point matched filtering to obtain an output signal with the rate of
Figure 838480DEST_PATH_IMAGE021
。
Step S2, specifically, while step S1 is executed, cross product frequency discrimination and AGC (automatic Gain Control) are performed on the resampled signal, then leading accumulation and lagging accumulation are performed respectively to obtain a leading accumulated value and a lagging accumulated value, timing error calculation is performed on the leading accumulated value and the lagging accumulated value to obtain a timing error, and the timing error is sent to a loop filter to obtain a loop Control error.
Specifically, in the synchronization loop, the resampled signal is subjected to difference product frequency discrimination, the frequency modulated signal is converted into a PCM signal, and the power level of the PCM signal is normalized through an AGC module.
The AGC processed signals are accumulated, including early accumulation and late accumulation. The two accumulation processing modes are the same, when the accumulation reset signal is equal to 1, the accumulation result is cleared, otherwise, the accumulation is continued. The calculation process is as follows: suppose that the output signal of the AGC module at the nth time is
Figure 711758DEST_PATH_IMAGE001
The accumulated reset signal is
Figure 465826DEST_PATH_IMAGE002
Then, the value is accumulated
Figure 449962DEST_PATH_IMAGE038
Is composed of
Figure 107340DEST_PATH_IMAGE004
（2）
According to the calculated advance accumulated value
Figure 885940DEST_PATH_IMAGE005
And lag accumulation value
Figure 691085DEST_PATH_IMAGE006
Calculating the timing error
Figure 915130DEST_PATH_IMAGE007
Is composed of
Figure 489331DEST_PATH_IMAGE008
（3）
The timing error passes through a loop filter to obtain a loop control error.
In embodiments of the present invention, the loop filter employs a second order loop or a third order loop.
Taking the second order loop as an example, the loop control error
Figure 642095DEST_PATH_IMAGE039
Is composed of
Figure 403378DEST_PATH_IMAGE040
（4）
Wherein the coefficients
Figure 994896DEST_PATH_IMAGE011
Are second order loop parameters.
Step S3, sending the loop control error to an NCO (digital Oscillator), generating an interpolation time and an interpolation phase by the digital Oscillator, and sending the interpolation time and the interpolation phase to an interpolation filter for controlling to generate the required resampling signal.
In this step, the numerically controlled oscillator generates an interpolation time and an interpolation phase according to the loop control error, and includes the following steps:
Figure 361286DEST_PATH_IMAGE041
（5）
wherein the content of the first and second substances,
Figure 245803DEST_PATH_IMAGE013
is the accumulated value of the NCO,
Figure 963224DEST_PATH_IMAGE014
the amount of the carbon dioxide is the intermediate amount,
Figure 92854DEST_PATH_IMAGE015
for interpolating the time enable signal when
Figure 313751DEST_PATH_IMAGE042
The time is the interpolation time instant,
Figure 136213DEST_PATH_IMAGE017
in order to interpolate the phase of the phase,
Figure 872088DEST_PATH_IMAGE018
is NCO control word and the calculation method is
Figure 976048DEST_PATH_IMAGE019
（6）
In step S4, the dco sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal for resetting the leading accumulation module and the lagging accumulation module.
Specifically, an advance bit clock and a retard bit clock are generated as the accumulation reset signal based on the interpolation timing. The specific implementation method comprises the following steps: enabling loop counting of interpolation instants, i.e. count values
Figure 379348DEST_PATH_IMAGE022
Clock with alarm
Figure 779236DEST_PATH_IMAGE043
Is shown as
Figure 205669DEST_PATH_IMAGE024
Lagging clock
Figure 441216DEST_PATH_IMAGE044
Is shown as
Figure 636705DEST_PATH_IMAGE045
。
The invention provides a synchronization method suitable for high-code-rate frequency modulation signals, which can be used for the synchronization of the high-code-rate frequency modulation signals and the synchronization of the low-code-rate frequency modulation signals, and has the advantages of low complexity, high synchronization precision, low synchronization threshold and good synchronization performance.
Compared with the prior art, the invention has the following beneficial effects:
1. the applicable symbol rate is high. According to the scheme of the invention, the maximum supported code rate is known to be
Figure 535391DEST_PATH_IMAGE027
The code rate supported by the conventional method is generally
Figure 449121DEST_PATH_IMAGE028
The following. Therefore, the invention is suitable for frequency modulation signals with higher code rate and is also suitable for frequency modulation signals with low code rate.
2. The synchronization precision is high. The invention resamples the input signal into the resample signal with fixed sampling multiple through the interpolation filter, and simultaneously ensures the stability of loop gain by combining with an AGC module; the loop is adopted to track the timing error, and NCO is adopted to adjust the interpolation time and the interpolation phase, so that the synchronization error is reduced; and the loop synchronization is performed firstly, and then the MSD detection is performed, so that the MSD detection performance is obviously improved. Therefore, the invention has extremely high synchronization precision.
3. The synchronization threshold is low. The invention adopts an interpolation filter to resample an input signal to obtain a resampled signal of 4 times of sampling times, and the resampled signal is processed by a synchronous loop to still have good synchronous signal at low signal-to-noise ratio and have low synchronous threshold.
4. The complexity is low. The invention only adopts 1 MSD module, and other modules (transversal filter, cross product frequency discrimination, AGC, loop filter) only consume more than 10 multipliers, and has the advantage of low realization complexity.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It will be understood by those skilled in the art that the present invention includes any combination of the summary and detailed description of the invention described above and those illustrated in the accompanying drawings, which is not intended to be limited to the details and which, for the sake of brevity of this description, does not describe every aspect which may be formed by such combination. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (7)

1. A synchronization method suitable for high-bit-rate frequency modulation signals is characterized by comprising the following steps:
step S1, the input signal is re-sampled by an interpolation filter; performing multi-symbol detection (MSD) detection on the resampled signal to obtain an output signal;
step S2, after cross product frequency discrimination and automatic gain control AGC are carried out on the resampled signals, respectively carrying out leading accumulation and lagging accumulation to obtain leading accumulated values and lagging accumulated values, then carrying out timing error calculation on the leading accumulated values and the lagging accumulated values to obtain timing errors, and sending the timing errors to a loop filter to obtain loop control errors;
step S3, sending the loop control error to a numerically controlled oscillator, generating an interpolation time and an interpolation phase by the numerically controlled oscillator, and sending the interpolation time and the interpolation phase to the interpolation filter for controlling the generation of the required resampling signal;
in step S4, the dco sends the generated interpolation time to the leading bit clock generation module and the lagging bit clock generation module to generate a leading accumulation reset signal and a lagging accumulation reset signal for resetting the leading accumulation module and the lagging accumulation module.
2. A method of synchronizing a frequency modulated signal at a high rate as defined in claim 1, wherein the interpolation filter is a polyphase filter comprising a plurality of filters, each of the filters having a set of filter coefficients derived from a polyphase decomposition.
3. The method for synchronizing high rate FM signals as claimed in claim 1, wherein in said step S2,
the output signal at the nth time is
Figure DEST_PATH_IMAGE001
Cumulative complexBit signal is
Figure 112351DEST_PATH_IMAGE002
Then, the value is accumulated
Figure DEST_PATH_IMAGE003
Is composed of
Figure 170437DEST_PATH_IMAGE004
According to the calculated advance accumulated value
Figure DEST_PATH_IMAGE005
And lag accumulation value
Figure 120813DEST_PATH_IMAGE006
Calculating the timing error
Figure DEST_PATH_IMAGE007
Is composed of
Figure 922547DEST_PATH_IMAGE008
The timing error passes through a loop filter to obtain a loop control error.
4. A method of synchronizing a frequency modulated signal having a high code rate as defined in claim 3, wherein the loop filter uses a second order loop or a third order loop.
5. A method of synchronizing a frequency modulated signal having a high code rate as claimed in claim 4, characterized in that the loop control error is determined when the loop filter uses a second order loop
Figure DEST_PATH_IMAGE009
Is composed of
Figure 877864DEST_PATH_IMAGE010
Wherein the coefficients
Figure DEST_PATH_IMAGE011
Are second order loop parameters.
6. The method for synchronizing a high rate fm signal according to claim 1, wherein in step S3, the interpolation time and the interpolation phase are generated by the digitally controlled oscillator, comprising the steps of:
Figure 870966DEST_PATH_IMAGE012
wherein the content of the first and second substances,
Figure DEST_PATH_IMAGE013
is the accumulated value of the NCO,
Figure 278945DEST_PATH_IMAGE014
the amount of the carbon dioxide is the intermediate amount,
Figure DEST_PATH_IMAGE015
for interpolating the time enable signal when
Figure 382905DEST_PATH_IMAGE016
The time is the interpolation time instant,
Figure DEST_PATH_IMAGE017
in order to interpolate the phase of the phase,
Figure 989466DEST_PATH_IMAGE018
is NCO control word and the calculation method is
Figure DEST_PATH_IMAGE019
；
Wherein the content of the first and second substances,
Figure 654934DEST_PATH_IMAGE020
in order to sample the signal with a frequency of,
Figure DEST_PATH_IMAGE021
i is the number of filters for the signal bit rate.
7. A method for synchronizing a high rate fm signal as claimed in claim 1, wherein in step S4, the leading bit clock and the lagging bit clock are generated as the accumulated reset signal according to the interpolation time;
the specific implementation method comprises the following steps: enabling loop counting of interpolation instants, i.e. count values
Figure 314323DEST_PATH_IMAGE022
Clock with alarm
Figure DEST_PATH_IMAGE023
Is shown as
Figure 457860DEST_PATH_IMAGE024
Lagging clock
Figure DEST_PATH_IMAGE025
Is shown as
Figure 591032DEST_PATH_IMAGE026
。
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115051782A (en) * 2022-08-16 2022-09-13 北京航空航天大学 Timing synchronization method of continuous phase modulation system

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008078545A1 (en) * 2006-12-27 2008-07-03 Nec Corporation Information reproducing apparatus
CN101841327A (en) * 2010-03-05 2010-09-22 中兴通讯股份有限公司 Signal processing system and method
CN105187348A (en) * 2015-05-31 2015-12-23 中国电子科技集团公司第十研究所 Any-rate CPFSK (Continuous Phase Frequency Shift Key) signal timing synchronization method
CN105388500A (en) * 2015-10-18 2016-03-09 中国电子科技集团公司第十研究所 Method for improving continuous phrase frequency shift key (CPFSK) signal carrier tracking precision
CN106998236A (en) * 2017-02-07 2017-08-01 中国人民解放军国防科学技术大学 A kind of feedback-type symbol timing synchronizing apparatus and method based on filtering interpolation
CN111212007A (en) * 2020-04-20 2020-05-29 成都新动力软件有限公司 Universal 600Mbps intermediate-speed demodulator implementation method and modem
CN111245544A (en) * 2020-01-08 2020-06-05 西安电子科技大学 Timing synchronization improvement method for symbol rate deviation in non-cooperative communication system
WO2021138395A1 (en) * 2019-12-31 2021-07-08 Hughes Network Systems, Llc Superior timing synchronization using high-order tracking loops
CN113708916A (en) * 2021-07-13 2021-11-26 中国人民解放军战略支援部队航天工程大学 PCM/FM telemetering signal parallel multi-symbol detection method based on GPU

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008078545A1 (en) * 2006-12-27 2008-07-03 Nec Corporation Information reproducing apparatus
CN101841327A (en) * 2010-03-05 2010-09-22 中兴通讯股份有限公司 Signal processing system and method
CN105187348A (en) * 2015-05-31 2015-12-23 中国电子科技集团公司第十研究所 Any-rate CPFSK (Continuous Phase Frequency Shift Key) signal timing synchronization method
CN105388500A (en) * 2015-10-18 2016-03-09 中国电子科技集团公司第十研究所 Method for improving continuous phrase frequency shift key (CPFSK) signal carrier tracking precision
CN106998236A (en) * 2017-02-07 2017-08-01 中国人民解放军国防科学技术大学 A kind of feedback-type symbol timing synchronizing apparatus and method based on filtering interpolation
WO2021138395A1 (en) * 2019-12-31 2021-07-08 Hughes Network Systems, Llc Superior timing synchronization using high-order tracking loops
CN111245544A (en) * 2020-01-08 2020-06-05 西安电子科技大学 Timing synchronization improvement method for symbol rate deviation in non-cooperative communication system
CN111212007A (en) * 2020-04-20 2020-05-29 成都新动力软件有限公司 Universal 600Mbps intermediate-speed demodulator implementation method and modem
CN113708916A (en) * 2021-07-13 2021-11-26 中国人民解放军战略支援部队航天工程大学 PCM/FM telemetering signal parallel multi-symbol detection method based on GPU

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115051782A (en) * 2022-08-16 2022-09-13 北京航空航天大学 Timing synchronization method of continuous phase modulation system

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