CN114124109A - Parity check circuit and method - Google Patents
Parity check circuit and method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
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Abstract
The invention discloses a parity check circuit and a method. The parity check circuit comprises a state setting module, a first operation module, a shift module, a second operation module and a third operation module; a first input end of the first operation module is accessed with a data signal; the state setting module is used for outputting a state signal to the first operation module, and the first operation module is used for carrying out logic operation on the data signal and the first signal output by the shift module, carrying out logic operation on the state signal and the first signal and outputting a second signal; the shifting module is used for shifting the second signal to output a first signal; the second operation module is used for carrying out logic operation on the first signal and the control signal and outputting a third signal; and the third operation module is used for carrying out logic operation on the third signal and the second signal and outputting a data signal and a parity check bit. The parity check circuit of the invention can output original data signals and parity check bits, and does not need a microcontroller, thereby being beneficial to reducing the cost.
Description
Technical Field
The embodiment of the invention relates to the technical field of data transmission, in particular to a parity check circuit and a parity check method.
Background
In data communication, during the process of transmitting data from a transmitting end to a receiving end, external interference may be inevitably caused, so that it is necessary for the receiving end to judge whether the received data is the data transmitted by the transmitting end during the communication process, especially during the wireless communication process.
In this regard, it is a common practice that a transmitting end transmits a check bit, such as a parity bit, related to data information after transmitting the data information, and a receiving end determines whether the received check bit and the received data have the same correlation relationship after receiving the data information and the check bit, thereby determining whether the received data is transmitted by the transmitting end.
However, the existing parity check circuit needs to implement a parity check algorithm through a microcontroller, which is relatively high in cost, and the existing parity check circuit can only output check bits.
Disclosure of Invention
The invention provides a parity check circuit and a method thereof, which can output data signals and parity check bits without a microcontroller and is beneficial to reducing the cost.
In a first aspect, an embodiment of the present invention provides a parity check circuit, where the parity check circuit includes: the device comprises a state setting module, a data module, a first operation module, a shift module, a second operation module and a third operation module;
a first input end of the first operation module is accessed with a data signal;
the output end of the state setting module is electrically connected with the first input end of a first operation module, the second input end of the first operation module is electrically connected with the output end of the shift module, the output end of the first operation module is electrically connected with the input end of the shift module, the state setting module is used for outputting a state signal to the first operation module after the data signal is sent, and the first operation module is used for performing logic operation on the data signal and the first signal output by the shift module, performing logic operation on the state signal and the first signal, and outputting a second signal; the shift module is used for shifting the second signal to output a first signal;
a first input end of the second operation module is electrically connected with an output end of the shift module, a second input end of the second operation module is connected with a control signal, and the second operation module is used for performing logic operation on the first signal and the control signal and outputting a third signal;
the first input end of the third operation module is electrically connected with the output end of the second operation module, the second input end of the third operation module is electrically connected with the output end of the first operation module, and the third operation module is used for performing logic operation on the third signal and the second signal and outputting the data signal and the parity check bit.
Optionally, the parity check circuit further comprises: a clock module;
the clock module is electrically connected with a clock end of the shift module, the clock module is used for outputting a clock signal, and the shift module is used for responding to the clock signal of the clock module to output the first signal.
Optionally, the parity check circuit further comprises: a control module;
the control module is electrically connected with a second input end of the second operation module and is used for outputting the control signal.
Optionally, the first operation module includes a first exclusive or operation unit;
the first input end of the first exclusive-or operation unit is the first input end of the first operation module, the second input end of the first exclusive-or operation unit is the second input end of the first operation module, the output end of the first exclusive-or operation unit is the output end of the first operation module, and the first exclusive-or operation unit is used for performing logical exclusive-or operation on the data signal and the first signal output by the shift module, performing logical exclusive-or operation on the state signal and the first signal, and outputting a second signal.
Optionally, the second operation module includes a logical and operation unit;
the first input end of the logical and operation unit is the first input end of the second operation module, the second input end of the logical and operation unit is the second input end of the second operation module, the output end of the logical and operation unit is the output end of the second operation module, and the logical and operation unit is used for performing logical and operation on the first signal and the control signal and outputting a third signal.
Optionally, the third operation module includes a second exclusive or operation unit;
the first input end of the second exclusive-or operation unit is the first input end of the third operation module, the second input end of the second exclusive-or operation unit is the second input end of the third operation module, the output end of the second exclusive-or operation unit is the output end of the third operation module, and the second exclusive-or operation unit performs logic operation on the third signal and the second signal and outputs the data signal and the parity bit.
Optionally, the shift module comprises a shift register;
the input end of the shift register is the input end of the shift module, the output end of the shift register is the output end of the shift module, and the shift register is used for outputting the first signal according to the second signal.
Optionally, the shift register comprises a flip-flop.
Optionally, the parity check circuit further comprises a resistor;
the output end of the state setting module is electrically connected with the first input end of the first operation module through the resistor.
In a second aspect, an embodiment of the present invention further provides a parity checking method, where the parity checking method includes:
the first operation module receives a data signal, and the state setting module sends a state signal to the first operation module;
the first operation module performs logic operation on the data signal and a first signal output by the shift module, performs logic operation on the state signal and the first signal, and outputs a second signal;
the shift module shifts the second signal to output a first signal;
the second operation module performs logic operation on the first signal and the control signal and outputs a third signal;
the third operation module performs logic operation on the third signal and the second signal and outputs the data signal and the parity bit.
The parity check circuit comprises a state setting module, a first operation module, a shift module, a second operation module and a third operation module, wherein an external data module can send a data signal, the first operation module performs logic operation on the data signal and a first signal output by the shift module according to the data signal, the result of the logic operation is used as a second signal, and after the first operation module outputs the second signal, the shift module can output the first signal according to the second signal. The second operation module performs logic operation on the first signal and the control signal, outputs a result of the logic operation as a third signal, and performs logic operation on the third signal and the second signal and outputs a data signal. After the data signal is sent, the state setting module outputs a state signal to the first operation module, and the first operation module performs logic operation on the state signal and the first signal and outputs a second signal; the shifting module shifts the second signal to output a first signal; the second operation module performs logic operation on the first signal and the control signal and outputs a third signal; the third operation module performs logic operation on the third signal and the second signal and outputs a parity bit, wherein the parity bit represents whether the number of 1 in the data signal is odd or even, so that whether the received data signal is accurate can be judged according to the parity bit, the data signal and the parity bit can be output, the parity check can be realized only by three operation modules and one shift module, a microcontroller is not required to perform algorithm processing, and the effect of reducing the cost is achieved. The invention solves the problems that the existing parity check circuit needs to realize the parity check algorithm through a microcontroller, the cost is higher, and the existing parity check circuit can only output the check bit, realizes that the parity check circuit can output the data signal and the parity check bit, does not need the microcontroller, and achieves the effect of reducing the cost.
Drawings
Fig. 1 is a schematic structural diagram of a parity check circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a parity check circuit according to another embodiment of the present invention;
FIG. 3 is a timing diagram of a parity check circuit according to an embodiment of the present invention;
FIG. 4 is a timing diagram of a parity check circuit according to another embodiment of the present invention;
FIG. 5 is a timing diagram of a parity check circuit according to another embodiment of the present invention;
FIG. 6 is a timing diagram of a parity check circuit according to another embodiment of the present invention;
fig. 7 is a flowchart of a parity checking method according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a parity check circuit according to an embodiment of the present invention, and referring to fig. 1, the parity check circuit includes: a state setting module 110, a first operation module 130, a shift module 140, a second operation module 150 and a third operation module 160; a first input end of the first arithmetic module 130 is accessed to the Data signal Data; the output end of the state setting module 110 is electrically connected to the first input end of the first operation module 130, the second input end of the first operation module 130 is electrically connected to the output end of the shift module 140, the output end of the first operation module 130 is electrically connected to the input end of the shift module 140, the state setting module 110 is configured to output a state signal a to the first operation module 130 after Data signal Data transmission is completed, the first operation module 130 is configured to perform logical operation on the Data signal and a first signal B1 output by the shift module 140, perform logical operation on the state signal a and a first signal B1, and output a second signal B2; the shift module 140 is configured to shift the second signal to output a first signal B1; a first input end of the second operation module 150 is electrically connected to an output end of the shift module 140, a second input end of the second operation module 150 is connected to the control signal, and the second operation module 150 is configured to perform a logic operation on the first signal B1 and the control signal C and output a third signal B3; the first input terminal of the third operation module 160 is electrically connected to the output terminal of the second operation module 150, the second input terminal of the third operation module 160 is electrically connected to the output terminal of the first operation module 130, and the third operation module 160 is configured to perform logic operation on the third signal B3 and the second signal B2, and output a Data signal Data and a parity E.
The external Data module may transmit the Data signal Data, and the first operation module 130 performs a logic operation on the Data signal Data and the first signal B1 output by the shift module 140, and uses the result of the logic operation as the second signal B2, where the first signal B1 is output by the shift module 140 according to the second signal B2 output by the first operation module 130, when the first operation module 130 does not yet output the second signal B2, the first signal B1 output by the shift module 140 may default to 0, and after the first operation module 130 outputs the second signal B2, the shift module 140 may output the first signal B1 according to the second signal B2, so as to be an input signal when the first operation module 130 performs the next operation. The second operation module 150 performs a logic operation on the first signal B1 and the control signal C, and outputs the result of the logic operation as a third signal B3, and the third operation module 160 performs a logic operation on the third signal B3 and the second signal B2, and outputs the Data signal Data.
After the Data signal Data is sent, the output end of the external Data module is in a high impedance state, the state setting module 110 can output a state signal a to the first operation module 130, where the state signal a may be a high level signal 1 or a low level signal 0, and the first operation module 130 performs a logic operation on the state signal a and the first signal B1 and outputs a second signal B2; the shift module 140 shifts the second signal B2 to output the first signal B1; the second operation module 150 performs logic operation on the first signal B1 and the control signal C, and outputs a third signal B3; the third operation module 160 performs a logical operation on the third signal B3 and the second signal B2, and outputs a parity E, which indicates whether the number of 1 in the Data signal Data is odd or even, for example, 0 or 1, 0 indicates that the number of 1 in the Data signal Data is even, and 1 indicates that the number of 1 in the Data signal Data is odd; alternatively, 0 indicates that the number of 1's in the Data signal Data is odd, and 1 indicates that the number of 1's in the Data signal Data is even, so that whether the received Data signal Data is accurate can be determined based on the parity E.
Illustratively, the Data signal Data is, for example, 8 bits, and the Data signal Data is serial Data, the operation of the parity check circuit is: (1) after the first operation module 130 receives the first bit D1 of the Data signal Data, the first bit D1 of the Data signal Data and the first bit B11 of the first signal B1 are logically operated, at this time, the first bit B11 of the first signal B1 defaults to 0, the first bit B21 of the second signal B2 is obtained after logical operation is performed, the shift module 140 outputs the second bit B12 of the first signal B1 according to the first bit B21 of the second signal B2 to be used as an input signal when the first operation module 130 performs next operation, the second operation module 150 performs logical operation on the first bit B11 of the first signal B1 and the first bit C1 of the control signal C to obtain the first bit B31 of the third signal B3, and the third operation module 160 performs logical operation on the first bit B31 of the third signal B3 and the first bit B21 of the second signal B2 to output the first bit D1 of the Data signal B3; (2) the first operation module 130 performs a logic operation according to the second bit D2 of the Data signal Data and the second bit B12 of the first signal B1, that is, the first operation module 130 performs a logic operation according to the second bit D2 of the Data signal Data and the second bit B12 of the first signal B1 to obtain the second bit B22 of the second signal B2, the shift module 140 outputs the third bit B13 of the first signal B1 according to the second bit B22 of the second signal B2, the second operation module 150 performs a logic operation on the second bit B12 of the first signal B1 and the second bit C2 of the control signal C to obtain the second bit B32 of the third signal B3, and the third operation module 160 performs a logic operation on the second bit B32 of the third signal B3 and the second bit B22 of the second signal B2 to output the second bit D2 of the Data signal Data; (3) in analogy, until the third operation module 160 performs a logic operation on the eighth bit B38 of the third signal B3 and the eighth bit D28 of the second signal B2 to output the eighth bit D8 of the Data signal Data, the Data signal Data transmission is completed; (4) after the Data signal Data is sent, the state setting module 110 may output the state signal a to the first operation module 130, the first operation module 130 operates the state signal a and the ninth bit B19 of the first signal B1 to obtain the ninth bit B29 of the second signal B2, the second operation module 150 performs a logic operation on the ninth bit B19 of the first signal B1 and the ninth bit C9 of the control signal C to obtain the ninth bit B39 of the third signal B3, the third operation module 160 performs a logic operation on the ninth bit B39 of the third signal B3 and the ninth bit B29 of the second signal B2 to obtain the parity bit E, so as to output the Data signal Data and the parity bit E, and the parity check may be implemented only by using three operation modules and one shift module without using a microcontroller to perform an arithmetic process, thereby achieving an effect of reducing cost.
According to the technical scheme, the parity check circuit comprises a state setting module, a first operation module, a shift module, a second operation module and a third operation module, an external data module can send data signals, the first operation module performs logic operation on the data signals and first signals output by the shift module, the result of the logic operation is used as second signals, and after the first operation module outputs the second signals, the shift module can output the first signals according to the second signals to be used as input signals of next operation of the first operation module. The second operation module performs logic operation on the first signal and the control signal, outputs a result of the logic operation as a third signal, and performs logic operation on the third signal and the second signal and outputs a data signal. After the data signal is sent, the state setting module outputs a state signal to the first operation module, and the first operation module performs logic operation on the state signal and the first signal and outputs a second signal; the shifting module shifts the second signal to output a first signal; the second operation module performs logic operation on the first signal and the control signal and outputs a third signal; the third operation module performs logic operation on the third signal and the second signal and outputs a parity bit, wherein the parity bit represents whether the number of 1 in the data signal is odd or even, so that whether the received data signal is accurate can be judged according to the parity bit, the data signal and the parity bit can be output, the parity check can be realized only by three operation modules and one shift module, a microcontroller is not required to perform algorithm processing, and the effect of reducing the cost is achieved. The technical scheme of the embodiment solves the problems that the existing parity check circuit needs to realize a parity check algorithm through a microcontroller, the cost is high, and the existing parity check circuit can only output check bits, so that the parity check circuit can output data signals and parity check bits without the microcontroller, and the effect of reducing the cost is achieved.
On the basis of the foregoing embodiment, fig. 2 is a schematic structural diagram of another parity check circuit provided in an embodiment of the present invention, and optionally, referring to fig. 2, the parity check circuit further includes a clock module 170; the clock module 170 is electrically connected to a clock terminal of the shift module 140, the clock module 170 is configured to output a clock signal CLK, and the shift module 140 is configured to output a first signal B1 in response to the clock signal CLK of the clock module 170.
Specifically, the clock module 170 may generate the clock signal CLK, and the shift module 140 may operate in response to the clock signal of the clock module 170 to output the first signal B1. Where the clock signal CLK includes a rising edge and a falling edge, the shift module 140 acts, for example, on the rising edge of the clock signal CLK to output the first signal B1.
Optionally, referring to fig. 2, the parity check circuit further comprises a control module 180; the control module 180 is electrically connected to a second input terminal of the second operation module 150, and the control module 180 is configured to output a control signal C.
Specifically, the control module 180 may output the control signal C, so that the second operation module 150 may perform a logical operation on the first signal B1 and the control signal C output by the shift module 140, thereby obtaining a third signal B3. When the external Data module transmits the Data signal Data, the control signal C is, for example, a high level signal 1, and when the state setting module 110 transmits the state signal a, the control signal C is, for example, a low level signal 0.
Alternatively, referring to fig. 2, the first operation module 130 includes a first exclusive or operation unit 131; the first input end of the first xor operation unit 131 is the first input end of the first operation module 130, the second input end of the first xor operation unit 131 is the second input end of the first operation module 130, the output end of the first xor operation unit 131 is the output end of the first operation module 130, and the first xor operation unit 131 is configured to perform a logical xor operation on the Data signal Data and the first signal B1 output by the shift module 140, perform a logical xor operation on the state signal a and the first signal B1, and output a second signal B2.
Specifically, the first xor operation unit 131 may perform a logical xor operation on the Data signal Data and the first signal B1 output by the shift module 140, where the logical xor operation means that if two input values are not the same, the xor result is 1, and if the two input values are the same, the xor result is 0. For example, if the first bit D1 of the Data signal Data is 0, the first bit B11 of the first signal B1 is 0, and the first bit B21 of the second signal B2 output by the first exclusive-or unit 131 is 0; for example, if the first bit D1 of the Data signal Data is 1, the first bit B11 of the first signal B1 is 0, and the first bit B21 of the second signal B2 output by the first exclusive-or unit 131 is 1. And the first exclusive or operation unit 131 may also perform a logical exclusive or operation on the state signal a and the first signal B1, thereby outputting a second signal B2.
Alternatively, referring to fig. 2, the second operation module 150 includes a logical and operation unit 151; the first input terminal of the and logic unit 151 is the first input terminal of the second operation module 150, the second input terminal of the and logic unit 151 is the second input terminal of the second operation module 150, the output terminal of the and logic unit 151 is the output terminal of the second operation module 150, and the and logic unit 151 is configured to perform a logical and operation on the first signal B1 and the control signal C, and output a third signal B3.
Specifically, the and logic unit 151 may perform an and operation on the first signal B1 and the control signal C, where the and operation means that if two input values are different, the result is 0, and if the two input values are the same, the result is 1. For example, if the first bit B11 of the first signal B1 is 0 and the first bit C1 of the control signal C is 1, the first bit B31 of the third signal B3 outputted by the and unit 151 is 0; for example, if the second bit B12 of the first signal B1 is 1 and the second bit C2 of the control signal C is 1, the second bit B32 of the third signal B3 output by the and logic unit 151 is 1, so that the third signal B3 can be output.
Alternatively, referring to fig. 2, the third operation module 160 includes a second exclusive or operation unit 161; the first input terminal of the second exclusive-or operation unit 161 is the first input terminal of the third operation module 160, the second input terminal of the second exclusive-or operation unit 161 is the second input terminal of the third operation module 160, the output terminal of the second exclusive-or operation unit 161 is the output terminal of the third operation module 160, and the second exclusive-or operation unit 161 performs a logical operation on the third signal B3 and the second signal B2 and outputs the Data signal Data and the parity E.
Specifically, the second exclusive-or operation unit 161 may perform an exclusive-or operation on the third signal B3 and the second signal B2, for example, when the first bit B31 of the third signal B3 is 0, and the first bit B21 of the second signal B2 is 1, then the first bit D1 of the Data signal Data output by the second exclusive-or operation unit 161 is 1; for example, when the ninth bit B39 of the third signal B3 is 0 and the ninth bit B29 of the second signal B2 is 0, the second exclusive-or operation unit 161 outputs the parity bit E as 0.
Alternatively, referring to fig. 2, the shift module 140 includes a shift register 141; the input terminal of the shift register 141 is the input terminal of the shift module 140, the output terminal of the shift register 141 is the output terminal of the shift module 140, and the shift register 141 is configured to output the first signal B1 according to the second signal B2.
Specifically, the data in the shift register 141 may be shifted to the right or to the left bit by bit sequentially under the clock pulse, the data may be input in parallel, output in parallel, input in series, output in parallel, input in parallel, output in series, input in series, and output in parallel, preferably, the shift register 141 may shift the second signal B2 output by the first operation module 130 by one bit to the right, for example, when the second signal B2 is 00100100100110, the first signal B1 output by the shift register 141 is 00010011.
Alternatively, referring to fig. 2, the shift register 141 includes a flip-flop 1411.
Specifically, the shift register 141 includes a flip-flop 1411, and the flip-flop 1411 is, for example, a D flip-flop, i.e., the flip-flop 1411 outputs the same value as the input value, i.e., when the first bit B21 of the second signal B2 output by the first operation module 130 is 0, the second bit of the first signal B1 output by the shift register 141 is also 0. It should be noted that, when the shift register 141 outputs the first bit B11 of the first signal B1, the first operation module 130 does not yet output the second signal B2, so the first bit B11 of the first signal B1 output by the shift register 141 is 0 by default.
Optionally, referring to fig. 2, the parity check circuit further includes a resistor R1; the output terminal of the state setting module 110 is electrically connected to the first input terminal of the first operation module 130 through a resistor R1.
Specifically, the resistor R1 may be a pull-up resistor or a pull-down resistor, the resistor R1 is a pull-up resistor when the state signal a output by the state setting module 110 is a high level signal 1, and the resistor R1 is a pull-down resistor when the state signal a output by the state setting module 110 is a low level signal 0, so that the state signal a can be output to the first operation module 130. When the external Data module finishes sending the Data signal Data, the first input end of the first operation module 130 is set to be in a high impedance state, at this time, the state setting module 1210 may output the state signal a to the first operation module 130 through the resistor R1, the representation of the parity bit E is related to the value of the state signal a, table 1 is the relationship between the parity bit and the numbers of 1 in the state signal and the Data signal, referring to table 1, when the state signal a is 0, the parity bit E is 1, which means that the number of 1 in the Data signal Data is odd, and the parity bit 0, which means that the number of 1 in the Data signal Data is even; when the state signal a is 1, the parity E of 1 indicates that the number of 1 in the Data signal Data is even, and the parity E of 0 indicates that the number of 1 in the Data signal Data is odd. It is thereby achieved that the parity E can indicate whether the number of 1's in the Data signal Data is odd or even, regardless of whether the state signal a is set to a high-level signal or a low-level signal.
TABLE 1 relationship of parity bits to the number of 1's in the status signal and data signal
| Status signal A | Number of 1 in Data signal Data | |
| 0 | Odd number of | 1 |
| 0 | Even number of | 0 |
| 1 | Odd number of | 0 |
| 1 | Even number of | 1 |
For example, fig. 3 is a timing diagram corresponding to a parity check circuit according to an embodiment of the present invention, referring to fig. 2 and fig. 3, the Data signal Data is 00101101, the state signal a is 0, the first end input of the first operation module 130 is 0, the second end input is 0, after the first exclusive-or operation unit 131 performs the exclusive-or operation, the first bit B21 of the output second signal B2 is 0, and when the clock signal CLK is a rising edge, the second bit B11 of the first signal B1 output by the flip-flop 1411 is 0 so as to be used as an input of the next operation of the first exclusive-or operation unit 131; after the logical and operation unit 151 performs the logical and operation on the first bit B11 of the first signal B1 and the first bit C1 of the control signal C, the first bit B31 of the output third signal B3 is 0, the second exclusive-or operation unit 161 performs the exclusive-or operation on the first bit B31 of the third signal B3 and the first bit B21 of the second signal B2 and outputs 0, and so on, and finally the second exclusive-or operation unit 161 outputs 001011010, that is, the Data signal 00101101 and the parity bit 0, since the state signal a is 0, the parity bit 0 indicates that the number of 1 in the Data signal Data is even, and the result of the parity bit matches the situation of the Data signal.
Fig. 4 is a timing diagram corresponding to another parity check circuit provided by an embodiment of the present invention, referring to fig. 2 and 4, Data signal Data is 00111011, status signal a is 0, after the first xor operation unit 131, flip-flop 1411, and logical and operation unit 151 and second xor operation unit 161 are operated, the second xor operation unit 161 outputs 001110111, that is, outputs Data signal 00111011, parity bit 1, because status signal a is 0, parity bit 1 indicates that the number of 1 in Data signal Data is odd, and the result of parity bit matches the condition of Data signal.
Fig. 5 is a timing diagram corresponding to another parity check circuit according to an embodiment of the present invention, referring to fig. 2 and 5, Data signal Data is 00101101, status signal a is 1, after the first exclusive-or operation unit 131, flip-flop 1411, and logical and operation unit 151 and second exclusive-or operation unit 161 are operated, the second exclusive-or operation unit 161 outputs 001011011, that is, outputs Data signal 00101101 and parity bit 1, because status signal a is 1, parity bit 1 indicates that the number of 1 in Data signal Data is even, and the result of parity bit matches the condition of Data signal.
Fig. 6 is a timing diagram corresponding to another parity check circuit according to an embodiment of the present invention, referring to fig. 2 and 6, where Data signal Data is 00111011, status signal a is 1, after the first xor operation unit 131, flip-flop 1411, and logical and operation unit 151 and second xor operation unit 161 are operated, the second xor operation unit 161 outputs 001110110, that is, outputs Data signal 00111011, and parity bit 0, and since status signal a is 1, parity bit 0 indicates that the number of 1 in Data signal Data is odd, and the result of parity bit matches the condition of Data signal.
Fig. 7 is a flowchart of a parity checking method according to an embodiment of the present invention, and referring to fig. 7, the parity checking method includes:
s710, the first operation module receives the data signal, and the state setting module sends a state signal to the first operation module.
Specifically, the external Data module may send the Data signal Data to the first operation module 130, after the Data signal Data is sent, the output end of the external Data module is in a high impedance state, and the state setting module 110 may output a state signal a to the first operation module 130, where the state signal a may be a high level signal 1 or a low level signal 0.
S720, the first operation module performs logic operation on the data signal and the first signal output by the shift module, performs logic operation on the state signal and the first signal, and outputs a second signal.
Specifically, the first operation module 130 performs a logic operation according to the Data signal Data and a first signal B1 output by the shift module 140, and uses the result of the logic operation as a second signal B2, wherein the first signal B1 is output by the shift module 140 according to the second signal B2 output by the first operation module 130, the first signal B1 output by the shift module 140 defaults to 0 when the second signal B2 is not output by the first operation module 130, and the shift module 140 can output the first signal B1 according to the second signal B2 after the second signal B2 is output by the first operation module 130.
And S730, the shifting module shifts the second signal to output a first signal.
Specifically, after the first operation module 130 outputs the second signal B2, the shift module 140 may shift the second signal B2, for example, to the right by one bit, and output the shifted result as the first signal B1.
S740, the second operation module performs logic operation on the first signal and the control signal, and outputs a third signal.
Specifically, the second operation module 150 performs a logic operation on the first signal B1 and a control signal C, and outputs the result of the logic operation as a third signal B3, wherein the control signal C is, for example, a high signal 1 when the external Data module transmits the Data signal Data, and the control signal C is, for example, a low signal 0 when the state setting module 110 transmits the state signal a.
And S750, the third operation module performs logic operation on the third signal and the second signal and outputs a data signal and a parity check bit.
Specifically, the third operation module 160 performs a logical operation on the third signal B3 and the second signal B2, and outputs the Data signal Data and the parity E, the parity E for example indicates whether the number of 1 in the Data signal Data is odd or even, the parity E for example is 0 or 1, 0 indicates that the number of 1 in the Data signal Data is even, and 1 indicates that the number of 1 in the Data signal Data is odd; or 0 represents that the number of 1 in the Data signal Data is odd number, and 1 represents that the number of 1 in the Data signal Data is even number, so that whether the received Data signal Data is accurate can be judged according to the parity bit E, the parity check can be realized only by three operation modules and one shift module, the microcontroller is not required to be used for algorithm processing, and the effect of reducing the cost is achieved.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A parity check circuit, comprising: the device comprises a state setting module, a first operation module, a shifting module, a second operation module and a third operation module;
a first input end of the first operation module is accessed with a data signal;
the output end of the state setting module is electrically connected with the first input end of a first operation module, the second input end of the first operation module is electrically connected with the output end of the shift module, the output end of the first operation module is electrically connected with the input end of the shift module, the state setting module is used for outputting a state signal to the first operation module after the data signal is sent, and the first operation module is used for performing logic operation on the data signal and the first signal output by the shift module, performing logic operation on the state signal and the first signal, and outputting a second signal; the shift module is used for shifting the second signal to output a first signal;
a first input end of the second operation module is electrically connected with an output end of the shift module, a second input end of the second operation module is connected with a control signal, and the second operation module is used for performing logic operation on the first signal and the control signal and outputting a third signal;
the first input end of the third operation module is electrically connected with the output end of the second operation module, the second input end of the third operation module is electrically connected with the output end of the first operation module, and the third operation module is used for performing logic operation on the third signal and the second signal and outputting the data signal and the parity check bit.
2. The parity check circuit of claim 1, further comprising: a clock module;
the clock module is electrically connected with a clock end of the shift module, the clock module is used for outputting a clock signal, and the shift module is used for responding to the clock signal of the clock module to output the first signal.
3. The parity check circuit of claim 1, further comprising: a control module;
the control module is electrically connected with a second input end of the second operation module and is used for outputting the control signal.
4. The parity check circuit of claim 1, wherein the first operation module comprises a first exclusive or operation unit;
the first input end of the first exclusive-or operation unit is the first input end of the first operation module, the second input end of the first exclusive-or operation unit is the second input end of the first operation module, the output end of the first exclusive-or operation unit is the output end of the first operation module, and the first exclusive-or operation unit is used for performing logical exclusive-or operation on the data signal and the first signal output by the shift module, performing logical exclusive-or operation on the state signal and the first signal, and outputting a second signal.
5. The parity circuit of claim 1, wherein the second operation module comprises a logical and operation unit;
the first input end of the logical and operation unit is the first input end of the second operation module, the second input end of the logical and operation unit is the second input end of the second operation module, the output end of the logical and operation unit is the output end of the second operation module, and the logical and operation unit is used for performing logical and operation on the first signal and the control signal and outputting a third signal.
6. The parity circuit of claim 1, wherein the third operation module comprises a second exclusive or operation unit;
the first input end of the second exclusive-or operation unit is the first input end of the third operation module, the second input end of the second exclusive-or operation unit is the second input end of the third operation module, the output end of the second exclusive-or operation unit is the output end of the third operation module, and the second exclusive-or operation unit performs logic operation on the third signal and the second signal and outputs the data signal and the parity bit.
7. The parity check circuit of any of claims 1-6, wherein the shift module comprises a shift register;
the input end of the shift register is the input end of the shift module, the output end of the shift register is the output end of the shift module, and the shift register is used for outputting the first signal according to the second signal.
8. The parity circuit of claim 7, wherein the shift register comprises a flip-flop.
9. The parity check circuit of claim 1, further comprising a resistor;
the output end of the state setting module is electrically connected with the first input end of the first operation module through the resistor.
10. A parity check method, comprising:
the first operation module receives a data signal, and the state setting module sends a state signal to the first operation module;
the first operation module performs logic operation on the data signal and a first signal output by the shift module, performs logic operation on the state signal and the first signal, and outputs a second signal;
the shift module shifts the second signal to output a first signal;
the second operation module performs logic operation on the first signal and the control signal and outputs a third signal;
the third operation module performs logic operation on the third signal and the second signal and outputs the data signal and the parity bit.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111404307.4A CN114124109A (en) | 2021-11-24 | 2021-11-24 | Parity check circuit and method |
| PCT/CN2022/102661 WO2023093045A1 (en) | 2021-11-24 | 2022-06-30 | Parity check circuit and method |
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| CN202111404307.4A CN114124109A (en) | 2021-11-24 | 2021-11-24 | Parity check circuit and method |
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| WO (1) | WO2023093045A1 (en) |
Cited By (1)
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|---|---|---|---|---|
| WO2023093045A1 (en) * | 2021-11-24 | 2023-06-01 | 广东高标电子科技有限公司 | Parity check circuit and method |
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| KR100833604B1 (en) * | 2007-01-09 | 2008-05-30 | 삼성전자주식회사 | Parity error detecting circuit |
| US8639960B2 (en) * | 2011-05-27 | 2014-01-28 | Arm Limited | Verifying state integrity in state retention circuits |
| US20150363263A1 (en) * | 2014-06-12 | 2015-12-17 | HGST Netherlands B.V. | ECC Encoder Using Partial-Parity Feedback |
| CN113285725A (en) * | 2021-07-14 | 2021-08-20 | 南京宁麒智能计算芯片研究院有限公司 | QC-LDPC encoding method and encoder |
| CN114124109A (en) * | 2021-11-24 | 2022-03-01 | 广东高标电子科技有限公司 | Parity check circuit and method |
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| WO2023093045A1 (en) * | 2021-11-24 | 2023-06-01 | 广东高标电子科技有限公司 | Parity check circuit and method |
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