CN114123773A - Design method of single-inductor double-output DC-DC voltage reducer and voltage reducer thereof - Google Patents
Design method of single-inductor double-output DC-DC voltage reducer and voltage reducer thereof Download PDFInfo
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Abstract
The invention discloses a design method of a single-inductor double-output DC-DC voltage reducer, relates to the electronic technology, and solves the technical problems that the existing voltage reducer design scheme mostly only exists in a theoretical stage, or the voltage reducer designed according to the theory is difficult to meet the design requirement. According to the power level topological circuit principle, a power level topological model of a voltage reducer is built in simulation software; constructing a signal control model of the voltage reducer in simulation software according to a feedback control circuit principle; and carrying out simulation verification on the power level topology model and the signal control model to obtain the performance parameters of the voltage reducer circuit. The invention also discloses a single-inductor double-output DC-DC voltage reducer. The invention realizes the conversion of theory into concrete model, and can make the closed loop response after the control loop compensation more stable after simulation test, so that the design model meets the design requirement.
Description
Technical Field
The invention relates to the electronic technology, in particular to a design method of a single-inductor double-output DC-DC voltage reducer and the voltage reducer.
Background
A single-inductor multiple-output DC-DC voltage reducer (hereinafter referred to as "voltage reducer") requires fewer off-chip components to provide different output voltages to different branches. Namely, the function that different output branches output different voltages can be realized by sharing one inductor by each output branch, and the size and the cost of the circuit are reduced. The system architecture of the single-inductor dual-output DC-DC voltage reducer is generally divided into a power stage topology circuit and a feedback control circuit part. The system architecture of the single-inductor dual-output DC-DC voltage reducer is shown in FIG. 1. It includes an inductor, a feedback control circuit (not shown in the figure), two switching tubes located at the front end of the inductor, and two output loops located at the back end of the inductor. The control ends of the two switch tubes at the front end of the inductor and the switch tubes in the two output loops at the rear end of the inductor are connected with the output end of the feedback control circuit so as to realize the control of the output loops.
The feedback control circuit includes overall energy feedback control and energy distribution control between the output channels. The general energy feedback control method is mainly divided into three types, including a voltage control method, a current control method, and ripple-based control. The energy distribution control is roughly classified into a linear-based PWM modulation method, a charge-based control method, and a comparator-based control method. The average current method is used in combination with charge-based control as in reference [1 ]; reference [2] uses ripple-based control in combination with comparator control; reference [3] employs average current control, energy distribution control in combination with linear PWM modulation and comparator modulation.
Although the single-inductor multi-output DC-DC voltage reducer is realized in many ways, most design schemes only exist in a theoretical stage, or the voltage reducer designed according to the theory is difficult to meet the design requirements.
Among them, references:
[1] A. Pizzutelli and M. Ghioni, "Novel control technique for single inductor multiple output converters operating in CCM with reduced cross-regulation," 2008 Twenty-Third Annual IEEE Applied Power Electronics Conference and Exposition, 2008, pp. 1502-1507, doi: 10.1109/APEC.2008.4522923。
[2] ludan bamboo, research and design of a single-inductor multiple-output DC-DC converter based on ripple adaptive turn-off time control [ D ], Shanghai: university of Redan, 2013, DOI: 10.7666/d.Y2700989.
[3] Chen, Z., Li, C., Leung, K.N. and Zheng, Y. (2019), Single-inductor multiple-output DC–DC converter with duty-cycle-constrained comparator control. Electron. Lett., 55: 617-619. https://doi.org/10.1049/el.2019.0730。
Disclosure of Invention
The invention aims to solve the technical problem of the prior art, and provides a design method of a single-inductor double-output DC-DC voltage reducer and the voltage reducer thereof, which realize the conversion of theory into a specific model and make the model after simulation test meet the design requirements.
The invention relates to a design method of a single-inductor double-output DC-DC voltage reducer, which comprises the following steps of:
step one, constructing a power level topology model of a voltage reducer in simulation software according to a power level topology circuit principle;
secondly, constructing a signal control model of the voltage reducer in simulation software according to a feedback control circuit principle;
the signal control model is used for sampling output voltages of two output loops of the power level topology model and output current of an inductor to obtain a first sampling voltage, a second sampling voltage and a third sampling voltage corresponding to the inductor current, wherein the first sampling voltage, the second sampling voltage and the third sampling voltage are in one-to-one correspondence with the two output voltages; error calculation and compensation operation are carried out on the three sampled voltages through a second-order lag compensation network, and two output end duty ratio signals used for carrying out one-to-one corresponding control on two output loops and two control end duty ratio signals used for controlling inductance output in a power level topological model are obtained;
and step three, performing simulation verification on the power level topology model and the signal control model to obtain the performance parameters of the voltage reducer circuit.
Further improved, error calculation and compensation operation are carried out on the three sampled voltages through a second-order lag compensation network, specifically,
inputting the first sampling voltage and the second sampling voltage into an error amplifier, and respectively carrying out error amplification and compensation with a reference voltage to obtain a first error signal and a second error signal;
secondly, adding the first error signal and the second error signal to obtain a third error signal;
inputting the third error signal and the third sampling voltage into an error amplifier for error amplification and compensation to obtain a fourth error signal;
step four, comparing the fourth error signal with a preset ramp signal to obtain two control end duty ratio signals of the signal control model;
and fifthly, comparing the first error signal and the second error signal with the integrated value of the third error signal respectively to obtain duty ratio signals of output ends of the two output loops.
Furthermore, the third sampling voltage is sampled by a method comprising,
and sampling the current flowing through the inductor in the power stage topology model through an inductor current sampling network, and converting the output current into a third sampling voltage.
Further, the signal control model comprises a current loop control model and a voltage loop control model which are designed by an average current control method and a charge control method based on duty ratio division.
Furthermore, the construction method of the current loop control model comprises the following steps,
the method comprises the steps of firstly, acquiring small signal models and state equations of a power level topological circuit and a feedback control circuit, and acquiring transfer functions of all loops in the small signal models according to the small signal models and the state equations;
the second step,Obtaining an inductive current transfer function G in the small signal model by adopting a state space averaging methodid(s),
Wherein, VgIs the voltage of the grid electrode of the switch tube; l issIs the inductance value of the inductor; rDRCParasitic resistance that is an inductance;
thirdly, according to the transfer function G of the inductive currentid(s) and Current Loop Compensation function G in Small Signal modelci(s) module gain, obtaining a current loop open loop transfer function G of the current loop modeli(s),
Wherein, KADCIs the gain of the analog-to-digital converter in the feedback control circuit; kPWMIs the gain of a comparator in the feedback control circuit; gdelayFor the actively added delay, assume it is one cycle; k is the gain of an inductive current sampling network in the feedback control circuit;
fourthly, adding a pole at the zero frequency of the current loop control model, adding a zero at the main pole, and adjusting the gain to enable the current loop to have an open loop transfer function GiThe bandwidth of(s) is less than half of the switching frequency of the current loop control model.
Further, the current loop open loop transfer function GiThe phase margin of the bandwidth(s) is 55-65 DEG, and the gain is 10-15 dB.
Furthermore, the voltage loop control model is constructed by the following steps,
a first step of obtaining a closed loop transfer function Ti(s) of the current loop model according to a functional relation between a forward transfer function G(s) of the current loop and a feedback transfer function F(s) of the current loop in the small signal model,
secondly, obtaining an output impedance transfer function Z of the voltage loop model according to the state equationoi，
Wherein R isoiIs an output resistor; coiIs an output capacitor; rESRA parasitic resistance that is an output capacitance;
thirdly, obtaining a voltage loop open-loop transfer function G of the voltage loop model according to the relation between the transfer functions of all loops in the small signal modelvi(s)，
Wherein G isvci(s) is a compensation function for the voltage loop; gvd(s) is the transfer function of the power stage; h(s) is the transfer function of the sampling network.
Further, the voltage loop open loop transfer function Gvi(s) bandwidth of current loop open loop transfer function Gi(s) 1/4-1/5 of bandwidth, and 15dB-25dB of gain.
Further, modeling and simulation verification are carried out on the power level topological model and the signal control model through matlab software and simulink software.
A single-inductor dual-output DC-DC voltage reducer is manufactured by applying performance parameters determined by the design method.
Advantageous effects
The invention has the advantages that: modeling the voltage reducer system in simulation software based on the principle theory of the voltage reducer, and carrying out simulation test to obtain performance parameters. Therefore, the theory is converted into a concrete model, the closed loop response after the control loop compensation can be more stable after simulation test, and the design model meets the design requirement.
Drawings
FIG. 1 is a system architecture diagram of a single-inductor dual-output DC-DC voltage reducer;
FIG. 2 is a block diagram of a small signal model;
FIG. 3 is a diagram of the architecture of the single-inductor dual-output DC-DC voltage reducer control loop system of the present invention;
FIG. 4 is a schematic diagram of a frequency response of a simulation result of the current loop control model according to the present invention;
FIG. 5 is a diagram illustrating simulation results of one output circuit of the voltage reducer according to the present invention;
FIG. 6 is an enlarged view of a portion of FIG. 5;
FIG. 7 is a diagram illustrating simulation results of another output loop of the voltage reducer of the present invention;
fig. 8 is a partially enlarged view of fig. 7.
Detailed Description
The invention is further described below with reference to examples, but not to be construed as being limited thereto, and any number of modifications which can be made by anyone within the scope of the claims are also within the scope of the claims.
Referring to fig. 2 to 3, the method for designing a single-inductor dual-output DC-DC voltage reducer of the present invention includes the following steps:
step one, according to the power level topological circuit principle, a power level topological model of a voltage reducer is built in simulation software.
Specifically, the power stage topology model of the voltage reducer shown in fig. 1 has the following relational expression, so that the supply topology model can be constructed by matlab software and simulink software to obtain the simulink model of the power stage.
And secondly, constructing a signal control model of the voltage reducer in simulation software according to the feedback control circuit principle.
In the embodiment, modeling and simulation verification are performed on the power level topological model and the signal control model through matlab software and simulink software, and finally the power level topological model and the signal control model are converted into a circuit to verify the feasibility of the circuit.
Specifically, the signal control model is used for sampling output voltages of two output loops of the power level topology model and output currents of the inductor to obtain a first sampling voltage, a second sampling voltage and a third sampling voltage, wherein the first sampling voltage, the second sampling voltage and the third sampling voltage correspond to the inductor currents in a one-to-one correspondence mode.
The third sampling voltage is sampled by an inductor current sampling network, and the current flowing through an inductor in the power level topology model is sampled, and the output current is converted into the third sampling voltage.
And performing error calculation and compensation operation on the three sampled voltages through a second-order lag compensation network to obtain two output end duty ratio signals for performing one-to-one corresponding control on the two output loops and two control end duty ratio signals for controlling inductance output in the power level topology model.
In this embodiment, the error calculation and compensation operation are performed on the three sampled voltages through the second-order lag compensation network, specifically,
the method comprises the steps of firstly, inputting a first sampling voltage and a second sampling voltage into an error amplifier, and respectively carrying out error amplification and compensation with a reference voltage to obtain a first error signal and a second error signal. In fig. 3, the first sampled voltage is denoted as Vo 1; the second sampled voltage is denoted as Vo 2; the first error signal is denoted as VC 1; the second error signal is denoted as VC 2.
And secondly, adding the first error signal and the second error signal to obtain a third error signal which is recorded as VCI.
And thirdly, inputting the third error signal and the third sampling voltage into an error amplifier for error amplification and compensation to obtain a fourth error signal. The third sampling voltage is recorded as Vsample; the fourth error signal is denoted as VI.
And step four, comparing the fourth error signal with a preset ramp signal to obtain two control end duty ratio signals of the signal control model. Namely, the two control end duty ratio signals are respectively used for controlling the two switching tubes positioned at the front end of the inductor as shown in fig. 1.
And fifthly, comparing the first error signal and the second error signal with the integrated value of the third error signal respectively to obtain duty ratio signals of output ends of the two output loops. I.e. the two output end duty cycle signals are respectively used for controlling the two output loops at the back end of the inductor as shown in fig. 1.
As for the signal control model of the present embodiment, it includes a current loop control model and a voltage loop control model designed by an average current control method and a charge control method based on duty division. That is, the main loop employs an average current control method, and the two output loops employ a charge control method based on duty division.
Specifically, the current loop control model is constructed by,
the method comprises the steps of firstly, acquiring small signal models and state equations of a power level topological circuit and a feedback control circuit, and acquiring transfer functions of all loops in the small signal models according to the small signal models and the state equations.
Secondly, obtaining an inductive current transfer function G in a small signal model by adopting a state space averaging methodid(s),
Wherein, VgIs the voltage of the grid electrode of the switch tube; l issIs the inductance value of the inductor; rDRCIs the parasitic resistance of the inductor.
Thirdly, according to the transfer function G of the inductive currentid(s) and Current Loop Compensation function G in Small Signal modelci(s) module gain, obtaining a current loop open loop transfer function G of the current loop modeli(s),
Wherein, KADCIs the gain of the analog-to-digital converter; kPWMIs the gain of the comparator; gdelayFor the actively added delay, assume it is one cycle; and K is the gain of the inductive current sampling network.
Fourthly, adding a pole at the zero frequency of the current loop control model, adding a zero at the main pole, compensating the current loop model, and adjusting the gain to enable the current loop to have an open-loop transfer function GiThe bandwidth of(s) is less than half of the switching frequency of the current loop control model. And in selecting the current loop open loop transfer function Gi(s) the larger the bandwidth, the better. The zeros may be added here using the sisotool tool in the matlab software.
Current loop open loop transfer function GiThe phase margin of the bandwidth(s) is 55-65 DEG, and the gain is 10-15 dB. Specifically, the phase margin can be selected to be 60 degrees, and the gain is 10 dB.
The voltage loop control model is constructed by the following method,
firstly, obtaining a closed loop transfer function T of a current loop model according to a functional relation between a forward transfer function G(s) of the current loop and a feedback transfer function F(s) of the current loop in a small signal modeli(s),
Secondly, obtaining an output impedance transfer function Z of the voltage loop model according to the state equationoi，
Wherein R isoiIs an output resistor; coiIs an output capacitor; rESRParasitic resistance as output capacitance。
Thirdly, obtaining a voltage loop open-loop transfer function G of the voltage loop model according to the relation between the transfer functions of all loops in the small signal modelvi(s)，
Wherein G isvci(s) is a compensation function for the voltage loop; gvd(s) is the transfer function of the power stage; h(s) is the transfer function of the sampling network.
The voltage loop is compensated in a similar way to the current loop, but the voltage loop has an open loop transfer function Gvi(s) bandwidth of current loop open loop transfer function Gi(s) 1/4-1/5 of bandwidth, and a gain of 20 dB. For the trade-off, the phase margin is around 80 °.
The power level topological model and the signal control model constructed according to the design method can simulate the whole module in simulink software.
And step three, performing simulation verification on the power level topology model and the signal control model to obtain the performance parameters of the voltage reducer circuit. Namely, a proper circuit is selected according to the performance parameters to build the whole system. As shown in fig. 3, the signal control model architecture built in this embodiment mainly includes a sampling network, an inductive current sampling network, a compensation module, a PWM module, and a driving module. The compensation module mainly comprises a second-order lag compensation network formed by an error amplifier, a resistor and a capacitor, and introduces a zero point and a second-order pole. The zero position refers to the zero position of the sisotool tool during compensation, and the secondary pole position is near the switching frequency. The PWM module is a comparator, the output of the comparator is connected with a driving module, and the driving module is an inverter chain and a control logic part which are increased step by step. And testing and simulating each module, and finally connecting the modules through the top module to form an integral sido circuit structure for testing and simulating.
Taking the current loop control model as an example, the open-loop frequency response and the closed-loop frequency response after adding compensation to the matlab software are shown in fig. 4. In the figure, the broken line is the open loop frequency and the solid line is the compensated closed loop frequency. It can be seen that the dominant pole before compensation is about 3.29khz and the gain after compensation drops from 58db with a phase margin of 57 °. Therefore, the low-frequency gain of the actual compensation module itself during open loop needs to be about 78dB, and the zero point position introduced by the second-order lag compensation network is the main pole position before compensation.
The feasibility of the proposed model is verified through simulink software simulation test, the theory is converted into a specific model, the compensated closed loop response is stable, and the overall performance meets the requirements.
Taking 0.18umBCD process as an example, simulation results of the single-inductor dual-output DC-DC voltage reducer in simulink software are shown in FIGS. 5-8. It can be seen from FIGS. 5-8 that Vo1 is about 1.2V and the voltage ripple is about 49 mV; vo2 is about 1.8V and the voltage ripple is about 43 mV.
A single-inductor dual-output DC-DC voltage reducer is manufactured by applying the performance parameters determined by the design method.
Converting each module into a specific circuit, referring to parameters of a model during simulation, designing a corresponding compensation circuit according to parameters of a compensation system established by using the ssotool during modeling compensation, selecting a corresponding circuit module according to the proposed control method, and finally completing the design and simulation test of the whole circuit.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make various changes and modifications without departing from the structure of the invention, which will not affect the effect of the invention and the practicability of the patent.
Claims (9)
1. A design method of a single-inductor dual-output DC-DC voltage reducer is characterized by comprising the following steps:
step one, constructing a power level topology model of a voltage reducer in simulation software according to a power level topology circuit principle;
secondly, constructing a signal control model of the voltage reducer in simulation software according to a feedback control circuit principle;
the signal control model is used for sampling output voltages of two output loops of the power level topology model and output current of an inductor to obtain a first sampling voltage, a second sampling voltage and a third sampling voltage corresponding to the inductor current, wherein the first sampling voltage, the second sampling voltage and the third sampling voltage are in one-to-one correspondence with the two output voltages; error calculation and compensation operation are carried out on the three sampled voltages through a second-order lag compensation network, and two output end duty ratio signals used for carrying out one-to-one corresponding control on two output loops and two control end duty ratio signals used for controlling inductance output in a power level topological model are obtained;
and step three, performing simulation verification on the power level topology model and the signal control model to obtain the performance parameters of the voltage reducer circuit.
2. The design method of the single-inductor dual-output DC-DC step-down transformer of claim 1, wherein error calculation and compensation operation are performed on the three sampled voltages through a second-order lag compensation network, and specifically,
inputting the first sampling voltage and the second sampling voltage into an error amplifier, and respectively carrying out error amplification and compensation with a reference voltage to obtain a first error signal and a second error signal;
secondly, adding the first error signal and the second error signal to obtain a third error signal;
inputting the third error signal and the third sampling voltage into an error amplifier for error amplification and compensation to obtain a fourth error signal;
step four, comparing the fourth error signal with a preset ramp signal to obtain two control end duty ratio signals of the signal control model;
and fifthly, comparing the first error signal and the second error signal with the integrated value of the third error signal respectively to obtain duty ratio signals of output ends of the two output loops.
3. The design method of the single-inductor dual-output DC-DC step-down transformer of claim 2, wherein the third sampling voltage is sampled by,
and sampling the current flowing through the inductor in the power stage topology model through an inductor current sampling network, and converting the output current into a third sampling voltage.
4. The method for designing a single-inductor dual-output DC-DC step-down transformer according to claim 2, wherein the signal control model comprises a current loop control model and a voltage loop control model designed by an average current control method and a charge control method based on duty cycle division.
5. The design method of the single-inductor dual-output DC-DC step-down transformer according to claim 4, wherein the current loop control model is constructed by the steps of,
the method comprises the steps of firstly, acquiring small signal models and state equations of a power level topological circuit and a feedback control circuit, and acquiring transfer functions of all loops in the small signal models according to the small signal models and the state equations;
secondly, obtaining an inductive current transfer function G in the small signal model by adopting a state space averaging methodid(s),
Wherein, VgIs the voltage of the grid electrode of the switch tube; l issIs the inductance value of the inductor; rDRCParasitic resistance that is an inductance;
thirdly, according to the transfer function G of the inductive currentid(s) and Current Loop Compensation function G in Small Signal modelci(s) module gain, obtaining a current loop open loop transfer function G of the current loop modeli(s),
Wherein, KADCIs the gain of the analog-to-digital converter in the feedback control circuit; kPWMIs the gain of a comparator in the feedback control circuit; gdelayFor the actively added delay, assume it is one cycle; k is the gain of an inductive current sampling network in the feedback control circuit;
fourthly, adding a pole at the zero frequency of the current loop control model, adding a zero at the main pole, and adjusting the gain to enable the current loop to have an open loop transfer function GiThe bandwidth of(s) is less than half of the switching frequency of the current loop control model.
6. The design method of a single-inductor dual-output DC-DC step-down transformer according to claim 5, wherein the current loop open-loop transfer function G isiThe phase margin of the bandwidth(s) is 55-65 DEG, and the gain is 10-15 dB.
7. The design method of the single-inductor dual-output DC-DC step-down transformer according to claim 5, wherein the voltage loop control model is constructed by the steps of,
firstly, obtaining a closed loop transfer function T of the current loop model according to a functional relation between a forward transfer function G(s) of the current loop and a feedback transfer function F(s) of the current loop in the small signal modeli(s),
Secondly, obtaining an output impedance transfer function Z of the voltage loop model according to the state equationoi，
Wherein R isoiIs an output resistor; coiTo be transportedDischarging a capacitor; rESRA parasitic resistance that is an output capacitance;
thirdly, obtaining a voltage loop open-loop transfer function G of the voltage loop model according to the relation between the transfer functions of all loops in the small signal modelvi(s)，
Wherein G isvci(s) is a compensation function for the voltage loop; gvd(s) is the transfer function of the power stage; h(s) is the transfer function of the sampling network.
8. The method of claim 7, wherein the voltage loop open loop transfer function G is a voltage loop open loop transfer functionvi(s) bandwidth of current loop open loop transfer function Gi(s) 1/4-1/5 of bandwidth, and 15dB-25dB of gain.
9. The design method of the single-inductor dual-output DC-DC voltage reducer according to any one of claims 1-8, characterized in that the power stage topology model and the signal control model are modeled and verified by matlab software and simulink software.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116388568A (en) * | 2023-03-28 | 2023-07-04 | 四川大学 | Control method and device for single-inductor double-output switch converter |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103560668A (en) * | 2013-11-12 | 2014-02-05 | 东南大学 | Method for realizing secondary switch 100% duty ratio output in single-inductor dual-output converter |
| CN103856045A (en) * | 2012-12-04 | 2014-06-11 | 韩山师范学院 | Fuzzy PI double-loop control method based on stratification thoughts |
| CN110165890A (en) * | 2018-02-14 | 2019-08-23 | 三星电子株式会社 | The electronic circuit of buck-boost conversion is executed using single inductance element |
| CN110492738A (en) * | 2019-08-08 | 2019-11-22 | 华南理工大学 | A kind of list inductance multi-output dc-DC buck converter |
| CN112671229A (en) * | 2021-01-12 | 2021-04-16 | 无锡中感微电子股份有限公司 | Single-inductor multi-output DC-DC converter |
| CN113410987A (en) * | 2021-05-14 | 2021-09-17 | 杭州电子科技大学 | Extreme learning machine-based sliding mode variable structure Buck circuit control method |
-
2022
- 2022-01-28 CN CN202210103670.0A patent/CN114123773B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103856045A (en) * | 2012-12-04 | 2014-06-11 | 韩山师范学院 | Fuzzy PI double-loop control method based on stratification thoughts |
| CN103560668A (en) * | 2013-11-12 | 2014-02-05 | 东南大学 | Method for realizing secondary switch 100% duty ratio output in single-inductor dual-output converter |
| CN110165890A (en) * | 2018-02-14 | 2019-08-23 | 三星电子株式会社 | The electronic circuit of buck-boost conversion is executed using single inductance element |
| CN110492738A (en) * | 2019-08-08 | 2019-11-22 | 华南理工大学 | A kind of list inductance multi-output dc-DC buck converter |
| CN112671229A (en) * | 2021-01-12 | 2021-04-16 | 无锡中感微电子股份有限公司 | Single-inductor multi-output DC-DC converter |
| CN113410987A (en) * | 2021-05-14 | 2021-09-17 | 杭州电子科技大学 | Extreme learning machine-based sliding mode variable structure Buck circuit control method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116388568A (en) * | 2023-03-28 | 2023-07-04 | 四川大学 | Control method and device for single-inductor double-output switch converter |
| CN116388568B (en) * | 2023-03-28 | 2024-03-22 | 四川大学 | Control method and device for single-inductor double-output switch converter |
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| CN114123773B (en) | 2022-06-03 |
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