CN114122127A - Nitride HEMT device provided with combined passivation medium and preparation method - Google Patents
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- 238000002360 preparation method Methods 0.000 title claims abstract description 13
- 238000002161 passivation Methods 0.000 title abstract description 19
- 230000004888 barrier function Effects 0.000 claims abstract description 42
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000000137 annealing Methods 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims description 68
- 229910052751 metal Inorganic materials 0.000 claims description 68
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 24
- 229910052710 silicon Inorganic materials 0.000 claims description 24
- 239000010703 silicon Substances 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 22
- 238000005530 etching Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 12
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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Abstract
The invention relates to a nitride HEMT device with a combined passivation medium and a preparation method thereof, wherein the combined passivation medium with different stresses is adopted in a grid region, and a compressive stress medium is adopted to offset the tensile stress of a barrier layer, so that the piezoelectric polarization is reduced, the heterojunction interface polarization charge density is reduced, the 2DEG concentration is reduced, and the threshold value of the device is improved; and a tensile stress medium is adopted in the drain electrode area, so that the piezoelectric polarization of the barrier layer is enhanced, the polarization charge density of the heterojunction interface is increased, the 2DEG concentration is increased, and the on-resistance of the device is reduced. Meanwhile, the concentration of the 2DEG in the grid electrode region is small, the spread width of a depletion region is large, the peak electric field of the grid electrode region can be effectively reduced, and the current collapse effect is restrained. When the compressive stress dielectric layer or the tensile stress dielectric layer is prepared, the tensile stress dielectric layer or the compressive stress dielectric layer on the whole surface is deposited firstly, and then the tensile stress dielectric layer or the compressive stress dielectric layer is converted into the compressive stress dielectric layer or the tensile stress dielectric layer through high-temperature annealing, so that the defects of complicated conventional procedures, small process window and the like are overcome.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a nitride HEMT device provided with a combined passivation medium and a preparation method of the nitride HEMT device provided with the combined passivation medium.
Background
Nitride HEMT devices are widely used in the fields of microwave, high power and the like due to the advantages of large current density, high output power, high working frequency, excellent radiation resistance and the like.
However, the threshold voltage of a nitride HEMT device is closely related to the 2DEG (two-dimensional electron gas) density under the gate, the smaller the 2DEG density, the larger the threshold voltage of the device; the greater the 2DEG density, the lower the threshold voltage of the device. Taking GaN HEMT devices as an example, in order to obtain a large threshold voltage, the 2DEG concentration can be reduced by reducing the Al composition or thickness of the AlGaN barrier layer. However, the reduced concentration of 2DEG results in a large on-resistance of the device, thereby increasing the on-loss of the device.
In addition, the nitride HEMT device may have a lower leakage current than an expected value under a certain condition, and may be defined as a current collapse effect. The current collapse effect reduces the output current of the device, increases the conduction loss, reduces the output power density, deteriorates the performance of the device and influences the work of the device.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a nitride HEMT device with a combined passivation medium and a preparation method thereof.
The technical scheme of the invention is as follows:
a nitride HEMT device comprises a substrate, a buffer layer, a channel layer, a barrier layer, a P-type nitride gate layer, a source metal and a drain metal; a gate metal is arranged on the P-type nitride gate layer, the P-type nitride gate layer and a certain range of area around the P-type nitride gate layer are defined as a gate area, the source metal and a certain range of area around the source metal are defined as a source area, and the drain metal and a certain range of area around the drain metal are defined as a drain area; the grid electrode area and the source electrode area are covered with a compressive stress dielectric layer, and the drain electrode area is covered with a tensile stress dielectric layer; the ratio of the width X to the width Y of the compressive stress dielectric layer to the width Y of the tensile stress dielectric layer between the P-type nitride gate layer and the drain metal is 0.1< X to Y < 10.
Preferably, the ratio of the width X: Y of the compressive stress dielectric layer to the width Y of the tensile stress dielectric layer between the P-type nitride gate layer and the drain metal is 0.5< X: Y < 2.
Preferably, the compressive stress medium layer comprises a stress medium layer; or the compressive stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different; the thickness of the compressive stress dielectric layer is 50 nm-1000 nm, and the stress value range is-0.1 GPa-5 GPa;
the tensile stress medium layer comprises a stress medium layer; or the tensile stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different; the thickness of the tensile stress dielectric layer is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
Preferably, the stress medium of the compressive stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the stress medium of the tensile stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride.
A preparation method of a nitride HEMT device comprises the following steps:
1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; selectively etching the P-type nitride layer to form a P-type nitride gate layer; preparing source metal and drain metal on the surface of the barrier layer; the P-type nitride gate layer and a region in a certain range around the P-type nitride gate layer are defined as a gate region, the source metal and a region in a certain range around the source metal are defined as a source region, and the drain metal and a region in a certain range around the drain metal are defined as a drain region;
2) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the gate region, the source region and the drain region;
or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the gate region, the source region and the drain region;
3) removing the compressive stress medium layer covering the drain region;
or removing the tensile stress dielectric layer covering the gate region and the source region;
4) depositing a tensile stress medium layer on the surface of the nitride epitaxial structure, wherein the tensile stress medium layer covers the compressive stress medium layer and the drain region;
or depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the tensile stress dielectric layer, the gate region and the source region;
the thickness of the compressive stress dielectric layer is 50 nm-1000 nm, and the stress value range is-0.1 GPa-5 GPa;
the thickness of the tensile stress dielectric layer is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
Preferably, the method also comprises the step 5) of removing the tensile stress dielectric layer covering the compressive stress dielectric layer;
or removing the compressive stress dielectric layer covering the tensile stress dielectric layer.
Preferably, the compressive stress medium layer comprises a stress medium layer; or the compressive stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the compressive stress medium layer comprises at least two stress medium layers, the stress medium layers of the compressive stress medium layer are sequentially deposited layer by layer in the step 2) or the step 4);
the tensile stress medium layer comprises a stress medium layer; or the tensile stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the tensile stress medium layer comprises at least two stress medium layers, the stress medium layers of the tensile stress medium layer are sequentially deposited layer by layer in the step 2) or the step 4).
Preferably, the stress medium of the compressive stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the stress medium of the tensile stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride.
A preparation method of a nitride HEMT device comprises the following steps:
1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; selectively etching the P-type nitride layer to form a P-type nitride gate layer; preparing source metal and drain metal on the surface of the barrier layer; the P-type nitride gate layer and a region in a certain range around the P-type nitride gate layer are defined as a gate region, the source metal and a region in a certain range around the source metal are defined as a source region, and the drain metal and a region in a certain range around the drain metal are defined as a drain region;
2) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the gate region, the source region and the drain region;
or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the gate region, the source region and the drain region;
3) performing high-temperature annealing to convert the compressive stress dielectric layer into a tensile stress dielectric layer;
or, carrying out high-temperature annealing to convert the tensile stress dielectric layer into a compressive stress dielectric layer;
4) removing the tensile stress dielectric layer covering the gate region and the source region;
or removing the compressive stress dielectric layer covering the drain region;
5) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the gate region, the source region and the tensile stress dielectric layer;
or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the drain region and the compressive stress dielectric layer;
the thickness of the compressive stress dielectric layer is 50 nm-1000 nm, and the stress value range is-0.1 GPa-5 GPa;
the thickness of the tensile stress dielectric layer is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
Preferably, the method also comprises the step 6) of removing the compressive stress dielectric layer covered on the tensile stress dielectric layer;
or removing the tensile stress medium layer covering the compressive stress medium layer.
Preferably, in the step 3), the annealing temperature is 700-1000 ℃, and the annealing time is 1-5 hours.
Preferably, the compressive stress medium layer comprises a stress medium layer; or the compressive stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the compressive stress medium layer comprises at least two stress medium layers, the stress medium layers of the compressive stress medium layer are sequentially deposited layer by layer in the step 5);
the tensile stress medium layer comprises a stress medium layer; or the tensile stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the tensile stress medium layer comprises at least two stress medium layers, the stress medium layers of the tensile stress medium layer are sequentially deposited layer by layer in the step 5).
Preferably, the stress medium of the compressive stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the stress medium of the tensile stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride.
The invention has the following beneficial effects:
according to the nitride HEMT device provided with the combined passivation medium, the combined passivation medium with different stresses is adopted, and the compressive stress medium is adopted in the grid region and can offset the tensile stress of the barrier layer, so that the piezoelectric polarization is reduced, the heterojunction interface polarization charge density is reduced, the 2DEG concentration is reduced, and the threshold value of the device is improved; and a tensile stress medium is adopted in the drain electrode area, so that the piezoelectric polarization of the barrier layer is enhanced, the polarization charge density of the heterojunction interface is increased, the 2DEG concentration is increased, and the on-resistance of the device is reduced. Meanwhile, the concentration of the 2DEG in the grid electrode region is small, the spread width of a depletion region is large, the peak electric field of the grid electrode region can be effectively reduced, and the current collapse effect is restrained.
The invention ensures smaller on-resistance on the basis of improving the threshold voltage of the nitride device, reduces the peak electric field of the grid region and inhibits current collapse.
In the invention, the compressive stress medium layer and the tensile stress medium layer can be of a single-layer film structure or a multi-layer film structure; when the multilayer film structure is implemented, the low-stress dielectric layer or the unstressed dielectric layer plays a passivation role and protects the surface of a device.
The preparation method of the nitride HEMT device provided with the combined passivation medium is used for preparing the nitride HEMT device, wherein the tensile stress medium layer is prepared in the drain region, the compressive stress medium layer is prepared in the source region and the gate region, the piezoelectric polarization of the barrier layer is weakened through the compressive stress medium layer, and the polarization charge density of the heterojunction interface is reduced, so that the 2DEG concentration is reduced, and the threshold value of the device is improved; the piezoelectric polarization is enhanced through the tensile stress medium layer, so that the 2DEG concentration is improved, and the resistance of a channel is reduced. Meanwhile, the concentration of the 2DEG in the grid electrode region is small, the spread width of a depletion region is large, the peak electric field of the grid electrode region can be effectively reduced, and the current collapse effect is restrained.
When the compressive stress medium layer or the tensile stress medium layer is prepared, the tensile stress medium layer or the compressive stress medium layer on the whole surface can be deposited firstly, and then the tensile stress medium layer or the compressive stress medium layer is converted into the compressive stress medium layer or the tensile stress medium layer through high-temperature annealing, so that the defects of complicated conventional procedures, small process window and the like are overcome.
Drawings
Fig. 1 is a structural cross-sectional view of a P-type nitride HEMT device (the compressive stress dielectric layer and the tensile stress dielectric layer are of a single-layer structure);
fig. 2 is a structural cross-sectional view of a P-type nitride HEMT device (the compressive stress dielectric layer and the tensile stress dielectric layer are of a multilayer structure);
fig. 3 is a cross-sectional view of the structure of a P-type nitride HEMT device (with the unstressed dielectric layer lowermost);
fig. 4 is a structural cross-sectional view of a P-type nitride HEMT device;
in the figure: 10 is a substrate, 11 is a buffer layer, 12 is a barrier layer, 13 is a P-type nitride gate layer, 14 is a source metal, 15 is a drain metal, 16 is a gate metal, 20 is a compressive stress dielectric layer, 201 is a first compressive stress dielectric sublayer, 202 is a second compressive stress dielectric sublayer, 203 is a third compressive stress dielectric sublayer, 21 is a tensile stress dielectric layer, 211 is a first tensile stress dielectric sublayer, 212 is a second tensile stress dielectric sublayer, and 213 is a third tensile stress dielectric sublayer.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Example 1
A nitride HEMT device provided with a combined passivation medium, as shown in fig. 1 and 2, includes a substrate 10, a buffer layer 11, a channel layer, a barrier layer 12, a P-type nitride gate layer 13, a source metal 14, a drain metal 15; a gate metal 16 is disposed on the P-type nitride gate layer 13, the gate region and the source region are covered with a compressive dielectric layer 20, and the drain region is covered with a tensile dielectric layer 21. The P-type nitride gate layer 13 and a region of a certain range around it are defined as a gate region, the source metal 14 and a region of a certain range around it are defined as a source region, and the drain metal 15 and a region of a certain range around it are defined as a drain region; the gate, source and drain regions typically include a P-nitride gate layer 13, a source metal 14, a drain metal 15, a peripheral metal region and a metal-free region.
The material of the P-type nitride gate layer is P-GaN, P-AlGaN, P-InGaN or P-InAlGaN.
The invention provides a combined passivation medium, namely a compressive stress medium layer 20 combined with a tensile stress medium layer 21, which can improve the threshold value of a device, inhibit current collapse and ensure that the device has smaller on-resistance. Compared with the combined passivation medium of the invention, if a single stress medium is adopted, the defects are that: by adopting a single compressive stress medium, although the threshold value of the device can be improved, the on-resistance of the device is very large, so that the on-loss of the device is increased; the single tensile stress medium is adopted, so that the on resistance of the device can be reduced, the saturation current of the device can be improved, and the threshold value of the device can be reduced.
In this embodiment, the nitride HEMT device includes a substrate 10, a GaN buffer layer 11, a channel layer, an AlGaN barrier layer 12, and a P-type nitride gate layer 13, and the thickness of the GaN buffer layer 11 is greater than that of the AlGaN barrier layer 12. Since the GaN buffer layer 11 and the AlGaN barrier layer 12 are both Ga-plane polarized, the spontaneous polarization directions in the GaN buffer layer 11 and the AlGaN barrier layer 12 are the same. When a thin AlGaN barrier layer 12 (with respect to the GaN buffer layer 11) is grown on a thick GaN buffer layer 11 (with respect to the AlGaN barrier layer 12), the thin AlGaN barrier layer 12 is under tensile stress because the lattice constant of AlGaN is smaller than that of GaN, while the GaN buffer layer 11 is relatively thick and stress is relieved.
For Ga-face materials, the AlGaN barrier layer 12 is under tensile stress to form a piezoelectric polarization that is directed toward the substrate 10 in the same direction as the spontaneous polarization, and thus the same spontaneous polarization and piezoelectric polarization direction further increases the positive polarization charge at the interface. In order to maintain the equilibrium state, freely movable electrons are induced at the interface side of the GaN buffer layer 11, and the electrons can freely move only in a plane parallel to the interface of the GaN buffer layer 11, but are confined in a direction perpendicular to the interface of the GaN buffer layer 11, i.e., a two-dimensional electron gas (2 DEG).
It can be seen that the 2DEG concentration is closely related to the polarization strength, and the compressive stress dielectric layer 20 counteracts the tensile stress applied to the AlGaN barrier layer 12, so that the piezoelectric polarization is reduced, the 2DEG concentration below the compressive stress dielectric layer 20 is reduced, and the threshold voltage of the device is increased. Meanwhile, because the 2DEG concentration is reduced, a depletion region formed by the device in an off state is larger, the electric field intensity is reduced, and the peak electric field of the gate region is also reduced. The current collapse of the device is closely related to the electric field intensity, and the stronger the electric field is, the more serious the current collapse is, so that the compressive stress dielectric layer 20 can improve the current collapse of the device. On the other hand, the tensile stress medium layer 21 can enhance the piezoelectric polarization, so that the 2DEG concentration is increased, and the resistance of the channel can be reduced.
In the present invention, the compressive stress dielectric layer 20 and the tensile stress dielectric layer 21 may be implemented as a single-layer structure or a multi-layer structure; furthermore, the compressive stress medium layer 20 with a single-layer structure may be combined with the tensile stress medium layer 21 with a multi-layer structure, the compressive stress medium layer 20 with a multi-layer structure may be combined with the tensile stress medium layer 21 with a single-layer structure, or the compressive stress medium layer 20 with a multi-layer structure may be combined with the tensile stress medium layer 21 with a multi-layer structure. When the compressive stress dielectric layer 20 and the tensile stress dielectric layer 21 are implemented as a multilayer structure, particularly when one layer of the multilayer structure is a low-stress dielectric layer or an unstressed dielectric layer and directly covers the surface of the AlGaN barrier layer 12, the dielectric layer can be used as a passivation layer to protect the surface of the AlGaN barrier layer 12, so that the AlGaN barrier layer 12 in a non-gate region can be prevented from being damaged and a large number of surface states can be introduced when the compressive stress dielectric layer 20 and the tensile stress dielectric layer 21 are deposited by using PECVD.
Specifically, the compressive stress dielectric layer 20 includes a stress dielectric layer (i.e., a single-layer film structure); alternatively, the compressive stress medium layer 20 includes at least two stress medium layers (i.e., a multilayer film structure), such as a first compressive stress medium sublayer 201, a second compressive stress medium sublayer 202, and the like, and the stress values of adjacent stress medium layers are different. When the compressive stress dielectric layer 20 is implemented as two or more stress dielectric layers, in particular, when the stress value of the stress dielectric layer facing the AlGaN barrier layer 12 is the lowest stress dielectric layer (e.g., the stress value ranges from-250 MPa to 150MPa, i.e., the compressive stress formed by the low stress dielectric layer in the compressive stress dielectric layer 20 is smaller than that of the adjacent stress dielectric layer, or the tensile stress formed by the low stress dielectric layer in the tensile stress dielectric layer 21 is smaller than that of the adjacent stress dielectric layer) or the stress-free dielectric layer, the compressive stress dielectric layer can be used as a passivation layer to protect the surface of the AlGaN barrier layer 12.
In this embodiment, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride (such as SiN), silicon oxide (SiO) or silicon oxynitride (SiON), that is, when the compressive stress medium layer 20 is implemented as a single-layer structure and the compressive stress medium layer 20 includes a stress medium layer, the stress medium of the compressive stress medium layer 20 is one of silicon nitride, silicon oxide or silicon oxynitride; when the compressive stress dielectric layer 20 is implemented as a multilayer structure, and the compressive stress dielectric layer 20 includes at least two layers of stress dielectric layers, the stress dielectric layer of the compressive stress dielectric layer 20 is a combination of silicon nitride, silicon oxide or silicon oxynitride, and is specifically selected according to implementation requirements. The whole thickness of the compressive stress dielectric layer 20 is 50nm to 1000nm, and the stress value ranges from-0.1 GPa to-5 GPa ("-" represents compressive stress).
The tensile stress medium layer 21 comprises a stress medium layer (namely a single-layer film structure); alternatively, the tensile stressor dielectric layer 21 includes at least two stressor dielectric layers (i.e., a multilayer film structure), such as a first tensile stressor dielectric sublayer 211, a second tensile stressor dielectric sublayer 212, and the like, and the stress values of adjacent stressor dielectric layers are different. When the tensile stress dielectric layer 21 is implemented as two or more stress dielectric layers, in particular, when the stress value of the stress dielectric layer facing the AlGaN barrier layer 12 is the lowest and is a low stress dielectric layer (for example, the stress value ranges from-250 MPa to 150MPa, that is, in the compressive stress dielectric layer 20, the compressive stress formed by the low stress dielectric layer is smaller than that of the adjacent stress dielectric layer or the unstressed dielectric layer), or, in the tensile stress dielectric layer 21, the tensile stress formed by the low stress dielectric layer is smaller than that of the adjacent stress dielectric layer) or the unstressed dielectric layer, the tensile stress dielectric layer can be used as a passivation layer to protect the surface of the AlGaN barrier layer 12.
In this embodiment, the stress medium of the tensile stress medium layer 21 is one or a combination of several of silicon nitride (such as SiN), silicon oxide (SiO) or silicon oxynitride (SiON), that is, when the tensile stress medium layer 21 is implemented as a single-layer structure and the tensile stress medium layer 21 includes a stress medium layer, the stress medium of the tensile stress medium layer 21 is one of silicon nitride, silicon oxide or silicon oxynitride; when the tensile stress dielectric layer 21 is implemented as a multilayer structure, and the tensile stress dielectric layer 21 includes at least two layers of stress dielectric layers, the stress dielectric of the tensile stress dielectric layer 21 is a combination of silicon nitride, silicon oxide or silicon oxynitride, and is specifically selected according to implementation requirements. The whole thickness of the tensile stress dielectric layer 21 is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
As shown in fig. 3, when the compressive stress medium layer 20 and the tensile stress medium layer 21 are implemented as a structure in which the compressive stress medium layer 20 having a three-layer structure is combined with the tensile stress medium layer 21 having a three-layer structure, that is, the compressive stress medium layer 20 includes a first compressive stress medium sublayer 201, a second compressive stress medium sublayer 202, and a third compressive stress medium sublayer 203, and the stress values of adjacent stress medium layers are different; the tensile stress medium layer 21 includes a first tensile stress medium sublayer 211, a second tensile stress medium sublayer 212, and a third tensile stress medium sublayer 213, and the stress values of adjacent stress medium layers are different. In this embodiment, when the compressive stress dielectric layer 20 and the tensile stress dielectric layer 21 face one of the stress dielectric layers of the AlGaN barrier layer 12, that is, the third compressive stress dielectric sublayer 203 and the third tensile stress dielectric sublayer 213 which are closest to the AlGaN barrier layer 12, the stress values are all zero.
As shown in fig. 4, a gate metal 16 is formed on P-type nitride gate layer 13 in a corresponding opening of P-type nitride gate layer 13.
In this embodiment, the ratio of the widths X: Y of the compressive stress dielectric layer and the tensile stress dielectric layer between the P-type nitride gate layer 13 and the drain metal 15 is 0.1< X: Y < 10. Preferably, 0.5< X: Y <2 can be implemented.
Example 2
The invention also provides a preparation method of the nitride HEMT device with the combined passivation medium, which is used for preparing the nitride HEMT device (such as the nitride HEMT device recorded in the embodiment 1), and takes the preparation method of firstly preparing the compressive stress medium layer 20 and then preparing the tensile stress medium layer 21 as an example, and comprises the following steps:
1) selecting a proper nitride epitaxial structure, in the embodiment, the P-type nitride HEMT epitaxial structure comprises a substrate 10, a GaN buffer layer 11, a channel layer and an AlGaN barrier layer 12. The thickness of the AlGaN barrier layer 12 can be set to be 1nm to 50nm according to implementation requirements, the composition of Al is 1 percent to 100 percent, the thickness of the P-type nitride layer is 50nm to 300nm, and the doping concentration is 1017～1021cm-3In the meantime.
2) Selectively etching the P-type nitride layer to form a P-type nitride gate layer 13; in specific implementation, processes such as ICP etching and the like can be adopted. Wherein, the material of the P-type nitride layer is P-GaN, P-AlGaN, P-InGaN or P-InAlGaN.
3) Preparing source metal 14 and drain metal 15 on the surface of the AlGaN barrier layer 12; in specific implementation, the metal system can be prepared by evaporation, sputtering or the like, and the metal system can include Ti, Al, Ni, Au, Ta or the like, and an alloy containing the metal system or a compound of the metal system.
4) Depositing a compressive stress dielectric layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the compressive stress dielectric layer 20 covers the gate region, the source region and the drain region; and selectively removing the compressive stress dielectric layer 20 covering the drain region by etching or other removal methods. Wherein, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the compressive stress dielectric layer 20 is 50nm to 1000nm, and the stress value ranges from-0.1 GPa to-5 GPa ("-" represents compressive stress).
5) Depositing a tensile stress dielectric layer 21 on the surface (whole surface) of the nitride epitaxial structure, wherein the tensile stress dielectric layer 21 covers the compressive stress dielectric layer 20 and the drain region; and selectively removing the tensile stress dielectric layer 21 covering the compressive stress dielectric layer 20 by etching or other removal methods, namely removing the tensile stress dielectric layer 21 in the range of the source region and the gate region. Wherein, the stress medium of the tensile stress medium layer 21 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress dielectric layer 21 is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
Further, step 6) is performed to form a hole in the compressive stress dielectric layer 20 covering the P-type nitride gate layer 13, and a gate metal 16 is formed on the P-type nitride gate layer 13 in a corresponding hole in the P-type nitride gate layer 13.
The compressive stress medium layer 20 and the tensile stress medium layer 21 may be implemented as a single-layer structure or a multi-layer structure; furthermore, the compressive stress medium layer 20 with a single-layer structure may be combined with the tensile stress medium layer 21 with a multi-layer structure, the compressive stress medium layer 20 with a multi-layer structure may be combined with the tensile stress medium layer 21 with a single-layer structure, or the compressive stress medium layer 20 with a multi-layer structure may be combined with the tensile stress medium layer 21 with a multi-layer structure.
When the compressive stress medium layer 20 includes at least two stress medium layers, the stress medium layers of the compressive stress medium layer 20 are sequentially deposited layer by layer in step 4).
When the tensile stress medium layer 21 comprises at least two stress medium layers, the stress medium layers of the tensile stress medium layer 21 are sequentially deposited layer by layer in step 5).
Example 3
The difference between this embodiment and embodiment 2 is that a tensile stress dielectric layer 21 is prepared first, and then a compressive stress dielectric layer 20 is prepared, specifically the differences are as follows:
in the step 4), firstly, depositing a tensile stress dielectric layer 21 on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer 21 covers the gate region, the source region and the drain region; removing the tensile stress dielectric layer 21 covering the gate region and the source region;
in the step 5), a compressive stress dielectric layer 20 is deposited on the surface of the nitride epitaxial structure, and the compressive stress dielectric layer 20 covers the tensile stress dielectric layer 21, the gate region and the source region; and then removing the compressive stress dielectric layer 20 covering the tensile stress dielectric layer 21.
When the compressive stress medium layer 20 comprises at least two stress medium layers, the stress medium layers of the tensile stress medium layer 21 are sequentially deposited layer by layer in step 4).
When the tensile stress medium layer 21 comprises at least two stress medium layers, the stress medium layers of the compressive stress medium layer 20 are sequentially deposited layer by layer in step 5).
Example 4
The difference between this embodiment and embodiments 2 and 3 is that the preparation processes of the compressive stress dielectric layer 20 and the tensile stress dielectric layer 21 are different, in this embodiment, by using the stress characteristic of the stress-converted dielectric, the entire compressive stress dielectric layer 20 is deposited first, then the compressive stress dielectric layer 20 is converted into the tensile stress dielectric layer 21 by high temperature annealing, and then the compressive stress dielectric layer 20 is deposited, so as to obtain the combination of the compressive stress dielectric layer 20 and the tensile stress dielectric layer 21 in different regions.
Specifically, the method for manufacturing a nitride HEMT device with a combined passivation dielectric according to this embodiment includes the following steps:
1) selecting a proper nitride epitaxial structure, in the embodiment, the P-type nitride HEMT epitaxial structure comprises a substrate 10, a GaN buffer layer 11, a channel layer, an AlGaN barrier layer 12 and a P-type nitride layer, wherein the thickness of the AlGaN barrier layer 12 can be set to be 1nm to 50nm according to implementation requirements, the Al component is 1% to 100%, the thickness of the P-type nitride layer is 50nm to 300nm, and the doping concentration is 10 nm17～1021cm-3In the meantime.
2) Selectively etching the P-type nitride layer to form a P-type nitride gate layer 13; in specific implementation, processes such as ICP etching and the like can be adopted. Wherein, the material of the P-type nitride layer is P-GaN, P-AlGaN, P-InGaN or P-InAlGaN.
3) Preparing source metal 14 and drain metal 15 on the surface of the AlGaN barrier layer 12; in specific implementation, the metal system can be prepared by evaporation, sputtering or the like, and the metal system can include Ti, Al, Ni, Au, Ta or the like, and an alloy containing the metal system or a compound of the metal system.
4) And depositing a compressive stress dielectric layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the compressive stress dielectric layer 20 covers the gate region, the source region and the drain region.
5) Performing high-temperature annealing to convert the compressive stress dielectric layer 20 into a tensile stress dielectric layer 21; in the specific implementation, the annealing temperature is 700-1000 ℃, and the annealing time is 1-5 h. Wherein, the stress medium of the tensile stress medium layer 21 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress dielectric layer 21 is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
6) And selectively removing the tensile stress dielectric layer 21 covering the gate region and the source region by etching or other removal methods.
7) And depositing a compressive stress dielectric layer 20 on the surface (whole surface) of the nitride epitaxial structure, wherein the compressive stress dielectric layer 20 covers the gate region, the source region and the tensile stress dielectric layer 21. Wherein, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the compressive stress dielectric layer 20 is 50nm to 1000nm, and the stress value ranges from-0.1 GPa to-5 GPa ("-" represents compressive stress).
8) And selectively removing the compressive stress dielectric layer 20 covering the tensile stress dielectric layer 21 by etching or other removal methods.
When the compressive stress dielectric layer 20 comprises at least two stress dielectric layers, the stress values of the adjacent stress dielectric layers are different; the tensile stress medium layer 21 comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different; then in step 4) and step 7), the stress dielectric layers of the compressive stress dielectric layer 20 are deposited in sequence.
The other portions are the same as in example 2.
Example 5
The difference between this embodiment and embodiment 4 is that a tensile stress dielectric layer 21 is deposited, the tensile stress dielectric layer 21 is converted into a compressive stress dielectric layer 20, and then the tensile stress dielectric layer 21 is deposited, so as to obtain the combination of the compressive stress dielectric layer 20 and the tensile stress dielectric layer 21 in different regions. The specific differences are as follows:
in the step 4), a tensile stress dielectric layer 21 is deposited on the surface (whole surface) of the nitride epitaxial structure, and the tensile stress dielectric layer 21 covers the gate region, the source region and the drain region.
In step 5), high-temperature annealing is performed to convert the tensile stress dielectric layer 21 into the compressive stress dielectric layer 20. Wherein, the stress medium of the compressive stress medium layer 20 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the compressive stress dielectric layer 20 is 50nm to 1000nm, and the stress value ranges from-0.1 GPa to-5 GPa ("-" represents compressive stress).
6) And selectively removing the compressive stress dielectric layer 20 covering the drain region by etching or other removal methods.
7) And depositing a tensile stress medium layer 21 on the surface (whole surface) of the nitride epitaxial structure, wherein the tensile stress medium layer 21 covers the drain region and the compressive stress medium layer 20. Wherein, the stress medium of the tensile stress medium layer 21 is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride; the whole thickness of the tensile stress dielectric layer 21 is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
8) And selectively removing the tensile stress medium layer 21 covering the compressive stress medium layer 20 by etching or other removal methods.
When the compressive stress dielectric layer 20 comprises at least two stress dielectric layers, the stress values of the adjacent stress dielectric layers are different; the tensile stress medium layer 21 comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different; then in step 4) and step 7), the stress dielectric layers of the tensile stress dielectric layer 21 are deposited in sequence.
The other portions are the same as in example 4.
The above examples are provided only for illustrating the present invention and are not intended to limit the present invention. Changes, modifications, etc. to the above-described embodiments are intended to fall within the scope of the claims of the present invention as long as they are in accordance with the technical spirit of the present invention.
Claims (13)
1. A nitride HEMT device is characterized by comprising a substrate, a buffer layer, a channel layer, a barrier layer, a P-type nitride gate layer, source metal and drain metal; a gate metal is arranged on the P-type nitride gate layer, the P-type nitride gate layer and a certain range of area around the P-type nitride gate layer are defined as a gate area, the source metal and a certain range of area around the source metal are defined as a source area, and the drain metal and a certain range of area around the drain metal are defined as a drain area; the grid electrode area and the source electrode area are covered with a compressive stress dielectric layer, and the drain electrode area is covered with a tensile stress dielectric layer; the ratio of the width X to the width Y of the compressive stress dielectric layer to the width Y of the tensile stress dielectric layer between the P-type nitride gate layer and the drain metal is 0.1< X to Y < 10.
2. The nitride HEMT device of claim 1, wherein the ratio of the width X: Y of the compressively stressed dielectric layer to the tensile stressed dielectric layer between the P-type nitride gate layer to the drain metal is 0.5< X: Y < 2.
3. The nitride HEMT device of claim 1, wherein the compressive stress dielectric layer comprises a stress dielectric layer; or the compressive stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different; the thickness of the compressive stress dielectric layer is 50 nm-1000 nm, and the stress value range is-0.1 GPa-5 GPa;
the tensile stress medium layer comprises a stress medium layer; or the tensile stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different; the thickness of the tensile stress dielectric layer is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
4. The nitride HEMT device according to any one of claims 1 to 3, wherein the stress medium of the compressive stress medium layer is one or a combination of silicon nitride, silicon oxide or silicon oxynitride, and the stress medium of the tensile stress medium layer is one or a combination of silicon nitride, silicon oxide or silicon oxynitride.
5. A preparation method of a nitride HEMT device is characterized by comprising the following steps:
1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; selectively etching the P-type nitride layer to form a P-type nitride gate layer; preparing source metal and drain metal on the surface of the barrier layer; the P-type nitride gate layer and a region in a certain range around the P-type nitride gate layer are defined as a gate region, the source metal and a region in a certain range around the source metal are defined as a source region, and the drain metal and a region in a certain range around the drain metal are defined as a drain region;
2) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the gate region, the source region and the drain region;
or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the gate region, the source region and the drain region;
3) removing the compressive stress medium layer covering the drain region;
or removing the tensile stress dielectric layer covering the gate region and the source region;
4) depositing a tensile stress medium layer on the surface of the nitride epitaxial structure, wherein the tensile stress medium layer covers the compressive stress medium layer and the drain region;
or depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the tensile stress dielectric layer, the gate region and the source region;
the thickness of the compressive stress dielectric layer is 50 nm-1000 nm, and the stress value range is-0.1 GPa-5 GPa;
the thickness of the tensile stress dielectric layer is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
6. The method for manufacturing a nitride HEMT device according to claim 5, further comprising the step of 5) removing the tensile stress dielectric layer covering the compressive stress dielectric layer;
or removing the compressive stress dielectric layer covering the tensile stress dielectric layer.
7. The method of fabricating a nitride HEMT device according to claim 5, wherein the compressive stress dielectric layer comprises a stress dielectric layer; or the compressive stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the compressive stress medium layer comprises at least two stress medium layers, the stress medium layers of the compressive stress medium layer are sequentially deposited layer by layer in the step 2) or the step 4);
the tensile stress medium layer comprises a stress medium layer; or the tensile stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the tensile stress medium layer comprises at least two stress medium layers, the stress medium layers of the tensile stress medium layer are sequentially deposited layer by layer in the step 2) or the step 4).
8. The method for manufacturing a nitride HEMT device according to any one of claims 5 to 7, wherein the stress medium of the compressive stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the stress medium of the tensile stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride.
9. A preparation method of a nitride HEMT device is characterized by comprising the following steps:
1) preparing a nitride epitaxial structure on a substrate, wherein the nitride epitaxial structure comprises a buffer layer, a channel layer, a barrier layer and a P-type nitride layer; selectively etching the P-type nitride layer to form a P-type nitride gate layer; preparing source metal and drain metal on the surface of the barrier layer; the P-type nitride gate layer and a region in a certain range around the P-type nitride gate layer are defined as a gate region, the source metal and a region in a certain range around the source metal are defined as a source region, and the drain metal and a region in a certain range around the drain metal are defined as a drain region;
2) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the gate region, the source region and the drain region;
or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the gate region, the source region and the drain region;
3) performing high-temperature annealing to convert the compressive stress dielectric layer into a tensile stress dielectric layer;
or, carrying out high-temperature annealing to convert the tensile stress dielectric layer into a compressive stress dielectric layer;
4) removing the tensile stress dielectric layer covering the gate region and the source region;
or removing the compressive stress dielectric layer covering the drain region;
5) depositing a compressive stress dielectric layer on the surface of the nitride epitaxial structure, wherein the compressive stress dielectric layer covers the gate region, the source region and the tensile stress dielectric layer;
or depositing a tensile stress dielectric layer on the surface of the nitride epitaxial structure, wherein the tensile stress dielectric layer covers the drain region and the compressive stress dielectric layer;
the thickness of the compressive stress dielectric layer is 50 nm-1000 nm, and the stress value range is-0.1 GPa-5 GPa;
the thickness of the tensile stress dielectric layer is 50 nm-1000 nm, and the stress value range is 0.1 GPa-2 GPa.
10. The method for manufacturing a nitride HEMT device according to claim 9, further comprising the step 6) of removing the compressive stress dielectric layer covering the tensile stress dielectric layer;
or removing the tensile stress medium layer covering the compressive stress medium layer.
11. The method for preparing a nitride HEMT device according to claim 9, wherein in the step 3), the annealing temperature is 700-1000 ℃ and the annealing time is 1-5 hours.
12. The method of fabricating a nitride HEMT device according to claim 9, wherein the compressive stress dielectric layer comprises a stress dielectric layer; or the compressive stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the compressive stress medium layer comprises at least two stress medium layers, the stress medium layers of the compressive stress medium layer are sequentially deposited layer by layer in the step 5);
the tensile stress medium layer comprises a stress medium layer; or the tensile stress medium layer comprises at least two stress medium layers, and the stress values of the adjacent stress medium layers are different;
when the tensile stress medium layer comprises at least two stress medium layers, the stress medium layers of the tensile stress medium layer are sequentially deposited layer by layer in the step 5).
13. The method for manufacturing a nitride HEMT device according to any one of claims 9 to 12, wherein the stress medium of the compressive stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride, and the stress medium of the tensile stress medium layer is one or a combination of several of silicon nitride, silicon oxide or silicon oxynitride.
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