CN114121981A - Three-dimensional memory and forming method thereof - Google Patents
Three-dimensional memory and forming method thereof Download PDFInfo
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- CN114121981A CN114121981A CN202111394532.4A CN202111394532A CN114121981A CN 114121981 A CN114121981 A CN 114121981A CN 202111394532 A CN202111394532 A CN 202111394532A CN 114121981 A CN114121981 A CN 114121981A
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
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- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H—ELECTRICITY
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
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Abstract
The invention relates to a three-dimensional memory and a forming method thereof. The method for forming the three-dimensional memory comprises the following steps: providing a substrate; forming a first sacrificial layer including a first etching pattern on the substrate; backfilling the first etching pattern to form a second sacrificial layer comprising a second etching pattern on the first sacrificial layer, wherein the projection of the first etching pattern is intersected with the projection of the second etching pattern along the direction vertical to the substrate; etching the first sacrificial layer along the second etching pattern to form a third etching pattern communicated with the first etching pattern; and etching the substrate along the first etching pattern and the third etching pattern to form a combined pattern in the substrate. The invention improves the appearance of the finally formed combined pattern.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a three-dimensional memory and a forming method thereof.
Background
With the development of the planar flash memory, the manufacturing process of the semiconductor has been greatly improved. In recent years, however, the development of planar flash memories has met with various challenges: physical limits, existing development technology limits, and storage electron density limits, among others. In this context, to solve the difficulties encountered by flat flash memories and to pursue lower production costs of unit memory cells, various three-dimensional (3D) flash memory structures, such as 3D NOR (3D NOR) flash memory and 3D NAND (3D NAND) flash memory, have come into force.
The 3D NAND memory is based on the small volume and the large capacity, the design concept of the three-dimensional mode layer-by-layer stacking height integration of the storage units is adopted, the memory with high unit area storage density and high-efficiency storage unit performance is produced, and the mainstream process of the design and production of the emerging memory is formed. However, the current three-dimensional memory has a drawback in forming a complicated pattern, thereby limiting the improvement of the performance of the three-dimensional memory.
Therefore, how to improve the performance of the three-dimensional memory is a technical problem to be solved urgently at present.
Disclosure of Invention
The invention provides a three-dimensional memory and a forming method thereof, which are used for solving the problem that complex patterns cannot be formed in the prior art so as to improve the performance of the three-dimensional memory.
In order to solve the above problems, the present invention provides a method for forming a three-dimensional memory, comprising the steps of:
providing a substrate;
forming a first sacrificial layer including a first etching pattern on the substrate;
backfilling the first etching pattern to form a second sacrificial layer comprising a second etching pattern on the first sacrificial layer, wherein the projection of the first etching pattern is intersected with the projection of the second etching pattern along the direction vertical to the substrate;
etching the first sacrificial layer along the second etching pattern to form a third etching pattern communicated with the first etching pattern;
and etching the substrate along the first etching pattern and the third etching pattern to form a combined pattern in the substrate.
Optionally, before forming the first sacrificial layer including the first etching pattern on the substrate, the method further includes the following steps:
and forming a mask layer on the surface of the substrate.
Optionally, the specific step of forming the first sacrificial layer including the first etching pattern on the substrate includes:
forming a first sacrificial layer on the surface of the mask layer;
and etching the first sacrificial layer to form a first etching pattern penetrating through the first sacrificial layer, wherein the cross section of the first etching pattern comprises a first connecting pattern and a first convex pattern at least connected to one side end of the first connecting pattern in a direction parallel to the top surface of the substrate.
Optionally, the first connecting pattern is a rectangular pattern, and the first convex pattern is a circular or elliptical pattern.
Optionally, the number of the first convex patterns is two, and the two first convex patterns are connected to two opposite ends of the first connecting pattern.
Optionally, the step of backfilling the first etching pattern to form a second sacrificial layer including a second etching pattern on the first sacrificial layer includes:
forming a second sacrificial layer which is filled with the first etching pattern and covers the first sacrificial layer;
and etching the second sacrificial layer to form the second etching pattern penetrating through the second sacrificial layer.
Optionally, the second etched pattern includes a second connection pattern and a second protrusion pattern connected to at least one side end of the second connection pattern.
Optionally, the second connection pattern is a rectangular pattern, and the second externally-convex pattern is a circular or elliptical pattern.
Optionally, the number of the second convex patterns is two, and the two second convex patterns are connected to opposite end portions of the second connection pattern.
Optionally, in a direction perpendicular to the substrate, an included angle between a projection of the first etching pattern and a projection of the second etching pattern is less than or equal to 90 degrees.
Optionally, the specific step of etching the first sacrificial layer along the second etching pattern to form a third etching pattern communicated with the first etching pattern includes:
etching the first sacrificial layer along the second etching pattern to form a third etching pattern penetrating the first sacrificial layer, the third etching pattern including a third connection pattern intersecting and communicating with the first connection pattern and a third protruded pattern connected to at least one side end of the third connection pattern;
and removing the second sacrificial layer.
Optionally, the base includes a substrate and a stacked layer on the substrate; etching the substrate along the first etching pattern and the third etching pattern, wherein the specific step of forming a combined pattern in the substrate comprises:
etching the mask layer along the first etching pattern and the third etching pattern to form a combined etching pattern penetrating through the mask layer;
and etching the stacked layer along the combined etching pattern to form a combined pattern penetrating through the stacked layer.
Optionally, a cross section of the combined pattern in a direction parallel to the surface of the substrate is a petal shape including a plurality of convex portions, and an included angle at an intersection position of two adjacent convex portions is smaller than or equal to 90 degrees.
In order to solve the above problem, the present invention also provides a three-dimensional memory, including:
a substrate;
the combined pattern is positioned in the substrate, the cross section of the combined pattern is in a petal shape comprising a plurality of convex parts in the direction parallel to the surface of the substrate, and the included angle of the intersection positions of two adjacent convex parts is smaller than or equal to 90 degrees.
Optionally, the substrate comprises a stack of layers;
the combined pattern is a channel hole penetrating through the stacked layers.
Optionally, the number of the convex portions is 4, and the 4 convex portions are distributed in central symmetry.
Optionally, the shapes of the plurality of outward protrusions are the same; alternatively, the first and second electrodes may be,
at least two of the outward protrusions have different shapes.
According to the three-dimensional memory and the forming method thereof provided by the invention, the finally formed combined pattern is split into the plurality of parts, and the plurality of parts are formed on different film layers in different process steps and then combined, so that the forming difficulty of the combined pattern is reduced, the appearance of the finally formed combined pattern is improved, the formation of the complex pattern in the semiconductor structure is realized, the appearance consistency of the finally formed plurality of combined patterns is ensured, and the performance of the three-dimensional memory is improved.
Drawings
FIG. 1 is a flow chart of a method for forming a three-dimensional memory according to an embodiment of the present invention;
FIGS. 2A-2J are schematic diagrams of the main process structures in the process of forming a three-dimensional memory according to an embodiment of the present invention;
FIG. 3 is a schematic top view of a composite pattern according to an embodiment of the present invention;
FIG. 4 is a schematic illustration of the splitting of a composite pattern in an embodiment of the present invention;
FIG. 5 is a schematic diagram of a three-dimensional memory according to an embodiment of the present invention.
Detailed Description
The following describes in detail a specific embodiment of a three-dimensional memory and a method for forming the same according to the present invention with reference to the accompanying drawings.
Due to the limitation of optical limit resolution and graph size, when a complex pattern comprising a plurality of sub-patterns is formed on a photoresist layer, the boundaries between two adjacent sub-patterns are easily connected together, for example, when a petal-shaped pattern is formed, the edges of two adjacent petals are connected together, so that the angle between two adjacent petals is larger than 90 degrees (namely an obtuse angle), when the complex pattern in the photoresist layer is transferred downwards onto a wafer by adopting photoetching and etching processes, the pattern formed on the wafer is basically an approximate rectangular pattern with fuzzy boundaries, and has larger deviation with the preset shape of the complex pattern, so that the complex pattern cannot be realized on the wafer, and the improvement of the performance of a three-dimensional memory is limited. Meanwhile, since a pattern difference due to limitations of optical limit resolution and a pattern size is uncertain, uniformity among a plurality of complex patterns formed on a wafer is poor, thereby resulting in poor performance stability of a three-dimensional memory.
Fig. 1 is a flow chart of a method for forming a three-dimensional memory according to an embodiment of the present invention, and fig. 2A to 2J are schematic diagrams of main process structures in a process for forming a three-dimensional memory according to an embodiment of the present invention. The three-dimensional memory described in this detailed description may be, but is not limited to, a 3D NAND memory. As shown in fig. 1 and fig. 2A to 2J, the method for forming the three-dimensional memory includes the following steps:
in step S11, the substrate 20 is provided.
Specifically, the base 20 may include only a substrate, or may include a substrate and several semiconductor layers on the substrate. The substrate may be a Si substrate, a Ge substrate, a SiGe substrate, an SOI (Silicon On Insulator) substrate, a GOI (Germanium On Insulator) substrate, or the like.
Step S12, forming a first sacrificial layer 22 including a first etching pattern 221 on the substrate 20, as shown in fig. 2B.
Optionally, before forming the first sacrificial layer 22 including the first etching pattern 221 on the substrate 20, the method further includes the following steps:
a mask layer 21 is formed on the surface of the substrate 20.
Optionally, the specific step of forming the first sacrificial layer 22 including the first etching pattern 221 on the substrate 20 includes:
forming a first sacrificial layer 22 on the surface of the mask layer 21;
the first sacrificial layer 22 is etched to form a first etching pattern 221 penetrating the first sacrificial layer 22, and a cross-section of the first etching pattern 221 includes a first connection pattern 2211 and a first protruded pattern 2212 connected to at least one side end portion of the first connection pattern 2211 in a direction parallel to the top surface of the substrate 20, as shown in fig. 2C.
Specifically, the mask layer 21 is formed on the surface of the substrate 20 before the first sacrificial layer 22 is deposited on the substrate 20, so as to ensure the morphology of the pattern finally transferred into the substrate 20 and avoid damage to the substrate 20 during the patterning of the first sacrificial layer 22. The mask layer 21 may also be an organic mask layer (e.g., a carbon mask layer) or a hard mask layer (e.g., a silicon nitride mask layer). Thereafter, a first sacrificial layer 22 is deposited on the surface of the mask layer 21, and a patterned first photoresist layer 23 is deposited on the surface of the first sacrificial layer 22 away from the substrate 20, as shown in fig. 2A. The first photoresist layer 23 has a first window 231 penetrating the first photoresist layer 23 along a direction perpendicular to the top surface of the substrate 20 (i.e., the surface of the substrate 20 facing the first sacrificial layer 22). The first sacrificial layer 22 is etched downwards along the first window 231, the first etching pattern 221 penetrating the first sacrificial layer 22 along the direction perpendicular to the top surface of the substrate 20 is formed in the first sacrificial layer 22, and after the first photoresist layer 23 is removed, the structure shown in fig. 2B is obtained.
Alternatively, the first connection patterns 2211 are rectangular patterns, and the first convex patterns 2212 are circular or elliptical patterns.
The first protruded patterns 2212 in this embodiment refer to patterns protruded in a direction parallel to the center-directed edge of the first connection patterns 2211.
Alternatively, the number of the first convex patterns 2212 is two, and two first convex patterns 2212 are connected to opposite ends of the first connection pattern 2211.
Fig. 2C is a schematic top view of the first etching pattern, and fig. 2B is a schematic cross-sectional view of fig. 2C along line AB. Fig. 3 is a schematic top view of a combined pattern according to an embodiment of the present invention, and fig. 4 is a schematic diagram of splitting the combined pattern according to the embodiment of the present invention. For example, the first etching pattern may be set according to the shape of a combined pattern to be finally formed. When the cross-sectional shape of the finally-formed combined pattern 27 in the direction parallel to the top surface of the substrate 20 is the petal-shaped shape as shown in fig. 3, the combined pattern 27 may be split in the manner as shown in fig. 4, and the combined pattern 27 in one petal-shaped shape is split into the first etching pattern 221 in one dumbbell shape and the second etching pattern 241 in one dumbbell shape, where the first etching pattern 221 in one dumbbell shape and the second etching pattern 241 in one dumbbell shape have different inclination directions.
The above splitting is merely illustrative. In other specific embodiments, a person skilled in the art may split the combined pattern according to actual needs, for example, the combined pattern 27 in a petal shape may be split into four etched patterns, each etched pattern includes a circular pattern and a rectangular pattern connected to the circular pattern. In the process of splitting the combined pattern, the split etching patterns can be the same or different from each other, and a person skilled in the art selects the combined pattern according to the actual etching precision requirement. The plurality of the present embodiment means two or more.
Step S13, backfilling the first etching pattern 221, and forming a second sacrificial layer 24 including a second etching pattern 241 on the first sacrificial layer 22, as shown in fig. 2E, wherein a projection of the first etching pattern 221 intersects a projection of the second etching pattern 241 along a direction perpendicular to the substrate 20.
Optionally, the step of backfilling the first etching pattern 221 to form the second sacrificial layer 24 including the second etching pattern 241 on the first sacrificial layer 22 includes:
forming a second sacrificial layer 24 which fills the first etching pattern 221 and covers the first sacrificial layer 22;
the second sacrificial layer 24 is etched to form the second etching pattern 241 penetrating the second sacrificial layer 24.
Optionally, the second etched pattern 241 includes a second connection pattern 2411 and a second protrusion pattern 2412 connected to at least one side end of the second connection pattern 2411.
Optionally, the second connection pattern 2411 is a rectangular pattern, and the second convex pattern 2412 is a circular or elliptical pattern.
Optionally, the number of the second protrusion patterns 2412 is two, and the two second protrusion patterns 2412 are connected to opposite end portions of the second connection pattern 2412.
Fig. 2F is a schematic top view of the first etching pattern, and fig. 2E is a schematic cross-sectional view of fig. 2F along the CD line. Specifically, after the first etching pattern 221 is formed, the second sacrificial layer 24 is formed to fill the first etching pattern 221 and cover the first sacrificial layer 22, and the patterned second photoresist layer 25 is formed to cover the second sacrificial layer 24, as shown in fig. 2D. The second photoresist layer 25 has a second window 251 extending through the second photoresist layer 25 in a direction perpendicular to the top surface of the substrate 20. The second sacrificial layer 24 is etched down along the second window 251 to form the second etching pattern 241 penetrating the second sacrificial layer 24 in a direction perpendicular to the top surface of the substrate 20. The second etched pattern 241 has a dumbbell shape in cross section, and includes the second connection pattern 2411 having a rectangular shape and the second protrusion pattern 2412 having a circular or elliptical shape. The second protrusion pattern 2412 refers to a pattern protruding in a direction parallel to a center-directed edge of the second connection pattern 2411.
When the first etching pattern 221 and the second etching pattern 241 are both dumbbell-shaped patterns, the intersection of the projection of the first etching pattern 221 and the projection of the second etching pattern 241 means that the projection of the first connection pattern 2211 in the first etching pattern 221 intersects the projection of the second connection pattern 2411 in the second etching pattern 241.
Optionally, in a direction perpendicular to the substrate 20, an included angle between a projection of the first etching pattern 221 and a projection of the second etching pattern 241 is smaller than or equal to 90 degrees.
For example, an angle of an intersection position of a projection of the first connection pattern 2211 in the first etch pattern 221 and a projection of the second connection pattern 2411 in the second etch pattern 241 is less than or equal to 90 degrees.
Step S14, etching the first sacrificial layer 22 along the second etching pattern 241 to form a third etching pattern 222 communicating with the first etching pattern 221, as shown in fig. 2G.
Optionally, the specific step of etching the first sacrificial layer 22 along the second etching pattern 241 to form a third etching pattern 222 communicated with the first etching pattern 221 includes:
etching the first sacrificial layer 22 along the second etching pattern 241 to form a third etching pattern 222 penetrating the first sacrificial layer 22, the third etching pattern 222 including a third connection pattern intersecting and communicating with the first connection pattern and a third outer convex pattern connected to at least one side end of the third connection pattern;
the second sacrificial layer 24 is removed.
Fig. 2H is a schematic top view of an initial combined etch pattern including the first etch pattern 221 and the third etch pattern 222 in the first sacrificial layer 22, and fig. 2G is a schematic cross-sectional view of fig. 2H along an EF line direction. Since the second etching pattern 241 is formed in the second sacrificial layer 24 and then the second etching pattern 241 is transferred downwards into the first sacrificial layer 22 to combine with the first etching pattern 221 in the first sacrificial layer 22 to form the initial combined etching pattern, the influence of the optical limit resolution and the pattern size on the morphology of the initial combined etching pattern to be formed can be reduced or even avoided, so that the included angle γ between the intersection positions of the first etching pattern 221 and the third etching pattern 222 in the initial combined etching pattern (i.e. the included angle between the intersection position of the projection of the first etching pattern 221 in the direction perpendicular to the substrate 20 and the projection of the second etching pattern 241 in the direction perpendicular to the substrate 20) is smaller than or equal to 90 degrees.
Step S15, etching the substrate 20 along the first etching pattern 221 and the third etching pattern 222, and forming a combined pattern 27 in the substrate 20, as shown in fig. 2J and fig. 3, where fig. 2J is a schematic cross-sectional view of fig. 3 along the GH line direction.
Optionally, the base 20 includes a substrate and a stack layer on the substrate; etching the substrate along the first etching pattern 221 and the third etching pattern 222, wherein the specific steps of forming the combined pattern 27 in the substrate 20 include:
etching the mask layer 21 along the first etch pattern 221 and the third etch pattern 222 to form a combined etch pattern penetrating the mask layer 21;
and etching the stacked layer along the combined etching pattern to form a combined pattern penetrating through the stacked layer.
Specifically, the stacked layers may include third sacrificial layers and interlayer insulating layers that are alternately stacked in a direction perpendicular to the substrate toward the stacked layers. And etching the stacked layer downwards along the combined etching pattern in the mask layer 21 to form the combined pattern 27 penetrating through the stacked layer, and taking the combined pattern 27 as a channel hole in the stacked layer.
Optionally, a cross section of the combined pattern 27 in a direction parallel to the surface of the substrate 20 is a petal shape including a plurality of convex portions, and an included angle at a position where two adjacent convex portions intersect is smaller than or equal to 90 degrees.
For example, as shown in fig. 3, the combined pattern 27 includes a first convex portion 271 and a second convex portion 272 adjacent to the first convex portion 271, and an included angle δ between an edge of the first convex portion 271 and an edge of the second convex portion 272 (i.e., an included angle at a position where the first convex portion 271 and the second convex portion 272 intersect) is less than or equal to 90 degrees.
In the present embodiment, the combination pattern 27 includes four convex portions as an example, and a person skilled in the art may set the number of the convex portions according to actual needs, for example, two, three, or five or more. All the convex portions in the combined pattern 27 in the present embodiment have the same shape and size. In other embodiments, the shape and/or size of the convex portions in the combined pattern 27 may be different.
Moreover, the present embodiment further provides a three-dimensional memory. FIG. 5 is a schematic diagram of a three-dimensional memory according to an embodiment of the present invention. The three-dimensional memory provided by the present embodiment can be formed by using the formation method of the three-dimensional memory shown in fig. 1, fig. 2A to fig. 2J, and fig. 3 to fig. 4. The three-dimensional memory described in this detailed description may be, but is not limited to, a 3D NAND memory. As shown in fig. 3 to 5, the three-dimensional memory includes:
a substrate 20;
the combined pattern 27 is positioned in the substrate 20, and the cross section of the combined pattern 27 is in a petal shape comprising a plurality of convex parts in a direction parallel to the surface of the substrate 20, and an included angle of the intersection position of two adjacent convex parts is smaller than or equal to 90 degrees.
Optionally, the substrate 20 comprises a stack of layers;
the combined pattern 27 is a channel hole penetrating the stacked layers.
Optionally, the number of the convex portions is 4, and the 4 convex portions are distributed in central symmetry.
In the present embodiment, a plurality of (for example, 4) convex portions are distributed in a central symmetry manner, so that the design operation of the mask plate can be simplified, and the manufacturing process of the three-dimensional memory can be simplified.
The present embodiment will be described by taking the example in which the number of the convex portions is 4. In other embodiments, the number of the convex portions may be any number, such as 3, 5, or 6 or more.
Optionally, the shapes of the plurality of outward protrusions are the same; alternatively, the first and second electrodes may be,
at least two of the outward protrusions have different shapes.
In the three-dimensional memory and the method for forming the same according to the present embodiment, the finally formed combined pattern is split into a plurality of portions, and the plurality of portions are formed on different film layers in different process steps and then combined, so that the difficulty in forming the combined pattern is reduced, the morphology of the finally formed combined pattern is improved, the formation of a complex pattern in a semiconductor structure is realized, the consistency of the morphology of the finally formed plurality of combined patterns is ensured, and the performance of the three-dimensional memory is improved.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (17)
1. A method for forming a three-dimensional memory is characterized by comprising the following steps:
providing a substrate;
forming a first sacrificial layer including a first etching pattern on the substrate;
backfilling the first etching pattern to form a second sacrificial layer comprising a second etching pattern on the first sacrificial layer, wherein the projection of the first etching pattern is intersected with the projection of the second etching pattern along the direction vertical to the substrate;
etching the first sacrificial layer along the second etching pattern to form a third etching pattern communicated with the first etching pattern;
and etching the substrate along the first etching pattern and the third etching pattern to form a combined pattern in the substrate.
2. The method of claim 1, wherein before forming the first sacrificial layer comprising the first etching pattern on the substrate, the method further comprises:
and forming a mask layer on the surface of the substrate.
3. The method of claim 2, wherein the step of forming a first sacrificial layer comprising a first etch pattern on the substrate comprises:
forming a first sacrificial layer on the surface of the mask layer;
and etching the first sacrificial layer to form a first etching pattern penetrating through the first sacrificial layer, wherein the cross section of the first etching pattern comprises a first connecting pattern and a first convex pattern at least connected to one side end of the first connecting pattern in a direction parallel to the top surface of the substrate.
4. The method of claim 3, wherein the first connection pattern is a rectangular pattern and the first convex pattern is a circular or elliptical pattern.
5. The method as claimed in claim 3, wherein the number of the first convex patterns is two, and the two first convex patterns are connected to opposite ends of the first connection pattern.
6. The method as claimed in claim 3, wherein the step of backfilling the first etching pattern and forming a second sacrificial layer comprising a second etching pattern on the first sacrificial layer comprises:
forming a second sacrificial layer which is filled with the first etching pattern and covers the first sacrificial layer;
and etching the second sacrificial layer to form the second etching pattern penetrating through the second sacrificial layer.
7. The method of claim 6, wherein the second etching pattern comprises a second connection pattern and a second protrusion pattern connected to at least one side end of the second connection pattern.
8. The method of claim 7, wherein the second connection pattern is a rectangular pattern, and the second convex pattern is a circular or elliptical pattern.
9. The method of claim 7, wherein the number of the second protrusion patterns is two, and the two second protrusion patterns are connected to opposite ends of the second connection pattern.
10. The method of claim 1, wherein an angle between a position where a projection of the first etching pattern intersects a projection of the second etching pattern in a direction perpendicular to the substrate is less than or equal to 90 degrees.
11. The method as claimed in claim 7, wherein the step of etching the first sacrificial layer along the second etching pattern to form a third etching pattern in communication with the first etching pattern comprises:
etching the first sacrificial layer along the second etching pattern to form a third etching pattern penetrating the first sacrificial layer, the third etching pattern including a third connection pattern intersecting and communicating with the first connection pattern and a third protruded pattern connected to at least one side end of the third connection pattern;
and removing the second sacrificial layer.
12. The method of claim 11, wherein the base comprises a substrate and a stack of layers on the substrate; etching the substrate along the first etching pattern and the third etching pattern, wherein the specific step of forming a combined pattern in the substrate comprises:
etching the mask layer along the first etching pattern and the third etching pattern to form a combined etching pattern penetrating through the mask layer;
and etching the stacked layer along the combined etching pattern to form a combined pattern penetrating through the stacked layer.
13. The method according to claim 1, wherein a cross section of the combined pattern in a direction parallel to the surface of the substrate has a petal shape including a plurality of convex portions, and an angle at which two adjacent convex portions intersect is less than or equal to 90 degrees.
14. A three-dimensional memory, comprising:
a substrate;
the combined pattern is positioned in the substrate, the cross section of the combined pattern is in a petal shape comprising a plurality of convex parts in the direction parallel to the surface of the substrate, and the included angle of the intersection positions of two adjacent convex parts is smaller than or equal to 90 degrees.
15. The three-dimensional memory according to claim 14, wherein the substrate comprises a stack of layers; the combined pattern is a channel hole penetrating through the stacked layers.
16. The three-dimensional memory according to claim 14, wherein the number of the convex portions is 4, and the 4 convex portions are distributed in a central symmetry manner.
17. The three-dimensional memory according to claim 14, wherein the plurality of the convex-outward portions are all the same shape; alternatively, the first and second electrodes may be,
at least two of the outward protrusions have different shapes.
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