CN114121775A - Method for manufacturing semiconductor device containing deep trench structure - Google Patents
Method for manufacturing semiconductor device containing deep trench structure Download PDFInfo
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- CN114121775A CN114121775A CN202111413916.6A CN202111413916A CN114121775A CN 114121775 A CN114121775 A CN 114121775A CN 202111413916 A CN202111413916 A CN 202111413916A CN 114121775 A CN114121775 A CN 114121775A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
Abstract
The application discloses a manufacturing method of a semiconductor device containing a deep trench structure, which comprises the following steps: providing a substrate, wherein a first epitaxial layer is formed on the substrate, a liner oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the liner oxide layer, a first oxide layer is formed on the hard mask layer, the region on the substrate comprises a first region and a second region, the first region is used for forming a contraposition mark, and the second region is used for forming a semiconductor device; performing first etching treatment through a photoetching process, forming a first groove in a first area, forming a second groove in a second area, wherein the depths of the first groove and the second groove are the same, and the first epitaxial layers at the bottoms of the first groove and the second groove are exposed; performing second etching treatment on the second region through a photoetching process to enable the depth of the second groove to reach a preset region in the first epitaxial layer so as to form a deep groove; and forming an alignment mark in the first trench, and forming a deep trench structure in the deep trench.
Description
Technical Field
The present disclosure relates to the field of technology, and more particularly, to a method for manufacturing a semiconductor device having a Deep Trench (DT) structure.
Background
Deep trench structures (the ratio of the height to the width of which is usually greater than 4) are widely used in the field of semiconductor integrated circuits, for example, Bi-CMOS devices (complementary metal oxide semiconductor (CMOS) devices and Bipolar Junction Transistor (BJT) devices integrated on the same chip), High Voltage (HV) devices, and image sensor (CMOS) devices.
In a manufacturing process of a semiconductor device including a deep trench structure, a deep trench is usually etched on a flat substrate surface, and then a series of complex process flows are performed. However, in the related art, the alignment mark formed in the manufacturing process of the semiconductor device including the deep trench structure has many disadvantages, for example, the alignment mark is not clear, the alignment accuracy is not high, and the alignment mark is not flat on the substrate surface, which may cause uneven photoresist coating or photoresist throwing in the subsequent process, thereby reducing the yield of the product.
Disclosure of Invention
The application provides a manufacturing method of a semiconductor device containing a deep groove structure, which can solve the problems that a contraposition mark formed in the manufacturing method of the semiconductor device containing the deep groove structure provided in the related technology is not clear and the surface of a substrate is not flat, and comprises the following steps:
providing a substrate, wherein a first epitaxial layer is formed on the substrate, a liner oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the liner oxide layer, a first oxide layer is formed on the hard mask layer, the region on the substrate comprises a first region and a second region, the first region is used for forming a contraposition mark, and the second region is used for forming the semiconductor device;
performing first etching treatment through a photoetching process, forming a first groove in the first area, forming a second groove in the second area, wherein the depths of the first groove and the second groove are the same, and the first epitaxial layer at the bottom of the first groove and the bottom of the second groove are exposed;
performing second etching treatment on the second region through a photoetching process to enable the depth of the second groove to reach the preset depth in the first epitaxial layer, so as to form a deep groove;
and forming a contraposition mark in the first trench, and forming a deep trench structure in the deep trench.
In some embodiments, the forming of the alignment mark in the first trench and the forming of the deep trench structure in the deep trench include:
forming a second epitaxial layer and a second oxide layer at the bottom of the first trench and the side wall and the bottom of the part, below the first oxide layer, in the deep trench in sequence;
forming a third oxide layer, wherein the third oxide layer fills the first groove and the deep groove;
carrying out planarization treatment until the hard mask layer is exposed;
performing third etching treatment to remove the second oxide layer and the third oxide layer with a predetermined depth in the deep trench, wherein the predetermined depth is lower than the liner oxide layer;
removing the pad oxide layer and the hard mask layer, wherein the alignment mark is formed by the second epitaxial layer, the second oxide layer and the third oxide layer which are left in the first region, and the deep trench structure is formed by the second epitaxial layer, the second oxide layer and the third oxide layer in the deep trench of the second region;
forming a third epitaxial layer, wherein the third epitaxial layer covers the alignment mark and fills the exposed area in the third groove;
and carrying out planarization treatment until the alignment mark is exposed.
In some embodiments, the impurity type in the first epitaxial layer and the second epitaxial layer are different, and the impurity type in the second epitaxial layer and the third epitaxial layer are the same.
In some embodiments, the substrate and the first epitaxial layer are of different impurity types.
In some embodiments, the hard mask layer comprises a silicon nitride layer.
In some embodiments, the performing a third etching process includes:
and performing the third etching treatment by a wet etching process.
In some embodiments, the semiconductor device comprises an image sensor device.
The technical scheme at least comprises the following advantages:
in the manufacturing process of the semiconductor device, a first groove is formed in a first area for forming the alignment mark through first etching treatment, a second groove is formed in a second area for forming the semiconductor device, then the second groove is continuously etched downwards to form a deep groove through second etching treatment in the second area, the alignment mark is formed in the first groove, a deep groove structure is formed in the deep groove, and the deep groove and the first groove are respectively formed, so that the problem that the alignment mark is unclear due to the fact that the grooves of the alignment mark and the deep groove structure are formed simultaneously is solved, and the yield of products is improved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a flow chart of a method of fabricating a semiconductor device provided in an exemplary embodiment of the present application;
fig. 2 to 13 are schematic views illustrating a manufacturing process of a semiconductor device according to an exemplary embodiment of the present application;
fig. 14 is a flow chart of a method for fabricating a semiconductor device according to an exemplary embodiment of the present application.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 1, which shows a flowchart of a method for fabricating a semiconductor device containing a deep trench structure, the semiconductor device including at least one of a Bi-CMOS device, a high voltage device, and a pattern sensor device, according to an exemplary embodiment of the present application, as shown in fig. 1, the method includes:
step S1, providing a substrate, where a first epitaxial layer is formed on the substrate, a pad oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the pad oxide layer, a first oxide layer is formed on the hard mask layer, and the region on the substrate includes a first region and a second region, the first region is used for forming an alignment mark, and the second region is used for forming a semiconductor device.
Referring to fig. 2, a schematic cross-sectional view of a substrate formed with multiple thin film layers is shown, according to an exemplary embodiment of the present application. As shown in fig. 2, a first epitaxial layer 221 is formed on a substrate 210, a pad oxide layer 230 is formed on the first epitaxial layer 221, a hard mask layer 240 is formed on the pad oxide layer 230, and a first oxide layer 251 is formed on the hard mask layer 240.
Wherein the pad oxide layer 230 may be silicon oxide (e.g., silicon dioxide (SiO))2) A layer), the first oxide layer 251 may be a silicon oxide (e.g., silicon dioxide) layer, and the constituent material of the hard mask layer 240 does not contain silicon oxide, e.g., it may be a silicon nitride (e.g., silicon nitride (SiN)) layer.
The first epitaxial layer 221 may be formed on the substrate 210 through an epitaxial process, the pad oxide layer 230 may be formed on the epitaxial layer 230 through a thermal oxidation (thermal oxidation) process, the hard mask layer 240 may be formed by depositing silicon nitride on the pad oxide layer 230 through a Chemical Vapor Deposition (CVD) process, and the first oxide layer 251 may be formed by depositing silicon nitride on the hard mask layer 240 through a CVD process.
A first area 201 and a second area 202 are distributed in an area where the surface of the substrate 210 is located, the first area 201 is used for forming an alignment mark, the second area 202 is used for forming a semiconductor device, and if the semiconductor device used for integration on the substrate 210 is an image sensor device, the second area 202 may be a pixel (pixel) area of the image sensor device.
Step S2, a first etching process is performed through a photolithography process to form a first trench in the first region and a second trench in the second region, wherein the first trench and the second trench have the same depth, and the first epitaxial layer at the bottom of the first trench and the bottom of the second trench are exposed.
Referring to fig. 3, there is shown a schematic cross-sectional view of a photoresist coated on a first oxide layer by a photolithography process; referring to fig. 4, a schematic cross-sectional view of the etching to form the first trench and the second trench is shown. Illustratively, as shown in fig. 3 and 4, step S2 includes, but is not limited to: covering the first oxide layer 251 with a photoresist 300 by a photolithography process to expose a target region (3001 is a target region in the first region 201, 3002 is a target region in the second region 202); performing dry etching until the first epitaxial layer 221 of the target region is exposed, forming a first trench 301 in the first region 201, and forming a second trench 302 in the second region 202, wherein the first trench 301 and the second trench 302 have the same depth because they are formed in the same etching step; the photoresist 300 is removed.
Step S3, performing a second etching process on the second region through a photolithography process to make the depth of the second trench reach a predetermined depth in the first epitaxial layer, thereby forming a deep trench.
Referring to fig. 5, there is shown a schematic cross-sectional view of a photoresist covered in a first region by a photolithography process; referring to fig. 6, a schematic cross-sectional view of etching to form a deep trench is shown. For example, as shown in fig. 5 and 6, step S3 includes, but is not limited to: covering the photoresist 300 on the first region 201 by photolithography to expose the second region 202; performing an etching process (e.g., by a dry etching process) to a predetermined depth in the first epitaxial layer 221 of the second trench 302, forming a deep trench 303 while the first oxide layer 251 of the second region 202 is thinned; the photoresist 300 is removed.
Step S4, forming an alignment mark in the first trench, and forming a deep trench structure in the deep trench.
Referring to fig. 11, a cross-sectional view of the formed alignment mark and deep trench structure is shown. Illustratively, as shown in fig. 11, in the first region 201, the alignment mark 410 is formed by the thin film layers filled in the first trench 301, and the thin film layers filled in the first trench 301 sequentially include a second epitaxial layer 222, a second oxide layer 252, and a third oxide layer 253 from bottom to top; in the second region 202, the thin film layer filled in the deep trench 303 forms a deep trench structure 420, the thin film layer filled in the deep trench 303 includes a lower portion and an upper portion, the thin film layer of the lower portion includes the second epitaxial layer 222, the second oxide layer 252, and the third oxide layer 253 from the outside to the inside, and the thin film layer of the upper portion includes the second epitaxial layer 222. Wherein the second oxide layer 252 and the third oxide layer 253 include a silicon oxide (e.g., silicon dioxide) layer.
In the embodiment of the present application, the impurity types in the substrate 210 and the first epitaxial layer 221 are different, and the impurity types in the first epitaxial layer 221 and the second epitaxial layer 222 are different. If the impurity type in the substrate 210 is a P (positive) type, the impurity type in the first epitaxial layer 221 is a n (negative) type, and the impurity type in the second epitaxial layer 222 is a P type.
In summary, in the embodiment of the present application, in the manufacturing process of the semiconductor device, a first trench is formed in a first region for forming the alignment mark through a first etching process, a second trench is formed in a second region for forming the semiconductor device, and then the second trench is continuously etched downward to form a deep trench through a second etching process performed in the second region, so that the alignment mark is formed in the first trench, and a deep trench structure is formed in the deep trench.
Referring to fig. 14, which shows a flowchart of a method for manufacturing a semiconductor device according to an exemplary embodiment of the present application, the method may be an alternative implementation manner of step S4 in the embodiment of fig. 1, and the method includes:
and S4.1, sequentially forming a second epitaxial layer and a second oxide layer at the bottom of the first trench and the side wall and the bottom of the part, below the liner oxide layer, in the deep trench.
Referring to fig. 7, a cross-sectional schematic view of the formation of the second epitaxial layer and the second oxide layer is shown. Illustratively, as shown in fig. 7, the second epitaxial layer 222 may be formed by an epitaxial process, the second oxide layer 252 may be formed by depositing silicon oxide on the second epitaxial layer 222 by a CVD process, and an etching process (e.g., by a dry etching process) is performed to remove the second epitaxial layer 222 and the second oxide layer 252 on the sidewall of the first trench 301 and to remove the second epitaxial layer 222 and the second oxide layer 252 above the first epitaxial layer 221 in the deep trench 303 (which may be achieved by adjusting the angle of the dry etching process due to the large aspect ratio of the deep trench 303).
And S4.2, forming a third oxide layer, wherein the third oxide layer fills the first groove and the deep groove.
Referring to fig. 8, a schematic cross-sectional view of forming a third oxide layer is shown. Illustratively, as shown in fig. 8, the third oxide layer 253 may be formed by depositing silicon oxide by a CVD process, and the third oxide layer 253 fills the unfilled regions in the first trench 301 and the deep trench 303.
And step S4.3, carrying out planarization treatment until the hard mask layer is exposed.
Referring to fig. 9, a schematic cross-sectional view of the first oxide layer and the third oxide layer removed over the hard mask layer after planarization is shown. Illustratively, the planarization process may be performed by a Chemical Mechanical Polishing (CMP) process, using the hard mask layer 240 as a stop layer.
And S4.4, performing third etching treatment to remove the second oxide layer and the third oxide layer with preset depth in the deep groove, wherein the preset depth is lower than the liner oxide layer.
Referring to fig. 10, a schematic cross-sectional view after the third etching process is shown. For example, as shown in fig. 10, since the hard mask layer 240 does not contain silicon oxide, the third etching process may be performed by a wet etching process to remove the second oxide layer 252 and the third oxide layer 253 in the deep trench 303 to a predetermined depth, which is lower than the pad oxide layer 230, while the third oxide layer 252 in the first trench 301 is thinned.
And S4.5, removing the liner oxide layer and the hard mask layer, forming a contraposition mark on the second epitaxial layer, the second oxide layer and the third oxide layer which are left in the first region, and forming a deep trench structure by the second epitaxial layer, the first oxide layer and the third oxide layer in the deep trench of the second region.
Referring to fig. 11, a schematic cross-sectional view after removing the pad oxide layer and the hard mask layer is shown. Illustratively, as shown in fig. 11, the pad oxide layer 230 and the hard mask layer 240 may be removed by a dry etching process. The second epitaxial layer 222, the second oxide layer 252 and the third oxide layer 253 remaining in the first region 201 constitute the alignment mark 410, and the second epitaxial layer 222, the second oxide layer 252 and the third oxide layer 253 in the deep trench 303 of the second region 202 constitute the deep trench structure 420.
And S4.6, forming a third epitaxial layer, wherein the third epitaxial layer covers the alignment mark and fills the exposed area in the third groove.
Referring to fig. 12, a schematic cross-sectional view of the formation of the third epitaxial layer is shown. Illustratively, as shown in fig. 12, the third epitaxial layer 223 may be formed by an epitaxial process. Wherein the impurity type in the third epitaxial layer 223 and the substrate 210 is the same.
And S4.7, carrying out planarization treatment until the alignment mark is exposed.
For example, as shown in fig. 13, a planarization process may be performed by a CMP process, using the third oxide layer 253 of the first region 101 as a stop layer.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (7)
1. A method for manufacturing a semiconductor device comprising a deep trench structure, the method comprising:
providing a substrate, wherein a first epitaxial layer is formed on the substrate, a liner oxide layer is formed on the first epitaxial layer, a hard mask layer is formed on the liner oxide layer, a first oxide layer is formed on the hard mask layer, the region on the substrate comprises a first region and a second region, the first region is used for forming a contraposition mark, and the second region is used for forming the semiconductor device;
performing first etching treatment through a photoetching process, forming a first groove in the first area, forming a second groove in the second area, wherein the depths of the first groove and the second groove are the same, and the first epitaxial layer at the bottom of the first groove and the bottom of the second groove are exposed;
performing second etching treatment on the second region through a photoetching process to enable the depth of the second groove to reach the preset depth in the first epitaxial layer, so as to form a deep groove;
and forming a contraposition mark in the first trench, and forming a deep trench structure in the deep trench.
2. The method of claim 1, wherein forming the alignment mark in the first trench and forming the deep trench structure in the deep trench comprises:
forming a second epitaxial layer and a second oxide layer at the bottom of the first trench and the side wall and the bottom of the part, below the first oxide layer, in the deep trench in sequence;
forming a third oxide layer, wherein the third oxide layer fills the first groove and the deep groove;
carrying out planarization treatment until the hard mask layer is exposed;
performing third etching treatment to remove the second oxide layer and the third oxide layer with a predetermined depth in the deep trench, wherein the predetermined depth is lower than the liner oxide layer;
removing the pad oxide layer and the hard mask layer, wherein the alignment mark is formed by the second epitaxial layer, the second oxide layer and the third oxide layer which are left in the first region, and the deep trench structure is formed by the second epitaxial layer, the second oxide layer and the third oxide layer in the deep trench of the second region;
forming a third epitaxial layer, wherein the third epitaxial layer covers the alignment mark and fills the exposed area in the third groove;
and carrying out planarization treatment until the alignment mark is exposed.
3. The method of claim 2, wherein the impurity type in the first epitaxial layer and the second epitaxial layer are different, and the impurity type in the second epitaxial layer and the third epitaxial layer are the same.
4. The method of claim 3, wherein the substrate and the first epitaxial layer are of different impurity types.
5. The method of any of claims 1 to 4, wherein the hard mask layer comprises a silicon nitride layer.
6. The method of claim 5, wherein performing a third etch process comprises:
and performing the third etching treatment by a wet etching process.
7. The method of claim 6, wherein the semiconductor device comprises an image sensor device.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111413916.6A CN114121775A (en) | 2021-11-25 | 2021-11-25 | Method for manufacturing semiconductor device containing deep trench structure |
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| CN202111413916.6A CN114121775A (en) | 2021-11-25 | 2021-11-25 | Method for manufacturing semiconductor device containing deep trench structure |
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