CN114121773A - Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method - Google Patents

Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method Download PDF

Info

Publication number
CN114121773A
CN114121773A CN202111495125.2A CN202111495125A CN114121773A CN 114121773 A CN114121773 A CN 114121773A CN 202111495125 A CN202111495125 A CN 202111495125A CN 114121773 A CN114121773 A CN 114121773A
Authority
CN
China
Prior art keywords
layer
gold
substrate
nickel
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111495125.2A
Other languages
Chinese (zh)
Inventor
叶冬
沈小刚
罗驰
练东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 24 Research Institute
Original Assignee
CETC 24 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 24 Research Institute filed Critical CETC 24 Research Institute
Priority to CN202111495125.2A priority Critical patent/CN114121773A/en
Publication of CN114121773A publication Critical patent/CN114121773A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/702—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof
    • H01L21/707—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof of thick-or thin-film circuits or parts thereof of thin-film circuits or parts thereof
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/009—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone characterised by the material treated
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/45—Coating or impregnating, e.g. injection in masonry, partial coating of green or fired ceramics, organic coating compositions for adhering together two concrete elements
    • C04B41/52—Multiple coating or impregnating multiple coating or impregnating with the same composition or with compositions only differing in the concentration of the constituents, is classified as single coating or impregnation
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B41/00—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone
    • C04B41/80—After-treatment of mortars, concrete, artificial stone or ceramics; Treatment of natural stone of only ceramics
    • C04B41/81—Coating or impregnation
    • C04B41/89—Coating or impregnation for obtaining at least two superposed coatings having different compositions
    • C04B41/90—Coating or impregnation for obtaining at least two superposed coatings having different compositions at least one coating being a metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Power Engineering (AREA)
  • Organic Chemistry (AREA)
  • Structural Engineering (AREA)
  • Materials Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

The invention relates to a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit and a manufacturing method thereof, wherein the ceramic thin film substrate comprises a thin film resistance layer, a barrier layer and a thin gold seed crystal layer which are sequentially formed on a substrate; forming a gold conduction band on the thin gold seed crystal layer; removing the thin gold seed crystal layer; forming a nickel layer in a region to be plated with nickel; covering a bonding pad gold layer on the nickel layer of the bonding pad area; forming a thin film resistor network; a nickel passivation layer is formed. According to the invention, a gold conduction band and a nickel-chromium-silicon thin film resistor network are respectively formed on an alumina ceramic substrate by adopting magnetron sputtering, photoetching technology, microelectronic electroplating technology, photoresist removing technology, corrosion technology and heat treatment technology, and a nickel-gold welding pad and a solder mask layer are superposed on the gold conduction band, so that the manufactured thin film substrate has thick gold layer thickness, high line width precision and steep step morphology, and can meet the application requirements of high precision, high frequency and high reliability; the substrate structure is compatible with a standard micro-assembly process and can be widely applied to the field of thin film hybrid integrated circuits.

Description

Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method
Technical Field
The invention belongs to the technical field of high-reliability thin film hybrid integrated circuits, and relates to a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit and a manufacturing method thereof.
Background
The substrate is a core component of electronic equipment, plays key roles of mechanical support, heat dissipation, electric conduction and the like, and is an MCM-D process technology based on a thin film process, which has the highest assembly density and performance in all forms of MCM components and is a key basic process technology related to an advanced packaging technology. With the development of electronic products in the direction of high density, high speed, high precision, miniaturization and system integration, the rf microwave thin film substrate is required to meet the technical requirements of thick gold layer thickness, high line width precision, steep step morphology and the process processing requirement compatible with the standard micro-assembly technology, so that the existing rf microwave thin film substrate processing technology needs to be improved.
Disclosure of Invention
Accordingly, the present invention is directed to a ceramic thin film substrate for a highly reliable thin film hybrid integrated circuit and a method for fabricating the same.
In order to achieve the purpose, the invention provides the following technical scheme:
a method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit comprises the following steps:
taking a substrate and cleaning the substrate;
sequentially forming a thin film resistance layer, a barrier layer and a thin gold seed crystal layer on a substrate;
forming a gold conduction band on the thin gold seed crystal layer;
removing the exposed thin gold seed crystal layer on the surface of the substrate to expose the barrier layer;
forming an upper end surface covering the gold conduction band and a nickel layer wrapping the side wall of the gold conduction band in a region to be plated with nickel;
covering a bonding pad gold layer on the nickel layer of the bonding pad area to form a nickel thin gold bonding pad; the size of the gold layer of the bonding pad is smaller than that of the gold conduction band below the gold layer;
removing the barrier layer of the exposed part on the thin film resistor layer;
removing the thin film resistor layer on the exposed part of the substrate to expose the substrate to form a thin film resistor network;
and carrying out heat treatment on the substrate to form a nickel passivation layer on the nickel layer at the exposed part.
Further, the substrate is an alumina ceramic wafer, and the cleaning of the substrate comprises the following steps:
taking NH4OH、H2O2And H2Taking the mixed solution of O as a first cleaning solution; putting the substrate into a first cleaning solution and boiling for 5 minutes;
taking KCL, H2O2And H2The mixed solution of O is used as a second cleaning solution; putting the substrate into a second cleaning solution and boiling for 5 minutes;
and (3) carrying out deionized washing on the substrate, drying the substrate by spin, and baking the substrate for 1 hour in an environment at 150 ℃.
Further, sequentially forming the thin film resistor layer, the barrier layer and the thin gold seed crystal layer on the substrate specifically includes:
forming a nickel-chromium silicon layer on a substrate through magnetron sputtering to serve as a thin film resistance layer, wherein the sheet resistance of the thin film resistance layer is 25-150 omega/□;
forming a titanium-tungsten layer as a barrier layer on the thin film resistance layer through magnetron sputtering; the thickness of the barrier layer is 40-50 nm;
forming a gold layer on the barrier layer as a thin gold seed crystal layer through magnetron sputtering; the thickness of the thin gold seed crystal layer is 120-200 nm.
Further, the forming of the gold conduction band on the thin gold seed layer specifically includes:
spin-coating a first photoresist on the thin gold seed crystal layer and photoetching a pattern of a gold conduction band; the first photoresist is a negative photoresist, and the thickness of the spin-coated photoresist is 5-6 μm.
Exposing and developing the first photoresist to expose a thin gold seed crystal layer in the gold conduction band region;
electroplating a gold layer with the thickness of 4-5.5 microns on the thin gold seed crystal layer exposed out of the gold conduction band area by adopting a microelectronic gold electroplating process to form a gold conduction band;
and removing the first photoresist on the substrate.
Further, removing the exposed thin gold seed crystal layer on the surface of the substrate, and exposing the barrier layer comprises:
adopting an electrochemical corrosion process, and corroding the gold layer on the surface of the whole substrate by using an acid solution at a corrosion rate of 30-40 nm/min; until the thin gold seed crystal layer exposed on the surface of the substrate is completely corroded to expose the barrier layer.
Further, forming a nickel layer covering the upper end surface of the gold conduction band and wrapping the sidewall of the gold conduction band in the region to be plated with nickel specifically includes:
photoetching a pattern of a region to be plated with nickel by using a second photoresist, wherein the region to be plated with nickel comprises a region where a gold conduction band is located below a bonding pad region, and an extension region which is formed by extending 5.0-7.5 mu m towards the direction without the gold conduction band on the periphery of the region where the gold conduction band is located and extending 200-250 mu m along the connected gold conduction band; the second photoresist adopts positive photoresist, and the thickness of the spin-coated photoresist is 5-6 μm;
exposing the upper end face of the gold conduction band in the nickel plating region through exposure and development of the second photoresist, and forming a gap exposing the side wall of the gold conduction band around the gold conduction band; the width of the gap is 5.0-7.5 mu m;
and electroplating a nickel layer on the upper end face and the side wall of the exposed gold conduction band by adopting a microelectronic nickel electroplating process, wherein the thickness of the nickel layer is 2-4.0 mu m.
Further, coating a gold layer on the nickel layer of the pad region, and forming the nickel thin gold pad specifically includes:
etching a pattern of a pad area on the nickel layer by using a third photoresist; the third photoresist is positive photoresist, and the thickness of the spin-coated photoresist is 5-6 mu m.
Exposing the nickel layer of the pad region by exposing and developing the third photoresist;
forming a nickel thin gold bonding pad by covering a bonding pad gold layer on the exposed nickel layer through magnetron sputtering; the thickness of the gold layer of the bonding pad is 100-120 nm;
and removing the second photoresist and the third photoresist on the substrate.
Further, removing the thin film resistor layer on the exposed portion of the substrate to expose the substrate specifically includes:
photoetching a graph of the thin film resistor area by adopting fourth photoresist; the fourth photoresist adopts positive photoresist, and the thickness of the spin-coated photoresist is 2-3 mu m;
exposing the thin film resistor layer outside the thin film resistor area by exposing and developing the fourth photoresist to form a thin film resistor network;
removing the thin film resistance layer on the exposed part of the substrate by wet etching to expose the substrate;
and removing the fourth photoresist on the substrate.
Further, the substrate is subjected to heat treatment under the protection of nitrogen, nickel nitride is generated on the nickel layer of the exposed part, a nickel passivation layer is formed, the heat treatment temperature is 300 +/-5 ℃, and the heat treatment time is 30 minutes.
A ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit comprises a substrate, wherein a thin film resistor network is arranged on the substrate, and the thin film resistor network is a nickel-chromium silicon layer with a square resistance of 25-150 omega/□; the thin film resistor network is provided with a gold conduction band, and the gold conduction band is provided with an upper end surface covering the gold conduction band of the region and a nickel layer wrapping the side wall of the gold conduction band of the region corresponding to the region to be plated with nickel; the region to be plated with nickel comprises a region where a gold conduction band is located below the bonding pad region, and an extension region which is formed by extending 5.0-7.5 mu m towards the direction without the gold conduction band on the basis of the region where the gold conduction band is located and extending 200-250 mu m along the connected gold conduction band; a bonding pad gold layer is arranged on the nickel layer of the bonding pad area; and a nickel passivation layer is arranged on the nickel layer of the uncovered area of the bonding pad gold layer.
In the invention, a gold conduction band and a nickel-chromium-silicon film resistor network are respectively formed on an alumina ceramic substrate by a film wiring process technology and by adopting magnetron sputtering, a photoetching technology, a microelectronic electroplating process, a photoresist removing technology, a corrosion technology and a heat treatment technology, and a nickel-gold welding pad and a solder mask layer are superposed on the gold conduction band. The film substrate manufactured by the process has thick gold layer thickness, high line width precision and steep step appearance, and can meet the application requirements of high precision, high frequency and high reliability; the substrate structure is compatible with standard micro-assembly processes such as gold wire bonding, polymer assembly, gold-based solder and tin-based solder welding, and the like, can be widely applied to the field of thin film hybrid integrated circuits, and is particularly suitable for the field of radio frequency and microwave circuits.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a flow chart of a method for manufacturing a ceramic thin film substrate for a highly reliable thin film hybrid integrated circuit according to a preferred embodiment of the present invention.
FIG. 2 is a cross-sectional view of a thin resistive layer, a barrier layer and a thin gold seed layer formed on a substrate.
FIG. 3 is a cross-sectional view of a thin gold seed layer with photoresist spun on and a gold conduction band pattern photo-etched.
FIG. 4 is a schematic cross-sectional view of a gold conduction band formed by a microelectronic gold electroplating process.
FIG. 5 is a cross-sectional view of FIG. 4 after the photoresist has been removed.
FIG. 6 is a cross-sectional view of the substrate of FIG. 5 after the removal of the exposed thin gold seed layer.
FIG. 7 is a schematic cross-sectional view of a gold conductive strip after exposure of a region to be plated with nickel by photolithography.
FIG. 8 is a schematic cross-sectional view of a nickel layer formed by selective nickel electroplating.
Fig. 9 is a schematic cross-sectional view after exposing the pad region by photolithography.
Fig. 10 is a cross-sectional view of the pad after sputtering a gold layer on the pad area.
FIG. 11 is a cross-sectional view of FIG. 10 after photoresist removal.
Fig. 12 is a schematic structural diagram of the pad region in fig. 11.
FIG. 13 is a cross-sectional view of FIG. 11 after etching the barrier layer.
Fig. 14 is a schematic cross-sectional view of fig. 12 after a thin film resistor pattern is formed by photolithography.
Fig. 15 is a schematic cross-sectional view of fig. 14 after etching away the nickel-chromium-silicon layer and removing the photoresist.
FIG. 16 is a cross-sectional view of the metal layer of FIG. 15 after a nickel nitride passivation layer has been formed by the thermal process.
In the figure: 1. the manufacturing method comprises a substrate, 2 parts of a thin film resistance layer, 3 parts of a barrier layer, 4 parts of a thin gold seed crystal layer, 6 parts of a gold conduction band, 7 parts of a nickel layer, 8 parts of a pad gold layer, 9 parts of a nickel passivation layer, 11 parts of a first photoresist, 12 parts of a second photoresist, 13 parts of a third photoresist, 14 parts of a fourth photoresist and 15 parts of a gap.
Detailed Description
The embodiments of the invention are explained below by means of specific examples, the illustrations provided in the following examples are merely illustrative of the basic idea of the invention, and features in the following examples and examples can be combined with one another without conflict.
As shown in fig. 1, a preferred embodiment of the method for manufacturing a ceramic thin film substrate for a highly reliable thin film hybrid integrated circuit according to the present invention comprises the steps of:
s1, a substrate 1 is taken out, and the substrate 1 is cleaned. The substrate 1 is preferably an alumina ceramic wafer, and the cleaning of the substrate 1 may include the following sub-steps:
s11, taking NH4OH、H2O2And H2Taking the mixed solution of O as a first cleaning solution; putting the substrate 1 into a first cleaning solution and boiling for 5 minutes; wherein the volume ratio of each solution is NH4OH:H2O2:H2O＝1:2:7。
S12, KCL and H2O2And H2The mixed solution of O is used as a second cleaning solution; putting the substrate 1 into a second cleaning solution and boiling for 5 minutes; wherein the volume ratio of each solution is KCL to H2O2:H2O＝1:2:7。
S13, the substrate 1 is dried after being deionized and washed, and is baked for 1 hour at the temperature of 150 ℃.
S2, as shown in fig. 2, sequentially forming a thin resistive layer 2, a barrier layer 3 and a thin gold seed layer 4 on a substrate 1; the method specifically comprises the following substeps:
s21, forming a nickel chromium silicon (NiCrSi) layer on the substrate 1 through magnetron sputtering to serve as the thin film resistor layer 2, wherein the sheet resistance of the thin film resistor layer 2 is 25-150 omega/□;
s22, forming a titanium Tungsten (TiW) layer as a barrier layer 3 on the thin film resistor layer 2 through magnetron sputtering; the thickness of the barrier layer 3 is 40-50 nm;
s23, forming a gold (Au) layer on the barrier layer 3 as a thin gold seed crystal layer 4 through magnetron sputtering; the thickness of the thin gold seed crystal layer 4 is 120-200 nm.
S3, forming a gold conduction band 6 on the thin gold seed crystal layer 4; the method specifically comprises the following substeps:
s31, spin-coating a first photoresist 11 on the thin gold seed crystal layer 4 and photoetching a pattern of the gold conduction band 6; the first photoresist 11 is a negative photoresist with the viscosity of 150cp, the coating speed is 800 rpm, and the thickness of the spin-coated photoresist is 5-6 μm.
S32, the thin gold seed layer 4 of the gold conduction band region is exposed by exposing and developing the first photoresist 11, and the cross-sectional shape after exposure and development is shown in fig. 3.
S33, electroplating a gold layer with the thickness of 4-5.5 microns on the thin gold seed crystal layer 4 exposed out of the gold conduction band area by adopting a microelectronic gold electroplating process, so that the thin gold seed crystal layer 4 in the gold conduction band area is thickened to form a gold conduction band 6; the cross-sectional shape is shown in fig. 4.
S34, removing the first photoresist 11 on the substrate 1 by soaking in fuming nitric acid, and drying the substrate 1 after flushing for 10 minutes; the cross-sectional shape after removing the first photoresist 11 is shown in fig. 5.
S4, as shown in FIG. 6, removing the exposed thin gold seed crystal layer 4 on the surface of the substrate 1 to expose the barrier layer 3; the specific method comprises the following steps:
performing equal corrosion on the gold layer (including the gold layer of the thin gold seed crystal layer 4 and the gold layer of the gold conduction band 6) on the surface of the whole substrate 1 by using an acid solution at room temperature by adopting an electrochemical corrosion process, wherein the corrosion rate is 30-40 nm/min; until the thin gold seed crystal layer 4 exposed on the surface of the substrate 1 is completely corroded, and the barrier layer 3 is exposed. In the process, the gold layer of the gold conduction band 6 and the gold layer of the thin gold seed crystal layer 4 can be synchronously corroded, but the thickness of the gold layer of the gold conduction band 6 is far larger than that of the thin gold seed crystal layer 4, and the corrosion rate is slow, so the influence of the corrosion process on the thickness of the gold conduction band 6 is small. In addition, the thin gold seed layer 4 below the gold conduction band 6 cannot be corroded, and the thin gold seed layer 4 below the gold conduction band 6 can also compensate the lost thickness of the gold conduction band 6 because the thin gold seed layer 4 and the gold conduction band 6 are both made of gold layers.
S5, forming a nickel (Ni) layer 7 covering the upper end surface of the gold conduction band 6 and wrapping the side wall of the gold conduction band 6 in the region to be plated with nickel; the method specifically comprises the following substeps:
s51, photoetching a pattern of a region to be plated with nickel by using a second photoresist 12, wherein the region to be plated with nickel comprises a region where a gold conduction band is located below a pad region, and an extension region which extends 5.0-7.5 mu m towards the direction without the gold conduction band 6 on the periphery of the region where the gold conduction band is located and extends 200-250 mu m along the connected gold conduction band 6; the second photoresist 12 is a positive photoresist with the viscosity of 60cp, the coating speed is 800 rpm, and the thickness of the spin-coated photoresist is 5-6 μm.
S52, exposing the upper end face of the gold conduction band 6 of the nickel plating region through exposure and development of the second photoresist 12, and forming a gap 15 exposing the side wall of the gold conduction band 6 around the gold conduction band 6 of the nickel plating region; the width of the gap 15 is 5.0-7.5 mu m; the cross-sectional shape after exposure and development is shown in FIG. 7.
S53, adopting a microelectronic nickel electroplating process to electroplate a nickel layer 7 on the upper end face and the side wall of the exposed gold conduction band 6, wherein the thickness of the nickel layer 7 is 2-4.0 mu m. The cross-sectional shape of the nickel layer 7 is shown in fig. 8.
S6, covering a pad gold layer 8 on the nickel layer 7 of the pad area to form a nickel thin gold pad; the size of the gold layer 8 of the bonding pad is smaller than that of the gold conduction band 6 below the bonding pad; the step may specifically comprise the following sub-steps:
s61, photoetching a pattern of a pad area on the nickel layer 7 by using a third photoresist 13; the third photoresist 13 is made of positive photoresist with the viscosity of 60cp, the coating rotating speed is 800 rpm, and the thickness of the spin-coated photoresist is 5-6 μm.
S62, exposing the nickel layer 7 in the pad region by exposing and developing the third photoresist 13, the remaining part being masked by the third photoresist 13; the cross-sectional shape after exposure and development is shown in FIG. 9.
S63, as shown in fig. 10, forming a nickel thin gold pad by covering a pad gold layer 8 on the exposed nickel layer 7 by magnetron sputtering; the thickness of the gold layer 8 of the bonding pad is 100-120 nm.
And S64, ultrasonically cleaning the substrate 1 by using acetone and ethanol solution to remove the second photoresist 12 and the third photoresist 13 on the substrate 1, and drying the substrate 1 after flushing for 10 minutes. The cross-sectional shape after removing the second photoresist 12 and the third photoresist 13 on the substrate 1 is shown in fig. 11; at this time, the gold layer sputtered on the third photoresist 13 in step S63 is also removed after the support of the third photoresist 13 is lost.
Fig. 12 is a top view of the two pad regions of fig. 11, wherein the dotted line represents the outline of the gold strip 6 covered by the nickel layer 7; as can be seen from the figure, the gold conduction band 6 below the left pad region is completely wrapped by the nickel layer 7, and the gold conduction band 6 below the right pad region is completely wrapped by the nickel layer 7, and the nickel layer 7 also completely wraps a section of the gold conduction band 6 connected with the nickel thin gold pad, so that the phenomenon that solder flows onto the gold conduction band 6 around the pad to cause gold layer corrosion of the gold conduction band 6 is avoided.
S7, as shown in fig. 13, removing the barrier layer 3 on the exposed portion of the thin film resistor layer 2; preferably, wet etching is used to remove the barrier layer 3 on the exposed portion of the thin film resistor layer 2, and the etching solution is H2O2The corrosion temperature is 40 ℃, and the corrosion rate is 250-270 nm/min.
S8, removing the film resistance layer 2 on the exposed part of the substrate 1 to expose the substrate 1; the method specifically comprises the following substeps:
s81, photoetching a pattern of the thin film resistor area by adopting a fourth photoresist 14; the fourth photoresist 14 is a positive photoresist with the viscosity of 20cp, the coating speed is 800 rpm, and the thickness of the spin-coated photoresist is 2-3 μm.
S82, exposing the thin film resistance layer 2 outside the thin film resistance region by exposing and developing the fourth photoresist 14; the cross-sectional shape after exposure and development is shown in fig. 14.
S83, removing the film resistor layer 2 on the exposed part of the substrate 1 by wet etching to expose the substrate 1, thereby forming a film resistor network; the cross-sectional shape after etching is shown in FIG. 15. The corrosion solution is cerium ammonium nitrate and nitric acid corrosion solution, the corrosion temperature is room temperature, and the corrosion speed is 5-7 nm/min.
And S84, ultrasonically cleaning the substrate 1 by using acetone and ethanol solution to remove the fourth photoresist 14 on the substrate 1, and drying the substrate 1 after flushing for 10 minutes.
S9, as shown in fig. 16, heat-treating the substrate 1 under the protection of nitrogen gas, wherein the heat-treating temperature is preferably 300 ± 5 ℃, and the heat-treating time is preferably 30 minutes, so as to generate nickel nitride on the nickel layer 7 of the exposed part and form a nickel passivation layer 9 (i.e. nickel nitride layer); and obtaining the ceramic film substrate for the high-reliability film hybrid integrated circuit. By passivating the surface of the exposed nickel layer 7, in the process of welding, because the nickel passivation layer 9 and tin-lead solder have no solderability, the welding of the solder is limited on the bonding pad, the phenomenon that the solder flows onto the gold layer of the gold conduction band 6 around the bonding pad to cause the gold layer of the gold conduction band 6 to be corroded is avoided, and the integrity, the electrical property and the reliability of the metal structure of the substrate 1 are ensured. In addition, the nickel passivation solder mask is simpler and more convenient than an organic medium (such as polyimide) process, avoids the loss of the organic medium to high-frequency signal transmission and is beneficial to the application in the high-frequency field.
According to the embodiment, through innovative layout design and process design, a thin film wiring process technology is adopted on an aluminum oxide ceramic thin film substrate, a magnetron sputtering and selective microelectronic gold electroplating process is adopted, the gold layer of the gold conduction band 6 is strictly limited in a window formed by thick photoresist to be deposited and thickened, and an equal-difference corrosion process is combined to form the conduction band with good surface flatness, high line width precision and steep step morphology, and the conduction band has good transmission characteristics of strong oxidation resistance, low resistance and low loss.
In the embodiment, on the same electroplated nickel layer 7, thin gold is sputtered on the nickel layer 7 in the pad area to form the nickel thin gold pad, and the exposed nickel layer 7 is reserved on the periphery of the nickel thin gold pad and the gold conduction band 6 layer connected with the nickel thin gold pad, and the surface of the exposed nickel layer 7 is passivated through a heat treatment process, so that the pad with the resistance welding function is formed, and the integrity, the electrical property and the reliability of the metal structure of the substrate 1 in the welding process are ensured. In addition, the process of passivating the solder mask layer by adopting nickel is simple and convenient, the loss of an organic medium to high-frequency signal transmission is avoided, and the application in the high-frequency field is facilitated.
The aluminum oxide ceramic film substrate manufactured by the method is compatible with standard micro-assembly processes such as gold wire bonding, polymer assembly, gold-based solder and tin-based solder welding and the like, can meet high-precision, high-frequency and high-reliability application occasions, and can also be popularized and applied to other types (such as aluminum nitride, beryllium oxide and the like) of film substrates to meet the high-reliability application requirements of products.
As shown in fig. 16, a preferred embodiment of the ceramic thin film substrate for a highly reliable thin film hybrid integrated circuit according to the present invention includes a substrate 1, wherein a thin film resistor network is disposed on the substrate 1, and the thin film resistor network is a nichrome layer with a sheet resistance of 25 to 150 Ω/□; the thin film resistor network is provided with a gold conduction band 6, and the thickness of the gold conduction band 6 is 4-5.5 micrometers. The gold conduction band 6 is provided with an upper end face covering the gold conduction band 6 in the region to be plated with nickel and a nickel layer 7 wrapping the side wall of the gold conduction band 6 in the region, wherein the region to be plated with nickel comprises a region where the gold conduction band is located below a bonding pad region and an extension region which is formed by extending 5.0-7.5 mu m towards the direction without the gold conduction band 6 on the basis of the region where the gold conduction band is located and extending 200-250 mu m along the connected gold conduction band 6; the thickness of the nickel layer is 2-4.0 μm. A pad gold layer 8 is arranged on the nickel layer 7 of the pad area, the thickness of the pad gold layer 8 is 100-120 nm, and the size of the pad gold layer 8 is smaller than that of the gold conduction band 6 below the pad gold layer. A nickel passivation layer 9 is arranged on the nickel layer 7 in the non-pad region, said nickel passivation layer 9 preferably being nickel nitride.
In the embodiment, the exposed nickel passivation layer 8 is arranged on the periphery of the nickel thin gold bonding pad and the gold conduction band 6 layer connected with the nickel thin gold bonding pad, so that the bonding pad with the resistance welding function is formed, and the integrity, the electrical property and the reliability of the metal structure of the substrate 1 in the welding process are ensured. In addition, the alumina ceramic thin film substrate of the embodiment is compatible with standard micro-assembly technologies, including gold wire bonding, gold-tin eutectic soldering, tin-lead solder soldering and polymer assembly, and the thin film hybrid integrated circuit product assembled by using the substrate 1 meets the requirements of GJB2438 'hybrid integrated circuit general Specification', and the reliability grade of the product reaches H level.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.

Claims (10)

1. A method for manufacturing a ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit is characterized by comprising the following steps:
taking a substrate and cleaning the substrate;
sequentially forming a thin film resistance layer, a barrier layer and a thin gold seed crystal layer on a substrate;
forming a gold conduction band on the thin gold seed crystal layer;
removing the exposed thin gold seed crystal layer on the surface of the substrate to expose the barrier layer;
forming an upper end surface covering the gold conduction band and a nickel layer wrapping the side wall of the gold conduction band in a region to be plated with nickel;
covering a bonding pad gold layer on the nickel layer of the bonding pad area to form a nickel thin gold bonding pad; the size of the gold layer of the bonding pad is smaller than that of the gold conduction band below the gold layer;
removing the barrier layer of the exposed part on the thin film resistor layer;
removing the thin film resistor layer on the exposed part of the substrate to expose the substrate to form a thin film resistor network;
and carrying out heat treatment on the substrate to form a nickel passivation layer on the nickel layer at the exposed part.
2. The method of claim 1, wherein the substrate is an alumina ceramic wafer, and the cleaning of the substrate comprises the following steps:
taking NH4OH、H2O2And H2Taking the mixed solution of O as a first cleaning solution; putting the substrate into a first cleaning solution and boiling for 5 minutes;
taking KCL, H2O2And H2The mixed solution of O is used as a second cleaning solution; putting the substrate into a second cleaning solution and boiling for 5 minutes;
and (3) carrying out deionized washing on the substrate, drying the substrate by spin, and baking the substrate for 1 hour in an environment at 150 ℃.
3. The method as claimed in claim 1, wherein the sequentially forming the thin film resistor layer, the barrier layer and the thin gold seed layer on the substrate comprises:
forming a nickel-chromium silicon layer on a substrate through magnetron sputtering to serve as a thin film resistance layer, wherein the sheet resistance of the thin film resistance layer is 25-150 omega/□;
forming a titanium-tungsten layer as a barrier layer on the thin film resistance layer through magnetron sputtering; the thickness of the barrier layer is 40-50 nm;
forming a gold layer on the barrier layer as a thin gold seed crystal layer through magnetron sputtering; the thickness of the thin gold seed crystal layer is 120-200 nm.
4. The method of claim 1, wherein forming a gold conductive strip on the thin gold seed layer comprises:
spin-coating a first photoresist on the thin gold seed crystal layer and photoetching a pattern of a gold conduction band; the first photoresist is a negative photoresist, and the thickness of the spin-coated photoresist is 5-6 μm.
Exposing and developing the first photoresist to expose a thin gold seed crystal layer in the gold conduction band region;
electroplating a gold layer with the thickness of 4-5.5 microns on the thin gold seed crystal layer exposed out of the gold conduction band area by adopting a microelectronic gold electroplating process to form a gold conduction band;
and removing the first photoresist on the substrate.
5. The method of claim 1, wherein removing the exposed thin gold seed layer from the surface of the substrate to expose the barrier layer comprises:
adopting an electrochemical corrosion process, and corroding the gold layer on the surface of the whole substrate by using an acid solution at a corrosion rate of 30-40 nm/min; until the thin gold seed crystal layer exposed on the surface of the substrate is completely corroded to expose the barrier layer.
6. The method as claimed in claim 1, wherein the forming of the nickel layer on the upper surface of the metal strap and on the sidewall of the metal strap surrounding the nickel plating region comprises:
photoetching a pattern of a region to be plated with nickel by using a second photoresist, wherein the region to be plated with nickel comprises a region where a gold conduction band is located below a bonding pad region, and an extension region which is formed by extending 5.0-7.5 mu m towards the direction without the gold conduction band on the periphery of the region where the gold conduction band is located and extending 200-250 mu m along the connected gold conduction band; the second photoresist adopts positive photoresist, and the thickness of the spin-coated photoresist is 5-6 μm;
exposing the upper end face of the gold conduction band in the nickel plating region through exposure and development of the second photoresist, and forming a gap exposing the side wall of the gold conduction band around the gold conduction band; the width of the gap is 5.0-7.5 mu m;
and electroplating a nickel layer on the upper end face and the side wall of the exposed gold conduction band by adopting a microelectronic nickel electroplating process, wherein the thickness of the nickel layer is 2-4.0 mu m.
7. The method of claim 1, wherein forming the thin ni pad includes:
etching a pattern of a pad area on the nickel layer by using a third photoresist; the third photoresist is positive photoresist, and the thickness of the spin-coated photoresist is 5-6 mu m.
Exposing the nickel layer of the pad region by exposing and developing the third photoresist;
forming a nickel thin gold bonding pad by covering a bonding pad gold layer on the exposed nickel layer through magnetron sputtering; the thickness of the gold layer of the bonding pad is 100-120 nm;
and removing the second photoresist and the third photoresist on the substrate.
8. The method as claimed in claim 1, wherein removing the exposed portion of the thin film resistor layer from the substrate to expose the substrate comprises:
photoetching a graph of the thin film resistor area by adopting fourth photoresist; the fourth photoresist adopts positive photoresist, and the thickness of the spin-coated photoresist is 2-3 mu m;
exposing the thin film resistor layer outside the thin film resistor area by exposing and developing the fourth photoresist to form a thin film resistor network;
removing the thin film resistance layer on the exposed part of the substrate by wet etching to expose the substrate;
and removing the fourth photoresist on the substrate.
9. The method of claim 1, wherein the substrate is heat treated under nitrogen to form a passivation layer of nickel nitride on the nickel layer on the exposed portion, the heat treatment temperature is 300 ± 5 ℃ and the heat treatment time is 30 minutes.
10. A ceramic thin film substrate for a high-reliability thin film hybrid integrated circuit is characterized by comprising a substrate, wherein a thin film resistor network is arranged on the substrate, and the thin film resistor network is a nickel-chromium silicon layer with a square resistance of 25-150 omega/□; the thin film resistor network is provided with a gold conduction band, and the gold conduction band is provided with an upper end surface covering the gold conduction band of the region and a nickel layer wrapping the side wall of the gold conduction band of the region corresponding to the region to be plated with nickel; the region to be plated with nickel comprises a region where a gold conduction band is located below the bonding pad region, and an extension region which is formed by extending 5.0-7.5 mu m towards the direction without the gold conduction band on the basis of the region where the gold conduction band is located and extending 200-250 mu m along the connected gold conduction band; a bonding pad gold layer is arranged on the nickel layer of the bonding pad area; and a nickel passivation layer is arranged on the nickel layer of the uncovered area of the bonding pad gold layer.
CN202111495125.2A 2021-12-09 2021-12-09 Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method Pending CN114121773A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111495125.2A CN114121773A (en) 2021-12-09 2021-12-09 Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111495125.2A CN114121773A (en) 2021-12-09 2021-12-09 Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method

Publications (1)

Publication Number Publication Date
CN114121773A true CN114121773A (en) 2022-03-01

Family

ID=80364530

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111495125.2A Pending CN114121773A (en) 2021-12-09 2021-12-09 Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method

Country Status (1)

Country Link
CN (1) CN114121773A (en)

Similar Documents

Publication Publication Date Title
JP4209178B2 (en) Electronic component mounting structure and manufacturing method thereof
KR100598757B1 (en) Semiconductor device and method of fabricating the same
JP3842548B2 (en) Semiconductor device manufacturing method and semiconductor device
US7138294B2 (en) Circuit substrate device, method for producing the same, semiconductor device and method for producing the same
US6576540B2 (en) Method for fabricating substrate within a Ni/Au structure electroplated on electrical contact pads
WO1998025298A1 (en) Semiconductor device, method for manufacture thereof, circuit board, and electronic equipment
KR100503940B1 (en) Semiconductor device and method of manufacturing the same
US8178790B2 (en) Interposer and method for manufacturing interposer
JPH06350234A (en) Method for mounting electrical and/or electronic parts on insulating board and making contact connection thereof and manufacture of printed circuit board with noncurrent metal deposition and method for mounting electronic parts and making contact connection thereof
JP3280327B2 (en) Test probe structure and method of manufacturing the same
JPH04277696A (en) Multilayer interconnection board and manufacture thereof
JPH03276655A (en) Multilayer-interconnection board and its manufacture
CN114121773A (en) Ceramic thin film substrate for high-reliability thin film hybrid integrated circuit and manufacturing method
JP2008288607A (en) Method for manufacturing electronic parts packaging structure
JP2003031945A (en) Wiring board, manufacturing method therefor and electric circuit assembly
JPH11204560A (en) Semiconductor device and manufacture thereof
JPH08181423A (en) Terminal electrode structure for solder bump mounting
JP2002151622A (en) Semiconductor circuit component and its manufacturing method
JPH0669373A (en) Wiring board and its manufacture
JP2514020B2 (en) Wiring board
JPH0821763B2 (en) Electronic circuit parts
JP3723350B2 (en) Wiring board and manufacturing method thereof
JPH0745950A (en) Thin-film multilayer circuit board
JPH05183273A (en) Multilayer wiring board and manufacture thereof and elecronic device using the same
KR100296001B1 (en) Multi-layer hybrid integrated circuit manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination