CN114121701A - Method for distinguishing fault defect source of chemical mechanical polishing layer - Google Patents

Method for distinguishing fault defect source of chemical mechanical polishing layer Download PDF

Info

Publication number
CN114121701A
CN114121701A CN202111327433.4A CN202111327433A CN114121701A CN 114121701 A CN114121701 A CN 114121701A CN 202111327433 A CN202111327433 A CN 202111327433A CN 114121701 A CN114121701 A CN 114121701A
Authority
CN
China
Prior art keywords
defect
characteristic diagram
distinguishing
graph
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111327433.4A
Other languages
Chinese (zh)
Inventor
曹海瑞
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Original Assignee
Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Integrated Circuit Manufacturing Co Ltd filed Critical Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority to CN202111327433.4A priority Critical patent/CN114121701A/en
Publication of CN114121701A publication Critical patent/CN114121701A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67259—Position monitoring, e.g. misposition detection or presence detection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67242—Apparatus for monitoring, sorting or marking
    • H01L21/67288—Monitoring of warpage, curvature, damage, defects or the like
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

The invention provides a method for distinguishing a fault defect source of a chemical mechanical polishing layer, which comprises the steps of obtaining design information of a product chip, and obtaining a first characteristic diagram according to the design information; acquiring a graph of the wafer, and giving the graph to the wafer by using the same coordinate origin as the first characteristic graph so as to obtain a second characteristic graph; importing the second characteristic diagram into a database of an ADC server in the prior art to obtain defect coordinates, wherein the database carries out defect code classification according to defect types generated by different process machines; when the ADC server is used for classifying, matching the defect coordinates with the coordinates of the first characteristic diagram, and comparing to obtain the position of the defect coordinates on the first characteristic diagram; the process machine tables corresponding to the defect coordinates are determined, automatic and accurate classification can be achieved through circulation, human intervention is eliminated, engineers are helped to quickly and accurately lock the processing machine tables, more influence on batch production is prevented, and the product yield is improved.

Description

Method for distinguishing fault defect source of chemical mechanical polishing layer
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for distinguishing fault defect sources of a chemical mechanical polishing layer.
Background
As the manufacturing process is smaller and smaller, the loss rate of the yield of the product caused by the defect of the Chemical Mechanical Polishing (CMP) layer in the back-end process approaches 100%, and more than one machine causing the defect, for example, the pattern of the CMP layer is damaged due to the particles of the metal hard mask layer etching machine and the integrated etching machine, and an engineer may notify the wrong machine or notify a plurality of machines of downtime in the actual operation process, which may result in the yield loss of the product or the yield loss of the machines.
The existing detection and classification method is based on ADC (auto Defect classification) server automatic classification, the traditional ADC classification mainly establishes a method in the early stage, then uses a large amount of Defect data as a database, and the later stage SEM machine defines the outline information of the Defect according to the different gray scales of the Defect and the background during automatic identification, and then matches the outline information with the information in the database for classification; the prior art cannot help engineers lock whether the defect source occurs in Metal Hard Mask ETCH (Metal Hard Mask ETCH) or in-line etching (AIO ETCH), and in the actual operation process, wrong machines or multiple machines are notified, so that yield loss of partial products or loss of productivity of the machines is caused.
The prior art has the following disadvantages:
(1) the shapes of the particles are varied, so that the profiles of the fault defects of the chemical mechanical polishing layer are different in shape; the accuracy (precision) of ADC classification can only reach about 90%;
(2) the current ADC technology can only simply classify defects and can not classify sources formed by the defects, and due to a Chemical Mechanical Polishing (CMP) grinding process, a part of previous layer information of a pattern is lost, so that troubles are often brought to judgment of engineers.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention aims to provide a method for distinguishing the defect source of the cmp layer failure, which is used to solve the problems of the prior art that the ADC classification accuracy is low, and only the defect can be classified, and the source of the defect formation cannot be classified.
To achieve the above and other related objects, the present invention provides a method for distinguishing the source of pattern defect in CMP layer, comprising:
the method comprises the steps of firstly, obtaining design information of a product chip, and obtaining a first characteristic diagram according to the design information, wherein different positions of the first characteristic diagram correspond to different process machines respectively;
obtaining a graph of a wafer, wherein the size proportion of the graph of the wafer is the same as that of the first characteristic diagram, and the graph of the wafer is endowed with a coordinate origin which is the same as that of the first characteristic diagram, so that a second characteristic diagram is obtained;
step three, importing the second characteristic diagram into a database of an ADC (analog to digital converter) server, so that the ADC server obtains defect coordinates in the second characteristic diagram, wherein the database carries out defect code classification according to defect types generated by different process machines;
fourthly, the ADC server classifies the defect coordinate, and the defect coordinate is matched with the coordinate of the first feature map, so that the position of the defect coordinate on the first feature map is obtained through comparison;
and step five, determining the process machine table corresponding to the defect coordinate according to the defect code in the step three.
Optionally, the process machine in the first step includes a metal hard mask layer etching machine and an integrated etching machine.
Optionally, the graph of the wafer in the second step is obtained by introducing a scanning machine or external information.
Optionally, the defect coordinates in step three are automatically identified by the SEM machine.
Optionally, when the ADC in step three does not detect the occurrence of the defect on the wafer, the process tool continues to operate.
Optionally, the design information in the first step is a layout of a product chip, and the first characteristic diagram is obtained by CAD drawing according to the layout.
Optionally, the second feature map in step three is inputted into the ADC server in text form.
As mentioned above, the method for distinguishing the fault defect source of the chemical mechanical polishing layer of the invention has the following beneficial effects:
the ADC classification method can automatically and accurately classify by circulation, eliminates human intervention, and overcomes the defect that the classification accuracy of the ADC cannot reach 100% in the prior art; the method can help engineers quickly and accurately lock the processing machine, prevent more influence on batch generation and improve the product yield; the problem that the yield of a semiconductor factory is lost due to the fact that Hl downtime inspection is carried out on a plurality of processing machines together is avoided; the working state of the processing machine can be monitored more accurately, and the stability of the process is improved.
Drawings
FIG. 1 is a schematic flow chart of the process of the present invention;
FIG. 2 is a schematic view of a hard metal mask layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a metal via opening pattern in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram showing coordinates assigned to a graphic according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating matching coordinates of a first feature map according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating a defect location determination according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating the location of a fault station for identifying defects according to an embodiment of the present invention.
Wherein 101-a first characteristic diagram, 102-a second characteristic diagram and 103-a defect coordinate.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Referring to fig. 1, the present invention provides a method for distinguishing the source of a cmp patterning defect, comprising:
the method comprises the steps of firstly, obtaining design information of a product chip, and obtaining a first characteristic diagram 101 according to the design information, wherein different positions of the first characteristic diagram 101 correspond to different process machines respectively, and the types of defects generated by the different process machines are different;
specifically, the design information of the chip includes a design layout of the chip, and the first characteristic diagram 101 is obtained by drawing through CAD according to each part in the design layout, wherein devices of each part correspond to different process machines, and when processing, because particles damage the part during chemical mechanical polishing, large quantities of defect data caused in different process machines are used as a database.
Referring to fig. 2 and 3, in one possible embodiment, information related to the product chip is obtained and a CAD is used to map the features, wherein fig. 2 is a graph developed by metal hard mask layer lithography (M × PH) and fig. 3 is a graph developed by metal via lithography (V × PH), it should be understood that more types of process tools may be used herein.
Step two, obtaining a graph of the wafer, wherein the graph of the wafer is subjected to scaling and other processing and has the same size proportion as the first characteristic diagram 101, the graph of the wafer can be obtained by a scanning machine and can also be obtained through external data input, the graph of the wafer is given by the same coordinate origin as the first characteristic diagram 101, so that a second characteristic diagram 102 is obtained, the coordinate axis of the second characteristic diagram 102 is the same as the coordinate axis of the first characteristic diagram 101, and the first characteristic diagram 101 can be used as a reference system, so that the position, corresponding to the product chip design layout, on the second characteristic diagram 102 is obtained;
referring to FIG. 4, in one possible embodiment, the same origin of coordinates as the scanning tool is selected and assigned to the corresponding coordinates of the pattern.
Step three, importing the second characteristic diagram 102 into a database of an ADC server in the prior art in a text form, so that an SEM machine in the ADC server can automatically identify, wherein the database carries out defect code classification according to defect types generated by different process machines;
specifically, when the SEM machine performs automatic identification, the ADC server first defines the profile information of the defect according to the difference between the gray scales of the defect and the background, and then performs classification by matching with the information in the database to obtain the defect coordinates 103 of the defect occurring location in the second feature map 102, and when the ADC does not detect the defect occurring on the wafer, the process machine continues to operate.
It should be understood that the ADC server herein may be replaced with another detection classification device.
Step four, when the ADC server classifies, matching the defect coordinate 103 of the defect position in the second characteristic diagram 102 with the coordinate of the first characteristic diagram 101, so as to obtain the position of the defect coordinate 103 on the first characteristic diagram 101 through comparison;
referring to fig. 5 and 6, in one possible embodiment, the ADC server matches the defect coordinates 103 information to the CAD first feature map 101 coordinates during the identification process to confirm that the defect is in a pattern revealed by the metal hard mask layer lithography (M × PH).
And step five, determining the process machine table corresponding to the defect coordinate 103 according to the defect code in the step one, accurately determining the process machine table at the position where the fault occurs, and accurately locking the fault machine table.
Referring to FIG. 7, in one possible embodiment, the location of the fault causing the defect is identified in the metal hard mask layer etching tool.
It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In conclusion, the invention can automatically and accurately classify by circulation, eliminates human intervention, and overcomes the defect of low ADC classification accuracy in the prior art; the method can help engineers quickly and accurately lock the processing machine, prevent more influence on batch generation and improve the product yield; the problem that the yield of a semiconductor factory is lost due to the fact that Hl downtime inspection is carried out on a plurality of processing machines together is avoided;
the working state of the processing machine can be monitored more accurately, and the stability of the process is improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (7)

1. A method for distinguishing the source of a defect in a cmp layer, comprising:
the method comprises the steps of firstly, obtaining design information of a product chip, and obtaining a first characteristic diagram according to the design information, wherein different positions of the first characteristic diagram correspond to different process machines respectively;
obtaining a graph of a wafer, wherein the size proportion of the graph of the wafer is the same as that of the first characteristic diagram, and the graph of the wafer is endowed with a coordinate origin which is the same as that of the first characteristic diagram, so that a second characteristic diagram is obtained;
step three, importing the second characteristic diagram into a database of an ADC (analog to digital converter) server, so that the ADC server obtains defect coordinates in the second characteristic diagram, wherein the database carries out defect code classification according to defect types generated by different process machines;
fourthly, the ADC server classifies the defect coordinate, and the defect coordinate is matched with the coordinate of the first feature map, so that the position of the defect coordinate on the first feature map is obtained through comparison;
and step five, determining the process machine table corresponding to the defect coordinate according to the defect code in the step three.
2. The method for distinguishing the source of the defect in the CMP layer according to claim 1, wherein: the process machine in the first step comprises a metal hard mask layer etching machine and an integrated etching machine.
3. The method for distinguishing the source of the defect in the CMP layer according to claim 1, wherein: and the graph of the wafer in the second step is obtained through a scanning machine.
4. The method for distinguishing the source of the defect in the CMP layer according to claim 1, wherein: and the defect coordinates in the third step are automatically identified by an SEM machine.
5. The method for distinguishing the source of the defect in the CMP layer according to claim 1, wherein: and when the ADC in the third step does not detect that the defects occur on the wafer, the process machine continues to work.
6. The method for distinguishing the source of the defect in the CMP layer according to claim 1, wherein: and the design information in the step one is a layout of a product chip, and the first characteristic diagram is obtained by CAD drawing according to the layout.
7. The method for distinguishing the source of the defect in the CMP layer according to claim 1, wherein: the second feature map in step three is entered into the ADC server in text form.
CN202111327433.4A 2021-11-10 2021-11-10 Method for distinguishing fault defect source of chemical mechanical polishing layer Pending CN114121701A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111327433.4A CN114121701A (en) 2021-11-10 2021-11-10 Method for distinguishing fault defect source of chemical mechanical polishing layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111327433.4A CN114121701A (en) 2021-11-10 2021-11-10 Method for distinguishing fault defect source of chemical mechanical polishing layer

Publications (1)

Publication Number Publication Date
CN114121701A true CN114121701A (en) 2022-03-01

Family

ID=80378129

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111327433.4A Pending CN114121701A (en) 2021-11-10 2021-11-10 Method for distinguishing fault defect source of chemical mechanical polishing layer

Country Status (1)

Country Link
CN (1) CN114121701A (en)

Similar Documents

Publication Publication Date Title
TWI755613B (en) Pattern grouping method based on machine learning
US8595666B2 (en) Semiconductor defect classifying method, semiconductor defect classifying apparatus, and semiconductor defect classifying program
US7593565B2 (en) All surface data for use in substrate inspection
KR101331249B1 (en) Method and apparatus for manufacturing data indexing
CN109923654B (en) Wafer noise reduction by cross-layer image subtraction
KR20060063929A (en) Dynamic metrology sampling methods
WO2017123888A1 (en) Improving defect sensitivity of semiconductor wafer inspectors using design data with wafer image data
CN109844916A (en) Defect based on defect and design attributes inspects sampling and standardization
US7174281B2 (en) Method for analyzing manufacturing data
CN112802771A (en) Defect detection wafer map optimization method and optimization system thereof
CN114300377A (en) Yield loss acquisition system and method for non-pattern wafer
CN111653500A (en) Method for judging wafer yield loss
US9940704B2 (en) Pre-layer defect site review using design
US6754593B1 (en) Method and apparatus for measuring defects
CN111539955A (en) Defect detection method
CN113609814A (en) Wafer yield loss prediction method and self-defined defect density graph self-reporting system
CN114121701A (en) Method for distinguishing fault defect source of chemical mechanical polishing layer
CN117197617A (en) Defect classification method and system for repeated defects
TWI409661B (en) Method for utilizing fabrication defect of an article
US10957608B2 (en) Guided scanning electron microscopy metrology based on wafer topography
US6944573B2 (en) Method and apparatus for the analysis of scratches on semiconductor wafers
CN110741466B (en) Broadband plasma verification based on a perturbed dot pattern
CN113314430B (en) Monitoring method and monitoring system in CMP (chemical mechanical polishing) process
US20230411224A1 (en) System and method for detecting defects on a wafer and related non-transitory computer-readable medium
CN113916903A (en) Defect detection method and system

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination