CN114121666A - Groove isolation method of fin field effect transistor, field effect transistor and processing equipment - Google Patents
Groove isolation method of fin field effect transistor, field effect transistor and processing equipment Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
- H01L21/76229—Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Abstract
The invention belongs to the technical field of microelectronics, and discloses a slot isolation method of a fin field effect transistor, a field effect transistor corresponding to the slot isolation method and processing equipment; by improving the manufacturing process flow, the height of the isolation area is expanded, potential bridging risks among working areas are avoided, the size of the characteristic pattern is further reduced, and the performance of a product and the utilization rate of a wafer are improved; through constructing the isolation groove and carrying out two filling and etching processes, the structure of the fin type working area is ensured on one hand, and the range of the isolation area is expanded on the other hand; the method can be put into production with a DDB co-production line in a double diffusion region isolation mode, and is beneficial to upgrading and maintaining the existing SDB system.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a slot isolation method of a fin type field effect transistor, the field effect transistor and processing equipment.
Background
The isolation difficulty of the diffusion region is increased continuously due to the continuous reduction of the characteristic size of the device; the adoption of an effective isolation structure is not only required for improving functions, but also enables the integration level of the device to be further improved. The trench isolation method in the prior art has a bridging risk between the PO and the epitaxy, and it is necessary to overcome this technical problem by improving the process.
Disclosure of Invention
The invention discloses a slot isolation method of a fin field effect transistor, the field effect transistor adopting the method and corresponding processing equipment.
The isolation method comprises the steps of constructing a first isolation groove to obtain a first intermediate piece; the first isolation groove structure process comprises a first photoetching and a first etching.
Then, filling the first medium into the first isolation groove until the first medium covers the surface of the first intermediate piece; then, performing first polishing treatment to obtain a second intermediate piece;
then depositing a second medium on the surface of the second intermediate piece to obtain a third intermediate piece; and further etching the third intermediate piece, opening the first isolation groove and exposing the first medium in the first isolation groove to form a first intermediate groove and obtain a fourth intermediate piece.
Further, filling a first medium into the first middle groove, and coating the surface layer of the fourth middle piece to obtain a fifth middle piece; polishing the surface of the fifth intermediate piece; meanwhile, removing the first medium on the surface of the fifth intermediate piece except the top of the first intermediate groove to obtain a sixth intermediate piece; and removing the second medium on the surface of the sixth intermediate piece.
So far, the first medium in the first middle groove forms a first bulge, and a seventh middle piece is obtained; the first medium of the first bulge and the first medium in the first isolation groove jointly form a first isolation part.
Further, etching the first dielectric layer on the surface of the seventh intermediate piece, and opening the fin-type component to obtain an eighth intermediate piece; and aligning the eighth intermediate member, transferring the first feature and obtaining a multilayer structure, thereby obtaining a ninth intermediate member.
The additional process further includes constructing a first work area to obtain a tenth intermediate member; and constructing a second working area to obtain an eleventh intermediate piece.
Further, the construction process of the first working area may include construction of the SiP; the process of constructing the second active region may include the construction of SiGe; the first feature of the method comprises PO layout features.
Further, the second isolation groove may be constructed by synchronizing with the construction step of the first isolation groove. Wherein, the second isolation groove may be a DDB structure; i.e. a double diffusion cut-off structure.
Specifically, the first medium may be filled into the first isolation groove through an FCVD process; the first polishing process is performed by a CMP (chemical Mechanical polishing) process corresponding to STI (shallow Trench isolation).
Further, the first medium can be filled by adopting a deposition method; the first intermediate groove is in an SDB structure, namely a single diffusion area cutting structure.
Further, the first dielectric may be an oxide, an oxide layer and/or an oxide film; the method for obtaining and/or filling the oxide comprises thermal oxidation; the second dielectric may be a metal oxide.
Furthermore, the method is used for the manufacturing process that the layout characteristic dimension is smaller than 28 nm; the filling process comprises a process based on epitaxy and/or ion implantation; the photoetching comprises an electron beam direct writing mode. In particular, the method can be effectively implemented for the process with the layout characteristic size of 14 nm.
In addition, the embodiment of the invention also discloses a fin field effect transistor, and the fin grid structure removed from the fin is isolated by adopting any method of the invention; the isolation trench can adopt an STI structure.
In particular, the first dielectric of the field effect transistor may comprise a metal nitride or other material with high dielectric properties.
The embodiment of the transistor processing equipment corresponding to the method of the invention can comprise a groove structure preparation unit and a functional area linking unit.
The groove structure preparation unit obtains a first intermediate piece by constructing a first isolation groove; the first isolation groove structure manufacturing process comprises first photoetching and first etching; filling a first medium into the first isolation groove until the first medium covers the surface of the first intermediate piece; and then, performing the first polishing treatment to obtain a second intermediate piece.
Depositing a second medium on the surface of the second intermediate piece to obtain a third intermediate piece; and etching the third intermediate piece, opening the first isolation groove, exposing the first medium in the first isolation groove, forming a first intermediate groove, and obtaining a fourth intermediate piece.
Further filling a first medium in the first middle groove and coating the surface layer of the fourth middle piece to obtain a fifth middle piece; and polishing the surface of the fifth intermediate piece, and simultaneously removing the first medium outside the groove top of the first intermediate groove on the surface of the fifth intermediate piece to obtain a sixth intermediate piece.
The functional area link unit further removes the second medium from the surface of the sixth intermediate member. Wherein the first medium inside the first intermediate groove forms a first bulge and a seventh intermediate piece is obtained; the first medium of the first bulge and the first medium in the first isolation groove jointly form a first isolation part.
Further, etching the first dielectric layer on the surface of the seventh intermediate piece, and opening the fin-type component to obtain an eighth intermediate piece; by aligning the eighth intermediate member, the first feature is transferred and a multilayer structure is obtained, thereby obtaining a ninth intermediate member.
Wherein, the first middle groove is in an SDB structure, namely a single diffusion region cutting structure; the first medium is an oxide, an oxidation layer and/or an oxidation film; the oxide pick-up and/or fill process includes thermal oxidation; the second medium is a metal oxide.
It should be noted that the method disclosed by the embodiment of the invention is suitable for a process in which the layout characteristic dimension is less than 28 nm; the filling process comprises a process based on epitaxy and/or ion implantation; the lithography process includes electron beam direct writing.
Further, in order to realize a corresponding circuit structure, a tenth middleware may be obtained by constructing the first working area; obtaining an eleventh middleware by constructing a second working area; wherein: the construction process of the first working area comprises the construction of SiP; the construction process of the second working area comprises the construction of SiGe; the first feature of the method comprises PO layout features.
Further, the first medium can be filled into the first isolation groove through an FCVD process; the first polishing process employs a CMP method corresponding to STI.
Further, the apparatus disclosed in the embodiment of the present invention may further include a double diffusion region cutoff DDB unit which constructs the second isolation trench in synchronization with the step of constructing the first isolation trench; the second isolation groove is a DDB structure, namely a double-diffusion cutting-off structure; the method can be used for the process with the characteristic dimension of 14nm of the layout structure.
By introducing the SBD structure disclosed by the embodiment of the method, the height of the isolation region is increased, and the bridging risk of the peripheral region in the etching process is avoided; in addition, since SBD saves more space than DDB; thus, devices employing this method will have a higher degree of integration and occupy less wafer area.
It should be noted that the terms "first", "second", and the like are used herein only for describing the components in the technical solution, and do not constitute a limitation on the technical solution, and are not understood as an indication or suggestion of the importance of the corresponding component; an element in the similar language "first", "second", etc. means that in the corresponding embodiment, the element includes at least one.
Drawings
To more clearly illustrate the technical solutions of the present invention and to facilitate further understanding of the technical effects, technical features and objects of the present invention, the present invention will be described in detail with reference to the accompanying drawings, which form an essential part of the specification, and which are used together with the embodiments of the present invention to illustrate the technical solutions of the present invention, but do not limit the present invention.
The same reference numerals in the drawings denote the same elements, and in particular:
FIG. 1 is a schematic diagram illustrating an isolation trench etching process according to an embodiment of the present invention;
FIG. 2 is a schematic view of trench filling and surface polishing according to an embodiment of the present invention;
FIG. 3 is a schematic illustration of a process dielectric layer deposition according to an embodiment of the invention;
FIG. 4 is a schematic diagram illustrating a trench expanding step etching process according to an embodiment of the present invention;
FIG. 5 is a schematic diagram illustrating an intermediate result of a deposition of a dielectric in a trench according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating the oxide layer being removed according to the embodiment of the present invention;
FIG. 7 is a schematic view of an isolation structure according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a fin gate structure according to an embodiment of the present invention;
FIG. 9 is a structural diagram of a PO functional layer according to an embodiment of the invention;
FIG. 10 is a schematic diagram of an active area AA (active area) SiP structure according to an embodiment of the present invention;
FIG. 11 is a schematic diagram of a SiGe structure according to an embodiment of the present invention;
FIG. 12 is a schematic illustration of a prior art barrier performance weakness region I;
FIG. 13 is a schematic illustration of a prior art barrier performance weak area II;
FIG. 14 is a schematic diagram of an isolation structure with active working areas according to an embodiment of the present invention;
FIG. 15 is an electron microscope image of a single and double isolation structure according to an embodiment of the present invention;
FIG. 16 is a schematic diagram of a single-double isolation structure according to an embodiment of the present invention;
FIG. 17 is a flow chart of a method of an embodiment of the present invention;
FIG. 18 is a block diagram of an apparatus according to an embodiment of the present invention; wherein:
10-a process tank construction step, 11-a pre-process unit;
20-a process groove first filling step, 22-a groove structure preparation unit;
30-process reconfiguration step, functional area linking unit;
40-a process tank refilling step, 44-a post-tightening process unit;
50-process transition step;
100-a first intermediate, 101-a first isolation slot, 111-a first isolation feature;
200-a second intermediate piece of material,
201-first medium in first isolation tank, 202-first medium in second isolation tank;
300-a third intermediate piece of material,
301-the second medium at the periphery of the top end of the first isolation trench, 302-the second medium at the periphery of the top end of the second isolation trench;
400-fourth intermediate piece, 401-first intermediate groove;
500-fifth middleware; 600-sixth middleware;
700-seventh intermediate, 701-first boss;
800-eighth intermediate, 801-fin structure local;
900-ninth middleware, 901, 902, 903-a multi-layer structure linked to a first spacer component;
a00-tenth intermediate, A01-first work area;
b00-eleventh intermediate, B01-second work area;
c00-a twelfth intermediate piece,
x00-prior art SBD and DDB structures,
X01-SDB structure of prior art, X02-DDB structure of prior art;
y00-open SBD and DDB structures of the prior art,
u00-single and double isolation structure electron microscope picture, V00-single and double isolation structure schematic view;
DDB1, DDB 2-double isolation structure, SDB1, SDB 2-single isolation structure.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. Of course, the following specific examples are provided only for explaining the technical solutions of the present invention, and are not intended to limit the present invention. In addition, the portions shown in the embodiments or the drawings are only illustrations of the relevant portions of the present invention, and are not all of the present invention.
As shown in fig. 17, a flow chart of an embodiment of the method of the present invention is presented, with a pair of alternating build and fill processes, to build a corresponding isolation structure.
Specifically, as shown in fig. 1, first, a first isolation groove 101 is constructed, resulting in a first intermediate member 100; the first isolation trench 101 is formed by a first photolithography and a first etching; in addition, the construction process can be synchronously carried out with the DDB structure, so that the realization mode of the corresponding process and the flexibility of modification and upgrading are enriched.
As shown in fig. 2, the first medium 201, 202 is filled into the first isolation groove 101 until the first medium 201, 202 covers the surface of the first intermediate member 100; the first polishing process is then performed to obtain the second intermediate member 200.
As shown in fig. 3, a second medium 301, 302 is deposited on the surface of the second intermediate member 200, resulting in a third intermediate member 300, and a lithographic work plane is reserved for further raising the height of the isolation trench.
Further, as shown in fig. 4, a first intermediate trench 401 is formed by etching the third intermediate piece 300, opening the first isolation trench 101, and exposing the first dielectric 201 in the first isolation trench 101, and obtaining a fourth intermediate piece 400.
As shown in fig. 5, a fifth intermediate member 500 is obtained by filling the first medium 201 in the first intermediate groove 401 and coating the surface layer of the fourth intermediate member.
As in fig. 6, by polishing the surface of the fifth intermediate member 500; meanwhile, the first medium 201 except the top of the first middle groove 401 on the surface of the fifth middle piece 500 is removed, and a sixth middle piece 600 is obtained.
As shown in fig. 7, the second medium 301 and 302 on the surface of the sixth middleware 600 are further removed; therein, the first medium 201 inside the first intermediate tank 401 forms the first protrusion 701 and results in the seventh intermediate piece 700.
The first dielectric 201 of the first protrusion 701 and the first dielectric 201 inside the first isolation groove 101 together form the first isolation member 111.
Further, as shown in fig. 8, fin feature 801 is opened by etching first dielectric layer 201 on the surface of seventh interposer 700, resulting in eighth interposer 800.
Further, as shown in fig. 9, by aligning the eighth intermediate member 800, the first feature is transferred and the multilayer structures 901, 902, 903 are obtained, thereby obtaining a ninth intermediate member 900.
Further, as shown in fig. 10, by constructing the first working area a01, a tenth intermediate member a00 is obtained; by constructing the second working space B01, an eleventh intermediate member B00 is obtained.
Further, as shown in fig. 11, the construction process of the first working area includes the construction of SiP; the construction process of the second working area comprises the construction of SiGe; wherein: the first feature comprises a PO layout feature.
As shown in fig. 1, the second isolation trenches 102 may be constructed in synchronization with the construction steps of the first isolation trenches 102.
As shown in fig. 1-11, the second isolation trench 102 is a DDB structure; namely a double diffusion cut-off structure; the first medium 201 can be filled into the first isolation groove 101 through an FCVD process; the first polishing treatment may employ CMP corresponding to STI; wherein STI is a shallow trench isolation structure and CMP is a chemical mechanical polishing process.
Further, the first medium 201, 202 may be filled by deposition; the first intermediate trench 401 is an SDB structure, i.e., a single diffusion region cutoff structure.
As in fig. 1-11, the first dielectric 201, 202 may be an oxide, oxide layer and/or oxide film; the oxide pick-up and/or fill process includes thermal oxidation; the second dielectrics 301, 302 are metal oxides.
The method of the embodiment can be used for the manufacture procedure that the characteristic dimension of the layout is less than 28 nm; the filling process comprises a process based on epitaxy and/or ion implantation; the photoetching also comprises an electron beam direct writing mode.
Furthermore, the method is suitable for the process with the layout characteristic dimension of 14 nm.
The embodiment of the invention also discloses a fin field effect transistor: the fin gate structure is isolated by any method of the invention. In addition, the isolation trench of the embodiment of the invention can adopt an STI structure; the first dielectric may also comprise a metal nitride or other material with high dielectric properties.
As shown in fig. 18, an embodiment of the present invention further discloses a transistor processing apparatus, including: a slot structure preparation unit 22 and a functional area linking unit 33.
As shown in fig. 1 to 11, the groove structure preparation unit 22 thereof constructs a first isolation groove 101, resulting in a first intermediate member 100; the first isolation trench 101 is formed by a first photolithography and a first etching; filling the first mediums 201 and 202 into the first isolation groove 101 until the first mediums 201 and 202 cover the surface of the first intermediate member 100; then, performing a first polishing process to obtain a second intermediate piece 200; depositing second mediums 301 and 302 on the surface of the second intermediate piece 200 to obtain a third intermediate piece 300; etching the third intermediate piece 300, opening the first isolation groove 101, and exposing the first medium 201 in the first isolation groove 101 to form a first intermediate groove 401, and obtaining a fourth intermediate piece 400; filling a first medium 201 in the first middle groove 401, and coating the surface layer of the fourth middle part to obtain a fifth middle part 500; polishing the surface of the fifth intermediate member 500; meanwhile, the first medium 201 except the top of the first middle groove 401 on the surface of the fifth middle piece 500 is removed, and a sixth middle piece 600 is obtained.
Further, the functional area link unit 33 removes the second media 301, 302 on the surface of the sixth middleware 600; wherein the first medium 201 inside the first intermediate groove 401 forms a first protrusion 701 and results in a seventh intermediate piece 700; the first medium 201 of the first protruding portion 701 and the first medium 201 inside the first isolation groove 101 together form a first isolation component 111; further, the fin component 801 is opened by etching the first dielectric layer 201 on the surface of the seventh intermediate component 700, so that an eighth intermediate component 800 is obtained; aligning eighth intermediary 800, transferring the first features and obtaining a multilayer structure 901, 902, 903, thus obtaining ninth intermediary 900; wherein, the first intermediate trench 401 is an SDB structure, i.e., a single diffusion region cut-off structure; the first dielectrics 201 and 202 are oxides, oxide layers and/or oxide films; the oxide pick-up and/or fill process includes thermal oxidation; the second dielectrics 301 and 302 are metal oxides; the method is used for the manufacturing process that the layout characteristic dimension is less than 28 nm; the filling process comprises a process based on epitaxy and/or ion implantation; the photoetching comprises an electron beam direct writing mode.
Further, by constructing the first working area a01, a tenth intermediate piece a00 is obtained; constructing a second working area B01, resulting in an eleventh intermediate piece B00; wherein the construction process of the first working area comprises the construction of SiP; the construction process of the second working area comprises the construction of SiGe; the first feature comprises a PO layout feature.
Further, the first medium 201 may be filled into the first isolation groove 101 through an FCVD process; the first polishing treatment adopts CMP corresponding to STI; wherein, STI is a shallow trench isolation structure, and CMP is a chemical mechanical polishing process; the first dielectric 201, 202 is filled by deposition.
The double diffusion region cut-off DDB unit thereof constructs the second isolation trench 102 in synchronization with the construction step of the first isolation trench 102; the second isolation trench 102 is a DDB structure; namely a double diffusion cut-off structure; the equipment can be used for the process with the characteristic dimension of 14nm of layout structure.
It should be noted that the above examples are only for clearly illustrating the technical solutions of the present invention, and those skilled in the art will understand that the embodiments of the present invention are not limited to the above contents, and obvious changes, substitutions or replacements can be made based on the above contents without departing from the scope covered by the technical solutions of the present invention; other embodiments will fall within the scope of the invention without departing from the inventive concept.
Claims (18)
1. A method for isolating a trench of a fin field effect transistor (FinFET), comprising:
constructing a first isolation groove (101) to obtain a first intermediate piece (100); wherein the first isolation groove (101) structure process comprises first photoetching and first etching;
filling a first medium (201, 202) into the first isolation groove (101) until the first medium (201, 202) covers the surface of the first intermediate piece (100); then, performing the first polishing treatment to obtain a second intermediate piece (200);
depositing a second medium (301, 302) on the surface of the second intermediate piece (200) to obtain a third intermediate piece (300);
etching the third intermediate piece (300), opening the first isolation groove (101), and exposing the first medium (201) in the first isolation groove (101) to form a first intermediate groove (401), and obtaining a fourth intermediate piece (400);
filling the first medium (201) into the first middle groove (401), and coating the surface layer of the fourth middle part to obtain a fifth middle part (500);
polishing the fifth intermediate piece (500) surface; simultaneously, removing the first medium (201) on the surface of the fifth intermediate piece (500) except the top of the first intermediate groove (401), and obtaining a sixth intermediate piece (600);
removing the second medium (301, 302) from the surface of the sixth intermediate piece (600); wherein the first medium (201) inside the first intermediate tank (401) forms a first protrusion (701) and results in a seventh intermediate piece (700);
wherein the first dielectric (201) of the first protrusion (701) constitutes a first isolation member (111) in combination with the first dielectric (201) inside the first isolation trench (101).
2. The method of claim 1, further comprising:
etching the first dielectric layer (201) on the surface of the seventh intermediate piece (700), and opening a fin-type component (801) to obtain an eighth intermediate piece (800);
aligning said eighth intermediate piece (800), transferring the first features and obtaining a multilayer structure (901, 902, 903), thereby obtaining a ninth intermediate piece (900).
3. The method of claim 2, further comprising:
constructing a first work area (A01) resulting in a tenth intermediate piece (A00);
the second working area (B01) is constructed, resulting in an eleventh intermediate member (B00).
4. The method of claim 3, wherein:
the construction process of the first working area comprises the construction of SiP;
the second active region is constructed by a process including SiGe construction.
5. The method of claim 2, wherein:
the first feature comprises a PO layout feature.
6. The method of claim 1, wherein:
in synchronism with the step of constructing the first isolation tank (102), a second isolation tank (102) is constructed.
7. The method of claim 6, wherein:
the second isolation groove (102) is of a DDB structure; the DDB is a double-diffusion cut-off structure.
8. The method of claim 1, wherein:
the first medium (201) is filled into the first isolation groove (101) through an FCVD process;
the first polishing treatment adopts CMP corresponding to STI; wherein the STI is a shallow trench isolation structure, and the CMP is a chemical mechanical polishing process.
9. The method of claim 8, wherein:
the first medium (201, 202) is filled by adopting a deposition method;
the first middle groove (401) is of an SDB structure, and the SDB is of a single diffusion region cutting structure.
10. The method of claim 8, wherein:
the first medium (201, 202) is an oxide, an oxide layer and/or an oxide film; the method of obtaining and/or filling the oxide comprises thermal oxidation;
the second dielectric (301, 302) is a metal oxide.
11. The method of any of claims 1 to 10, wherein:
the method is used for the manufacturing process that the characteristic dimension of the layout is less than 28 nm;
the filling process comprises a process based on epitaxy and/or ion implantation processes;
the lithography comprises an electron beam direct writing mode.
12. The method of claim 9 or 10 or 11, wherein:
the method is used for the manufacturing process with the layout characteristic dimension of 14 nm.
13. A fin field effect transistor, comprising:
a fin gate structure, the fin gate being isolated using any of the methods of claims 1-12.
14. The fet of claim 13, wherein:
the isolation trench adopts the STI structure; the first dielectric also includes a metal nitride or other material of high dielectric properties.
15. A transistor processing apparatus, comprising:
a groove structure preparation unit (22) and a functional region linking unit (33); wherein the content of the first and second substances,
the tank structure preparation unit (22) constructs a first isolation tank (101) to obtain a first intermediate member (100); wherein the first isolation groove (101) structure process comprises first photoetching and first etching; filling a first medium (201, 202) into the first isolation groove (101) until the first medium (201, 202) covers the surface of the first intermediate piece (100); then, performing the first polishing treatment to obtain a second intermediate piece (200); depositing a second medium (301, 302) on the surface of the second intermediate piece (200) to obtain a third intermediate piece (300); etching the third intermediate piece (300), opening the first isolation groove (101), and exposing the first medium (201) in the first isolation groove (101) to form a first intermediate groove (401), and obtaining a fourth intermediate piece (400); filling the first medium (201) into the first middle groove (401), and coating the surface layer of the fourth middle part to obtain a fifth middle part (500); polishing the fifth intermediate piece (500) surface; simultaneously, removing the first medium (201) on the surface of the fifth intermediate piece (500) except the top of the first intermediate groove (401), and obtaining a sixth intermediate piece (600);
the functional area link unit (33) removes the second medium (301, 302) from the surface of the sixth middleware (600); wherein the first medium (201) inside the first intermediate tank (401) forms a first protrusion (701) and results in a seventh intermediate piece (700); wherein the first dielectric (201) of the first protrusion (701) constitutes a first isolation member (111) in combination with the first dielectric (201) inside the first isolation trench (101).
16. The apparatus of claim 15, wherein:
etching the first dielectric layer (201) on the surface of the seventh intermediate piece (700), and opening a fin-type component (801) to obtain an eighth intermediate piece (800); aligning said eighth intermediate piece (800), transferring the first features and obtaining a multilayer structure (901, 902, 903), thus obtaining a ninth intermediate piece (900);
the first middle groove (401) is of an SDB structure, and the SDB is of a single diffusion region cutting structure; the first medium (201, 202) is an oxide, an oxide layer and/or an oxide film; the method of obtaining and/or filling the oxide comprises thermal oxidation; the second medium (301, 302) is a metal oxide; the method is used for the manufacturing process that the characteristic dimension of the layout is less than 28 nm; the filling process comprises a process based on epitaxy and/or ion implantation processes; the lithography comprises an electron beam direct writing mode.
17. The apparatus of claim 15, further comprising:
constructing a first work area (A01) resulting in a tenth intermediate piece (A00); constructing a second working area (B01) resulting in an eleventh intermediate piece (B00); wherein:
the construction process of the first working area comprises the construction of SiP; the construction process of the second working area comprises the construction of SiGe; the first features comprise PO layout features; the first medium (201) is filled into the first isolation groove (101) through an FCVD process; the first polishing treatment adopts CMP corresponding to STI; wherein the STI is a shallow trench isolation structure, and the CMP is a chemical mechanical polishing process; the first medium (201, 202) is filled by adopting a deposition method.
18. The apparatus of claim 15, further comprising:
the double diffusion region cuts off the DDB cell,
the double diffusion region cut-off DDB cell is synchronized with the construction step of the first isolation trench (102), and a second isolation trench (102) is constructed; the second isolation groove (102) is of a DDB structure; the DDB is a double-diffusion cutting structure; wherein: the equipment is used for the manufacturing process of which the characteristic dimension of the layout structure is 14 nm.
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| US20160079125A1 (en) * | 2014-09-11 | 2016-03-17 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| CN108400167A (en) * | 2017-05-08 | 2018-08-14 | 格芯公司 | The fin formula field effect transistor and method interrupted with single diffusion |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20160079125A1 (en) * | 2014-09-11 | 2016-03-17 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods of manufacturing the same |
| CN108400167A (en) * | 2017-05-08 | 2018-08-14 | 格芯公司 | The fin formula field effect transistor and method interrupted with single diffusion |
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