CN114121639A - Manufacturing method of smooth groove and smooth groove structure - Google Patents

Manufacturing method of smooth groove and smooth groove structure Download PDF

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Publication number
CN114121639A
CN114121639A CN202010881132.5A CN202010881132A CN114121639A CN 114121639 A CN114121639 A CN 114121639A CN 202010881132 A CN202010881132 A CN 202010881132A CN 114121639 A CN114121639 A CN 114121639A
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Prior art keywords
etching
mask layer
dry etching
groove
trench
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Inventor
王志成
龚芷玉
刘启军
罗烨辉
周才能
宋瓘
曹申
赵艳黎
郑昌伟
李诚瞻
罗海辉
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Zhuzhou CRRC Times Semiconductor Co Ltd
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Priority to CN202010881132.5A priority Critical patent/CN114121639A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
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    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

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Abstract

The invention provides a method for manufacturing a smooth groove and a smooth groove structure, wherein the method comprises the following steps: the method comprises the steps of firstly etching the semiconductor wafer by a first dry etching method mainly based on anisotropy through the mask layer to form a groove structure with steep side walls and smooth bottom, then removing the first mask layer, and etching the semiconductor wafer by a second dry etching method mainly based on isotropy under the condition of no protection of the mask layer to smooth the top and the bottom of the groove, and finally forming the groove with steep side walls and smooth top and bottom. Therefore, the groove manufacturing method provided by the invention has simple process steps, can greatly improve the process efficiency and save the cost, and the smooth groove structure provided by the invention can not only improve the performance and the reliability of a device, but also bring convenience for the subsequent growth and filling processes in the groove.

Description

Manufacturing method of smooth groove and smooth groove structure
Technical Field
The invention belongs to the technical field of semiconductor grooves, and particularly relates to a manufacturing method of a smooth groove and a smooth groove structure.
Background
With the wide application of trench isolation and trench gate structures in semiconductor devices, the influence of the trench process on the performance of the semiconductor device is crucial. Because of its high hardness and chemical stability, the SiC semiconductor wafer is mostly subjected to a dry etching process.
As shown in fig. 1, the bottom of the trench formed by the conventional dry etching process is not smooth enough, and a micro-trench (indicated by a dashed circle in fig. 1) also exists at the boundary between the bottom of the trench and the sidewall of the trench, and the entire dry etching process is performed under the protection of the mask layer, and after the mask layer is removed, the top of the trench is at a right angle of 90 degrees, which causes inconvenience to the subsequent process and affects the performance and reliability of the device.
Disclosure of Invention
In view of the above, the present invention provides a method for fabricating a smooth trench and a structure of the smooth trench, so as to solve the problem that the bottom and the top of the trench formed by the conventional trench process are not smooth enough to affect the device performance.
A method for manufacturing a round trench comprises the following steps:
forming a patterned mask layer on a first surface of a semiconductor wafer, the mask layer exposing a trench region of the semiconductor wafer,
carrying out a first dry etching process by taking the surface of the groove region as an etching starting surface, and adjusting the first dry etching parameters to ensure that the etching mode of the first dry etching process is mainly anisotropic so as to form a groove with a steep side wall and a smooth bottom in the groove region of the semiconductor wafer,
the mask layer is removed and the mask layer is removed,
and carrying out second dry etching by taking the first surface as an etching initial surface, and adjusting the parameters of the second dry etching to ensure that the etching mode of the second dry etching process is mainly isotropic etching, so that the upper part and the bottom of the groove become a smooth structure.
Preferably, the step of forming a patterned mask layer on the first surface of the semiconductor wafer comprises:
performing a deposition process to form a mask layer on the entire first surface,
coating a patterned photoetching barrier layer on the surface of the mask layer, wherein the photoetching barrier layer exposes the surface of the part of the mask layer in the groove region,
and carrying out a photoetching process on the first surface through the photoetching barrier layer to pattern the mask layer so as to remove the part of the mask layer in the groove region, so that the surface of the groove region is exposed by the mask layer.
Preferably, the semiconductor wafer is a silicon carbide wafer,
and selecting one material of polysilicon, amorphous silicon, aluminum nitride and silicon dioxide to form the mask layer.
Preferably, the first dry etching is performed by using a plasma etching machine, and the adjusting of the first dry etching parameters makes the etching manner of the first dry etching process mainly anisotropic, including:
during a first phase, introducing a first group of etching gases into a reaction chamber of the plasma etcher, and setting gas flow rates of various gases in the first group of etching gases so as to round an interface area of the bottom of the trench and the sidewall of the trench during the first phase, and during the first phase, setting the pressure of the reaction chamber to a first preset pressure, and setting upper electrode power and lower electrode power of the plasma etcher to a first preset power and a second preset power, so that the etching manner of the first dry etching is dominated by physical etching so as to form a trench with a straight sidewall during the first phase,
during a second stage, introducing a second group of reaction gases into the reaction chamber, setting the flow rate of each gas in the second group of reaction gases as a preset flow rate, setting the pressure of the reaction chamber as a second preset pressure, and setting the power of the upper electrode and the power of the lower electrode as a third preset power and a fourth preset power so as to round the bottom of the groove during the second stage,
the second preset pressure is greater than the first preset pressure, and the fourth preset power is less than the second preset power.
Preferably, the first reaction group gas comprises sulfur hexafluoride gas and oxygen gas, and the gas flow ratio of the sulfur hexafluoride gas to the oxygen gas is greater than 1:2 and less than 2: 1, the first preset pressure is not more than 5mTorr, and the first preset power is as follows: 800-: 300-500W of the reaction kettle is adopted,
the second set of reactant gases includes octafluorocyclobutene gas and argon, the flow rate of the octafluorocyclobutene gas is set as follows: 30-50sccm, and the flow rate of the argon gas is set as follows: 90-110sccm, the second preset pressure is 8-10mTorr, and the third preset power is: 600-: 100- & lt300 & gtW.
Preferably, the step of performing the second dry etching by using the plasma etching machine and adjusting the parameters of the second dry etching so that the etching manner of the second dry etching process is mainly isotropic includes:
and in the third stage, after the mask layer is removed, introducing a third group of etching gases into a reaction chamber of the plasma etching machine, setting the gas flow of each gas in the third group of etching gases, setting the pressure of the reaction chamber to be a third preset pressure, and setting the power of the upper electrode and the power of the lower electrode to be a fifth preset power and a sixth preset power, so that the effect of physical etching is weakened in the third stage, and the etching mode of the second dry etching is mainly chemical etching.
Preferably, the third group of reaction gases includes sulfur hexafluoride gas, oxygen gas and helium gas, wherein the gas flow ratio of the sulfur hexafluoride gas to the oxygen gas is greater than 9: 1 and less than 11: 1,
the third preset pressure is 20-40mTorr, and the fifth preset power is: 800-.
Preferably, the mask layer is removed from the first surface by wet etching, and the entire first surface and the bottom of the trench are etched during the second dry etching process.
Preferably, the manufacturing method further comprises: cleaning the semiconductor wafer before forming the mask layer,
and after the second dry etching process is carried out, forming a sacrificial oxide layer on the first surface and the surface of the groove, and removing the sacrificial oxide layer.
A rounded trench structure formed by the method according to any one of the above embodiments, wherein the bottom of the trench, the boundary region between the bottom and the sidewall of the trench, and the boundary region between the sidewall and the first surface are all rounded structures.
The invention has the beneficial effects that: the method adopts two times of dry etching to form a smooth groove, firstly uses first dry etching mainly based on anisotropy to etch the semiconductor wafer through the mask layer so as to form a groove structure with steep side wall and smooth bottom, then removes the first layer of mask, and uses second dry etching mainly based on isotropy to etch the semiconductor wafer under the condition of no protection of the mask layer so as to smooth the top and the bottom of the groove, and finally forms the groove with steep side wall, smooth top and smooth bottom. Therefore, the groove manufacturing method provided by the invention has simple process steps, can greatly improve the process efficiency and save the cost, and the smooth groove provided by the invention has steep side wall and smooth top and bottom, thereby not only improving the performance and reliability of the device, but also bringing convenience for the subsequent growth and filling process in the groove.
Drawings
FIG. 1 is a schematic diagram of a trench structure implemented in the prior art;
FIG. 2 is a schematic view of a semiconductor wafer structure corresponding to a mask process in a trench manufacturing method according to the present invention;
FIG. 3 is a schematic view of a semiconductor wafer structure corresponding to a process for forming a photoresist layer in a trench manufacturing method according to the present invention;
FIG. 4 is a schematic view of a semiconductor wafer structure corresponding to a patterned mask layer process in a trench manufacturing method according to the present invention;
FIG. 5 is a schematic view of a semiconductor wafer structure corresponding to a first etching process in the trench manufacturing method according to the present invention;
FIG. 6 is a schematic diagram of a semiconductor wafer structure corresponding to a mask layer removal process in a trench manufacturing method according to the present invention;
FIG. 7 is a schematic diagram of a semiconductor wafer structure corresponding to a second etching process in the trench manufacturing method according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without any creative effort, shall fall within the protection scope of the present invention. It should be noted that "…" in this description of the preferred embodiment is only for technical attributes or features of the present invention.
The invention mainly forms a smooth groove on a semiconductor wafer by two dry etching processes, and before the invention is introduced, the following relevant definitions and contents of the etching process are introduced.
Dry etching: the method is a technology for etching a film by using plasma by using a plasma etching machine, and comprises chemical etching and physical etching, wherein the chemical etching is mainly isotropic, and the physical etching is mainly anisotropic.
Chemical etching: when the gas exists in the form of plasma, the chemical activity of the etching gas is much stronger than that of the etching gas under normal conditions, and the gas can react with the material more quickly by selecting proper gas according to different etched materials.
Physical etching: the plasma is guided and accelerated by the electric field, so that the plasma has certain energy, and atoms of an etched material can be knocked out when the plasma bombards the surface of an etched object, so that the aim of etching by utilizing physical energy transfer is fulfilled.
The main etching mode is a etching mode in the process of etching A by the etching process, which means that more than half of A etched in the etching process is caused by a etching.
Fig. 2-7 are schematic cross-sectional views of a semiconductor wafer corresponding to various process steps in the process of fabricating a rounded trench according to the present invention, which will be described in detail with reference to fig. 2-7.
The invention provides a method for manufacturing a smooth groove, which mainly comprises the following steps:
step 1: the semiconductor wafer is cleaned. The semiconductor wafer is a SiC wafer in the present embodiment, and may be another semiconductor wafer having a similar chemical property to SiC in other embodiments.
Step 2: a patterned mask layer is formed on a first surface of a semiconductor wafer, and the mask layer exposes a trench region of the semiconductor wafer.
Specifically, as shown in fig. 2 to 5, step 2 may further include:
step 21: a deposition process is performed to form a mask layer 02 on the entire first surface of the semiconductor wafer 01. As shown in fig. 2, the mask layer 02 covers the entire first surface. One of polysilicon, amorphous silicon, aluminum nitride and silicon dioxide can be selected to form the mask layer.
Step 22: a patterned photoresist barrier layer 03 is coated on the surface of the mask layer, the photoresist barrier layer 03 exposes the surface of the mask layer 02 in the trench region, and the specific structure formed in this step is shown in fig. 3.
Step 23: the first surface is subjected to a photolithography process through the photolithography barrier layer 03, the mask layer 02 is patterned to remove a portion of the mask layer 02 located in the trench region, so that the surface of the trench region is exposed by the mask layer 02, and then the photolithography barrier layer 03 is removed, and the structure formed at this step is as shown in fig. 4.
And step 3: and performing a first dry etching process by using the surface of the trench region as an etching start surface, and adjusting the first dry etching parameters to make the etching manner of the first dry etching process mainly anisotropic, so as to form a trench T with a steep sidewall and a smooth bottom in the trench region of the semiconductor wafer, as shown in fig. 5.
The first dry etching process comprises a first stage and a second stage, wherein during the first stage, a first group of etching gases are introduced into a reaction chamber of the plasma etching machine, the gas flow rate of each gas in the first group of etching gases is set, so that during the first stage, the boundary area of the bottom of the groove and the side wall of the groove is smoothened, and during the first stage, the pressure of the reaction chamber is set to be a first preset pressure, and the power of an upper electrode and the power of a lower electrode of the plasma etching machine are set to be a first preset power and a second preset power, so that the etching mode of the first dry etching is mainly physical etching, and a groove with steep side wall is formed during the first stage. And during a second stage, introducing a second group of reaction gases into the reaction chamber, setting the flow of each gas in the second group of reaction gases as a preset flow, setting the pressure of the reaction chamber as a second preset pressure, and setting the power of the upper electrode and the power of the lower electrode as a third preset power and a fourth preset power so as to round and smoothen the bottom of the groove during the second stage, wherein the second preset pressure is greater than the first preset pressure, and the fourth preset power is less than the second preset power.
Specifically, in the embodiment according to the present invention, during the first stage, the gases SF6 (sulfur hexafluoride) and O2 (oxygen) are used as the reaction gases, and the ratio of the two gas flows is set to be greater than 1:2 and less than 2: 1, for example, in a state where the pressure of the reaction chamber is set to be within 5mTorr (first preset pressure) which may be set to 1:1(SF 6: O2 is 1:1), the upper electrode power is set to: 800-: 300-500W (second predetermined power). During the first stage, gases SF6 (sulfur hexafluoride) and O2 (oxygen) are used as reaction gases, and the flow ratio of the two gases is set to be 1:1, so as to avoid forming micro-trenches at the junction area of the bottom and the side wall of the formed trench, the power of the lower electrode is larger than 300W, and to enhance physical etching, so that the physical etching is mainly used during the first stage, and the trench with steep side wall is obtained.
In the second stage, C4F8 (octafluorocyclobutene) and Ar (argon) are used as the reaction gases, wherein the flow rate of C4F8 may be 30-50sccm and the flow rate of Ar may be 90-110 sccm. In this embodiment, the flow rate of C4F8 is 40, and the flow rate of Ar is 100 sccm. The second preset pressure is set to be 8-10mTorr, and the third preset power is as follows: the fourth preset power of 600-: 100- & lt300 & gtW. During the second stage, gas with more etching byproducts is used as reaction gas, the pressure of the reaction chamber is increased, and the lower electrode is reduced, so that the bottom of the round groove can be obtained.
And 4, step 4: and removing the mask layer 02. In this embodiment, the mask layer 02 is removed from the first surface by wet etching, and the semiconductor wafer structure after the removal of the mask layer is as shown in fig. 6, where a boundary between the sidewall of the trench T and the first surface is exposed.
And 5: and carrying out second dry etching by taking the first surface as an etching initial surface, and adjusting the second dry etching parameters to ensure that the etching mode of the second dry etching process is mainly isotropic etching, so that the upper part and the bottom of the groove T become a smooth structure. As shown in fig. 7, the bottom of the trench T, the junction area of the bottom and the sidewall of the trench, and the junction area of the sidewall and the first surface are all rounded structures.
Step 7, gases SF6 (sulfur hexafluoride), O2 (oxygen) and He (helium) are used as a group of reaction gases, wherein the ratio of the flow rate of SF6 to the flow rate of O2 is more than 11: 1, and less than 9: 1, for example a ratio of 10: 1. The third preset pressure of the reaction chamber is set to 20-40mTorr, and the fifth preset power is: 800-: 0W. In step 7, the etching gas is mainly SF6 to react with the SiC wafer, and the lower electrode power is set to zero in order to weaken the physical etching effect, so that step 7 is mainly a chemical etching method. Because the mask is completely removed at this time, the top and the bottom of the trench are exposed, so that the top and the bottom can be rounded. The top and bottom trenches with different rounding radii can be obtained by adjusting the second etching time and the etching rate.
Step 6: and forming sacrificial oxide layers on the first surface and the surface of the groove, and removing the sacrificial oxide layers to eliminate the damage of the first dry etching and the second dry etching to the semiconductor wafer and reduce the surface roughness of the groove.
Referring to fig. 7, the bottom of the trench, the boundary area between the bottom and the sidewall of the trench, and the boundary area between the sidewall and the first surface are all rounded structures.
The method adopts two times of dry etching to form a smooth groove, firstly uses first dry etching mainly based on anisotropy to etch the semiconductor wafer through the mask layer so as to form a groove structure with steep side wall and smooth bottom, then removes the first layer of mask, and uses second dry etching mainly based on isotropy to etch the semiconductor wafer under the condition of no protection of the mask layer so as to smooth the top and the bottom of the groove, and finally forms the groove with steep side wall, smooth top and smooth bottom. Therefore, the groove manufacturing method provided by the invention has simple process steps, can greatly improve the process efficiency and save the cost, and the smooth groove provided by the invention has steep side wall and smooth top and bottom, so that the performance and reliability of a device can be improved, and convenience can be brought to the subsequent growth and filling process in the groove.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. A method for manufacturing a smooth groove is characterized by comprising the following steps:
forming a patterned mask layer on a first surface of a semiconductor wafer, the mask layer exposing a trench region of the semiconductor wafer,
carrying out a first dry etching process by taking the surface of the groove region as an etching starting surface, and adjusting the first dry etching parameters to ensure that the etching mode of the first dry etching process is mainly anisotropic so as to form a groove with a steep side wall and a smooth bottom in the groove region of the semiconductor wafer,
the mask layer is removed and the mask layer is removed,
and carrying out second dry etching by taking the first surface as an etching initial surface, and adjusting the parameters of the second dry etching to ensure that the etching mode of the second dry etching process is mainly isotropic etching so as to ensure that the upper part and the bottom of the groove become a smooth structure.
2. The method of claim 1, wherein the step of forming a patterned mask layer on the first surface of the semiconductor wafer comprises:
performing a deposition process to form a mask layer on the entire first surface,
coating a patterned photoetching barrier layer on the surface of the mask layer, wherein the photoetching barrier layer exposes the surface of the part of the mask layer in the groove region,
and carrying out a photoetching process on the first surface through the photoetching barrier layer to pattern the mask layer so as to remove the part of the mask layer in the groove region, so that the surface of the groove region is exposed by the mask layer.
3. The method of manufacturing according to claim 1, wherein the semiconductor wafer is a silicon carbide wafer,
and selecting one material of polysilicon, amorphous silicon, aluminum nitride and silicon dioxide to form the mask layer.
4. The manufacturing method according to claim 3, wherein the step of performing the first dry etching by using a plasma etching machine and adjusting the first dry etching parameters so that the etching manner of the first dry etching process is mainly anisotropic comprises:
during a first phase, introducing a first group of etching gases into a reaction chamber of the plasma etcher, and setting gas flow rates of various gases in the first group of etching gases so as to round an interface area of the bottom of the trench and the sidewall of the trench during the first phase, and during the first phase, setting the pressure of the reaction chamber to a first preset pressure, and setting upper electrode power and lower electrode power of the plasma etcher to a first preset power and a second preset power, so that the etching manner of the first dry etching is dominated by physical etching so as to form a trench with a straight sidewall during the first phase,
during a second stage, introducing a second group of reaction gases into the reaction chamber, setting the flow rate of each gas in the second group of reaction gases as a preset flow rate, setting the pressure of the reaction chamber as a second preset pressure, and setting the power of the upper electrode and the power of the lower electrode as a third preset power and a fourth preset power so as to round the bottom of the groove during the second stage,
the second preset pressure is greater than the first preset pressure, and the fourth preset power is less than the second preset power.
5. The method of manufacturing according to claim 4,
the first reaction group gas comprises sulfur hexafluoride gas and oxygen, and the gas flow ratio of the sulfur hexafluoride gas to the oxygen is more than 1:2 and less than 2: 1, the first preset pressure is not more than 5mTorr, and the first preset power is as follows: 800-: 300-500W of the reaction kettle is adopted,
the second set of reactant gases includes octafluorocyclobutene gas and argon, the flow rate of the octafluorocyclobutene gas is set as follows: 30-50sccm, and the flow rate of the argon gas is set as follows: 90-110sccm, the second preset pressure is 8-10mTorr, and the third preset power is: 600-: 100- & lt300 & gtW.
6. The manufacturing method according to claim 5, wherein the step of performing the second dry etching by using the plasma etching machine and adjusting the parameters of the second dry etching so that the etching manner of the second dry etching process is mainly isotropic comprises:
and in the third stage, after the mask layer is removed, introducing a third group of etching gases into a reaction chamber of the plasma etching machine, setting the gas flow of various gases in the third group of etching gases, setting the pressure of the reaction chamber to be a third preset pressure, and setting the power of the upper electrode and the power of the lower electrode to be a fifth preset power and a sixth preset power, so that the effect of physical etching is weakened in the third stage, and the etching mode of the second dry etching is mainly chemical etching.
7. The method of manufacturing according to claim 6,
the third group of reaction gases comprises sulfur hexafluoride gas, oxygen and helium, wherein the gas flow ratio of the sulfur hexafluoride gas to the oxygen is larger than 9: 1 and less than 11: 1,
the third preset pressure is 20-40mTorr, and the fifth preset power is: 800-.
8. The method of claim 5, wherein the mask layer is removed from the first surface by wet etching, and the entire first surface and the bottom of the trench are etched during the second dry etching process.
9. The method of manufacturing according to claim 1, further comprising: cleaning the semiconductor wafer before forming the mask layer,
and after the second dry etching process is carried out, forming a sacrificial oxide layer on the first surface and the surface of the groove, and removing the sacrificial oxide layer.
10. A rounded trench structure formed by the method according to any one of claims 1 to 9, wherein the bottom of the trench, the boundary region between the bottom and the sidewall of the trench, and the boundary region between the sidewall and the first surface are rounded structures.
CN202010881132.5A 2020-08-27 2020-08-27 Manufacturing method of smooth groove and smooth groove structure Pending CN114121639A (en)

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WO2023178895A1 (en) * 2022-03-21 2023-09-28 苏州东微半导体股份有限公司 Manufacturing method for silicon carbide device

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CN101572229A (en) * 2008-04-28 2009-11-04 北大方正集团有限公司 Method for flattening surface of polysilicon
CN111128717A (en) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 Manufacturing method of silicon carbide groove structure

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Publication number Priority date Publication date Assignee Title
CN101572229A (en) * 2008-04-28 2009-11-04 北大方正集团有限公司 Method for flattening surface of polysilicon
CN111128717A (en) * 2018-10-30 2020-05-08 株洲中车时代电气股份有限公司 Manufacturing method of silicon carbide groove structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023178895A1 (en) * 2022-03-21 2023-09-28 苏州东微半导体股份有限公司 Manufacturing method for silicon carbide device

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