CN114121138A - Memory voltage testing method and device, computing equipment and system - Google Patents
Memory voltage testing method and device, computing equipment and system Download PDFInfo
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Abstract
The invention relates to the field of computer equipment, in particular to a memory voltage testing method, a device, computing equipment and a system, which are applied to BMC (baseboard management controller), wherein the BMC is connected with the memory equipment, and the method comprises the following steps: acquiring a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device; acquiring a current state corresponding to the memory device; and adjusting the output voltage of the memory device according to the current state so as to test the memory device. According to the memory voltage testing method, the voltage adjusting instruction is obtained by the BMC, and then the output voltage of the memory device is adjusted, so that the operation of adjusting the output voltage of the memory device is reduced, no extra tool is needed, and the memory voltage testing efficiency is improved. In addition, the output voltage of the memory device in various states can be adjusted, and the accuracy of testing the memory device is improved.
Description
Technical Field
The invention relates to the field of computer equipment, in particular to a memory voltage testing method, a memory voltage testing device, computing equipment and a memory voltage testing system.
Background
With the rapid development of cloud computing and big data technology, the informatization and intellectualization trends of the current society are increasingly accelerated, and the requirements on performance and reliability are higher when a server is used as a core device of an informatization system. In the development process of the server, sufficient and rigorous tests are required to ensure the product quality, and the memory is one of important components and is a part which needs to pay important attention in the test process.
The memory four-corner test is an important item in the memory related test, and comprises four conditions of high temperature and low pressure, high temperature and high pressure, low temperature and low pressure and low temperature and high pressure. After the server is placed in the high-low temperature box, the power supply voltage of the memory needs to be adjusted according to the temperature set value. Taking a currently mainstream DDR4 memory as an example, there are three Supply voltages, namely, a Supply Voltage for Output (VDDQ), a memory chip activation (VPP), and an input/Output signal termination (VTT), where the input/Output signal termination (VPP) is 1/2 of the Output buffer Supply Voltage, and does not need to be adjusted independently.
The voltage regulation method available in the current test is as follows: a debugging tool of a VR manufacturer is used for connecting a debugging interface reserved on a server main board and a PC, the voltage values of output buffer power supply voltage and storage chip activation power supply voltage can be modified after debugging software is installed on the PC, and wiring is conducted from the inside of a slave case, so that the voltage of a memory is adjusted.
The voltage adjusting method has a complex operation process and needs additional debugging tools and software, so the voltage adjusting efficiency is low.
Disclosure of Invention
In view of this, embodiments of the present invention provide a memory voltage testing method, device, computing device and system method, which aim to solve the problem of low voltage adjustment efficiency due to the complicated memory voltage testing operation process and the need of additional debugging tools and software.
According to a first aspect, an embodiment of the present invention provides a memory voltage testing method, which is applied to a BMC, where the BMC is connected to a memory device, and the method includes:
acquiring a voltage adjusting instruction, wherein the voltage adjusting instruction is used for indicating to adjust the output voltage in the memory device;
acquiring a current state corresponding to the memory device;
and adjusting the output voltage of the memory device according to the current state so as to test the memory device.
According to the memory voltage testing method provided by the embodiment of the application, the voltage adjusting instruction is obtained, and the current state corresponding to the memory device is obtained. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging tool of a VR manufacturer is not needed to be used for connecting the reserved debugging interface on the server mainboard with the PC, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjusting instruction and then adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, and no additional tool is needed, so that the efficiency of testing the memory voltage is improved. In addition, according to the method, the output voltage of the memory device can be adjusted according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the accuracy of testing the memory device is improved.
With reference to the first aspect, in a first implementation manner of the first aspect, adjusting an output voltage of a memory device according to a current state to test the memory device includes:
switching the control mode of the memory device to a target control mode according to the voltage adjustment instruction;
the output voltage of the memory device is adjusted based on the target control mode.
According to the memory voltage testing method provided by the embodiment of the application, the control mode of the memory device is switched to the target control mode according to the voltage adjusting instruction, and the output voltage of the memory device is adjusted based on the target control mode. Therefore, the accuracy of adjusting the output voltage of the memory device can be improved, and errors in adjusting the output voltage of the memory device caused by mismatching of the control mode of the memory device are avoided.
With reference to the first aspect, in a second implementation manner of the first aspect, the obtaining a current state corresponding to a memory device includes:
acquiring power state information sent by target equipment;
and determining the current state corresponding to the memory device according to the power state information.
According to the memory voltage testing method provided by the embodiment of the application, the current state corresponding to the memory device is determined by acquiring the power state information sent by the target device and according to the power state information. Therefore, the accuracy of the current state corresponding to the acquired memory device can be ensured.
With reference to the second implementation manner of the first aspect, in a third implementation manner of the first aspect, determining a current state corresponding to the memory device according to the power state information includes:
if the power supply state information is high level information, determining that the current state is a normal working state;
and if the power supply state information is low level information, determining that the current state is a power-on shutdown state.
According to the memory voltage testing method provided by the embodiment of the application, whether the current state is the normal working state or the power-on shutdown state is determined according to the fact that the power supply state information is the high level information and the low level information, and therefore the accuracy of the obtained current state corresponding to the memory device is further guaranteed.
With reference to the first aspect, in a fourth implementation manner of the first aspect, the adjusting an output voltage of a memory device according to a current state includes:
if the current state is a normal working state, sending a first control instruction to the memory device; the first control instruction is used for indicating the memory device to adjust the voltage output register; the voltage output register is used for adjusting the activation power supply voltage of the memory chip of the memory device and outputting the buffering power supply voltage in a normal working state.
According to the memory voltage testing method provided by the embodiment of the application, under the condition that the current state corresponding to the memory device is the normal working state, the first control instruction is sent to the memory device, so that the memory device can adjust the voltage output register, and the memory chip of the memory device is adjusted to activate the power supply voltage and output the buffer power supply voltage. The memory chip of the memory device is adjusted in the normal working state by activating the power supply voltage and outputting the buffer power supply voltage, and the coverage of voltage adjustment is complete.
With reference to the first aspect, in a fifth implementation manner of the first aspect, the adjusting an output voltage of a memory device according to a current state includes:
if the current state is a power-on shutdown state, sending a second control instruction to the memory device; the second control instruction is used for indicating the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage of the memory chip of the memory device and outputting the buffering power supply voltage in the power-on and power-off state.
According to the memory voltage testing method provided by the embodiment of the application, under the condition that the current state corresponding to the memory device is the power-on and power-off state, the second control instruction is sent to the memory device, so that the memory device can adjust the starting voltage register, and the memory chip of the memory device is adjusted to activate the power supply voltage and output the buffer power supply voltage. The memory chip of the memory device is adjusted in the power-on and power-off states by activating the power supply voltage and outputting the buffer power supply voltage, and the coverage of voltage adjustment is complete.
With reference to the first implementation manner of the first aspect, in a sixth implementation manner of the first aspect, after the adjusting the output voltage of the memory device according to the current state, the method further includes:
and switching the control mode of the memory device from the target control mode to the normal control mode.
According to the memory voltage testing method provided by the embodiment of the application, after the output voltage of the memory device is adjusted according to the current state, the control mode of the memory device is switched from the target control mode to the normal control mode, so that the normal work of the memory device is not influenced after the voltage of the memory device is adjusted.
According to a second aspect, an embodiment of the present invention further provides a memory voltage testing apparatus, which is applied to a BMC, where the BMC is connected to a memory device to be adjusted, and the apparatus includes:
the first acquisition module is used for acquiring a voltage adjustment instruction, and the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
the second obtaining module is used for obtaining the current state corresponding to the memory device;
and the adjusting module is used for adjusting the output voltage of the memory device according to the current state so as to test the memory device.
The memory voltage testing device provided by the embodiment of the application obtains the voltage adjustment instruction and obtains the current state corresponding to the memory device. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging tool of a VR manufacturer is not needed to be used for connecting the reserved debugging interface on the server mainboard with the PC, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjusting instruction and then adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, and no additional tool is needed, so that the efficiency of testing the memory voltage is improved. In addition, according to the method, the output voltage of the memory device can be adjusted according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the accuracy of testing the memory device is improved.
According to a third aspect, an embodiment of the present invention further provides a computing device, which includes a storage and a processor, where the storage stores computer instructions, and the processor executes the computer instructions, so as to execute the memory voltage testing method in the first aspect and the implementation manner of the first aspect.
According to a fourth aspect, an embodiment of the present invention further provides a memory voltage testing system, which includes a BMC and a memory device, where the BMC is connected to the memory device,
the BMC acquires a voltage adjusting instruction, wherein the voltage adjusting instruction is used for indicating to adjust the output voltage in the memory device;
the BMC acquires a current state corresponding to the memory device;
and the BMC adjusts the output voltage of the memory device according to the current state so as to test the memory device.
The memory voltage test system provided by the embodiment of the application obtains the voltage adjustment instruction and obtains the current state corresponding to the memory device. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging tool of a VR manufacturer is not needed to be used for connecting the reserved debugging interface on the server mainboard with the PC, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjusting instruction and then adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, and no additional tool is needed, so that the efficiency of testing the memory voltage is improved. In addition, according to the method, the output voltage of the memory device can be adjusted according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the accuracy of testing the memory device is improved.
According to a fifth aspect, an embodiment of the present invention provides a computer-readable storage medium, which stores computer instructions for causing a computer to execute the memory voltage testing method in the first aspect or any one of the implementation manners of the first aspect.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to the drawings without creative efforts for those skilled in the art.
FIG. 1 is a flow chart of a memory voltage testing method according to an embodiment of the present invention;
FIG. 2 is a flow chart of a memory voltage testing method according to another embodiment of the present invention;
FIG. 3 is a flow chart of a memory voltage testing method according to another embodiment of the present invention;
FIG. 4 is a flowchart illustrating a method for testing a memory voltage according to another embodiment of the present invention;
FIG. 5 is a functional block diagram of a memory voltage testing apparatus according to an embodiment of the present invention;
FIG. 6 is a diagram of a hardware structure of a computing device provided by an embodiment of the invention;
fig. 7 is a schematic structural diagram of a memory voltage testing system provided by an embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that in the method for testing the memory voltage provided in the embodiment of the present application, the execution main body may be a device for testing the memory voltage, and the device for testing the memory voltage may be implemented as part or all of a computer device in a software, hardware, or a combination of the software and the hardware, where the computer device may be a server or a terminal, where the server in the embodiment of the present application may be a server or a server cluster composed of multiple servers, and the terminal in the embodiment of the present application may be other intelligent hardware devices such as a smart phone, a personal computer, a tablet computer, a wearable device, and an intelligent robot. In the following method embodiments, the execution subject is a computing device as an example.
In an embodiment of the present application, as shown in fig. 1, a memory voltage testing method is provided, which is described by taking the method as an example of being applied to a BMC, where the BMC is connected to a memory device, and the method includes the following steps:
and S11, acquiring a voltage adjusting command.
The voltage adjustment instruction is used for instructing adjustment of output voltage in the memory device.
In an optional embodiment, the BMC may receive a voltage adjustment command input by a user based on the BMC display interface, and may also receive a voltage adjustment command sent by another device.
In another optional embodiment, the BMC may further obtain the voltage adjustment command based on the detection of the memory device.
And S12, acquiring the current state corresponding to the memory device.
Specifically, the BMC may send detection information to the other device, where the detection information is used to detect whether the other device is working normally. If the BMC receives response information sent by other equipment based on the detection information, the BMC determines that the current state corresponding to the memory equipment is a normal working state; if the BMC does not receive response information sent by other equipment based on the detection information, the BMC determines that the current state corresponding to the memory equipment is a power-on power-off state. The other devices may be CPUs, or may be devices such as integrated south bridge or north bridge.
And S13, adjusting the output voltage of the memory device according to the current state so as to test the memory device.
In an optional implementation manner, the BMC may determine an adjustment policy corresponding to the current state according to the current state corresponding to the memory device, and then adjust the output voltage corresponding to the memory device according to the adjustment policy, so as to test the memory device. The adjustment strategy may be to directly adjust the value of the output voltage of the memory device, for example, to adjust the active supply voltage of the memory chip to 5V, to adjust the output buffer supply voltage to 6V,
according to the memory voltage testing method provided by the embodiment of the application, the voltage adjusting instruction is obtained, and the current state corresponding to the memory device is obtained. Therefore, the output voltage of the memory device can be adjusted according to the current state, and the memory device can be tested under various output voltages by adjusting the output voltage of the memory device. According to the memory voltage testing method, a debugging tool of a VR manufacturer is not needed to be used for connecting the reserved debugging interface on the server mainboard with the PC, debugging software is installed on the PC, and then the voltage value of the output voltage of the memory device is modified. The BMC acquires the voltage adjusting instruction and then adjusts the output voltage of the memory device, so that the operation of adjusting the output voltage of the memory device is reduced, and no additional tool is needed, so that the efficiency of testing the memory voltage is improved. In addition, according to the method, the output voltage of the memory device can be adjusted according to the current state corresponding to the memory device, so that the output voltage of the memory device is matched with the current state corresponding to the memory device, the output voltage of the memory device in various states can be adjusted, and the accuracy of testing the memory device is improved.
In an alternative embodiment of the present application, as shown in fig. 2, after the step S11 "obtaining the voltage adjustment command", the method may further include the following steps:
and S21, switching the control mode of the memory device to a target control mode according to the voltage adjusting instruction.
Specifically, the output voltage of the memory device supports multiple control modes in general, and the multiple control modes may include, for example, an SVID bus, a PMBus, an I2C bus, and the like.
After acquiring the voltage adjustment instruction, the BMC may determine a target control mode corresponding to the memory device according to the voltage adjustment instruction, and then switch the control mode of the memory device to the target control mode.
For example, assuming that the control mode corresponding to the current output voltage of the memory device is the PMBus control mode, after the BMC obtains the voltage adjustment instruction, it determines that the target control mode corresponding to the memory device is I2C bus control, and therefore, the BMC switches the control mode of the memory device from the PMBus control to I2C bus control.
S22, adjusting the output voltage of the memory device based on the target control mode.
Specifically, after switching the control mode of the memory device to the target control mode, the BMC may adjust the output voltage of the memory device based on the switched target control mode.
According to the memory voltage testing method provided by the embodiment of the application, the control mode of the memory device is switched to the target control mode according to the voltage adjusting instruction, and the output voltage of the memory device is adjusted based on the target control mode. Therefore, the accuracy of adjusting the output voltage of the memory device can be improved, and errors in adjusting the output voltage of the memory device caused by mismatching of the control mode of the memory device are avoided.
In an alternative embodiment of the present application, as shown in fig. 3, a method for testing a memory voltage provided in the embodiment of the present application may include the following steps:
and S31, acquiring a voltage adjusting command.
The voltage adjustment instruction is used for instructing adjustment of output voltage in the memory device.
Please refer to fig. 1, which illustrates the above-mentioned detailed description of S11.
And S32, acquiring the current state corresponding to the memory device.
The step S32 may include the following steps:
s321, obtaining power status information sent by the target device.
Specifically, the BMC may receive power status information sent by a target device based on communication with the target device, where the target device may be a CPU, or may also be a device such as an integrated south bridge or a north bridge. The power state information may characterize the current operating state of the target device.
And S322, determining the current state corresponding to the memory device according to the power state information.
In an optional implementation manner, if the power state information is high level information, it is determined that the current state is a normal operating state.
In another optional implementation, if the power state information is low level information, it is determined that the current state is a power-on/off state.
Specifically, after receiving power state information sent by the target device, the BMC may identify and study the power state information, and if the power state information is high-level information, it indicates that a power source passes through the target device, and the target device is operating normally, and the BMC determines that the current state is the normal operating state. If the power state information is low level information, it indicates that the target device has a power supply and passes through, but the target device does not work normally, and the BMC determines that the current state is a power-on/off state.
According to the memory voltage testing method provided by the embodiment of the application, whether the current state is the normal working state or the power-on shutdown state is determined according to the fact that the power supply state information is the high level information and the low level information, and therefore the accuracy of the obtained current state corresponding to the memory device is further guaranteed.
And S33, adjusting the output voltage of the memory device according to the current state so as to test the memory device.
The above S33 may include the following cases:
in one case, if the current state is a normal working state, a first control instruction is sent to the memory device; the first control instruction is used for indicating the memory device to adjust the voltage output register; the voltage output register is used for regulating the activation power supply voltage of the memory chip of the memory device and outputting the buffer power supply voltage in a normal working state.
In another case, if the current state is a power-on shutdown state, a second control instruction is sent to the memory device; the second control instruction is used for indicating the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage of the memory chip of the memory device and outputting the buffering power supply voltage in the power-on and power-off state.
Specifically, after determining the current state corresponding to the memory device, the BMC may determine the control instruction that needs to be sent to the memory device according to the current state of the memory device.
In one case, if the current state is a normal working state, the BMC sends a first control instruction to the memory device. After the memory device receives the first control instruction sent by the BMC, the voltage output register is adjusted according to the first control instruction, and therefore the memory chip of the memory device is adjusted to activate the power supply voltage and output the buffering power supply voltage.
In another case, if the current state is a power-on shutdown state, the BMC sends a second control instruction to the memory device. And after the memory device receives a second control instruction sent by the BMC, adjusting the starting voltage register according to the second control instruction, so as to adjust the activation power supply voltage of the memory chip of the memory device and output the buffering power supply voltage.
According to the memory voltage testing method provided by the embodiment of the application, under the condition that the current state corresponding to the memory device is the normal working state, the first control instruction is sent to the memory device, so that the memory device can adjust the voltage output register, and the memory device memory chip is adjusted to activate the power supply voltage and output the buffer power supply voltage. The memory chip activation power supply voltage and the output buffer power supply voltage of the memory device are adjusted under the normal working state. And under the condition that the current state corresponding to the memory device is a power-on shutdown state, sending a second control instruction to the memory device, so that the memory device can adjust the starting voltage register, and adjust the memory device storage chip to activate the power supply voltage and output the buffer power supply voltage. The activation power supply voltage and the output buffer power supply voltage of the memory chip of the memory device are adjusted in the power-on and power-off state, and the coverage of voltage adjustment is complete.
In an alternative embodiment of the present application, as shown in fig. 4, a method for testing a memory voltage provided in the embodiment of the present application may include the following steps:
and S41, acquiring a voltage adjusting command.
Please refer to fig. 3, which provides a detailed description of S31.
And S42, switching the control mode of the memory device to a target control mode according to the voltage adjusting instruction.
Please refer to fig. 2, which illustrates the above-mentioned detailed description of S21.
And S43, acquiring the current state corresponding to the memory device.
Please refer to fig. 3, which provides a detailed description of S32.
And S44, adjusting the output voltage of the memory device based on the target control mode according to the current state so as to test the memory device.
Please refer to fig. 3, which provides a detailed description of S33.
And S45, switching the control mode of the memory device from the target control mode to the normal control mode.
Specifically, after the output voltage of the memory device is adjusted, the BMC switches the control mode of the memory device from the target control mode to the normal control mode.
According to the memory voltage testing method provided by the embodiment of the application, after the output voltage of the memory device is adjusted according to the current state, the control mode of the memory device is switched from the target control mode to the normal control mode, so that the normal work of the memory device is not influenced after the voltage of the memory device is adjusted.
As shown in fig. 5, the present embodiment provides a memory voltage testing apparatus, which is applied to BMC, where the BMC is connected to a memory device to be adjusted, and the apparatus includes:
a first obtaining module 51, configured to obtain a voltage adjustment instruction, where the voltage adjustment instruction is used to instruct to adjust an output voltage in the memory device;
a second obtaining module 52, configured to obtain a current state corresponding to the memory device;
and an adjusting module 53, configured to adjust an output voltage of the memory device according to the current state, so as to test the memory device.
In an embodiment of the present application, the adjusting module 53 is specifically configured to switch a control mode of the memory device to a target control mode according to the voltage adjusting instruction; the output voltage of the memory device is adjusted based on the target control mode.
In an embodiment of the present application, the second obtaining module 52 is specifically configured to obtain power status information sent by the target device; and determining the current state corresponding to the memory device according to the power state information.
In an embodiment of the application, the second obtaining module 52 is specifically configured to determine that the current state is a normal operating state if the power state information is high level information; and if the power supply state information is low level information, determining that the current state is a power-on and power-off state.
In an embodiment of the present application, the adjusting module 53 is specifically configured to send a first control instruction to the memory device if the current state is a normal operating state; the first control instruction is used for indicating the memory device to adjust the voltage output register; the voltage output register is used for adjusting the activation power supply voltage of the memory chip of the memory device and outputting the buffering power supply voltage in a normal working state.
In an embodiment of the present application, the adjusting module 53 is specifically configured to send a second control instruction to the memory device if the current state is a power-on/off state; the second control instruction is used for indicating the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage of the memory chip of the memory device and outputting the buffering power supply voltage in the power-on and power-off state.
In an embodiment of the application, the switching module 54 is further configured to switch the control mode of the memory device from the target control mode to the normal control mode.
For the specific limitations and advantages of the memory voltage testing apparatus, reference may be made to the above limitations on the memory voltage testing method, which is not described herein again. All or part of each module in the memory voltage testing device can be realized by software, hardware and a combination thereof. The modules can be embedded in a hardware form or independent of a processor in the electronic device, or can be stored in a memory in the electronic device in a software form, so that the processor can call and execute operations corresponding to the modules.
An embodiment of the present invention further provides a computing device, which has the memory voltage testing apparatus shown in fig. 5.
As shown in fig. 6, fig. 6 is a schematic structural diagram of a computing device according to an alternative embodiment of the present invention, and as shown in fig. 6, the computing device may include: at least one processor 61, such as a CPU (Central Processing Unit), at least one communication interface 63, memory 64, at least one communication bus 62. Wherein a communication bus 62 is used to enable the connection communication between these components. The communication interface 63 may include a Display (Display) and a Keyboard (Keyboard), and the optional communication interface 63 may also include a standard wired interface and a standard wireless interface. The Memory 64 may be a high-speed RAM Memory (volatile Random Access Memory) or a non-volatile Memory (non-volatile Memory), such as at least one disk Memory. The memory 64 may optionally be at least one memory device located remotely from the processor 61. Wherein the processor 61 may be in connection with the apparatus described in fig. 6 or fig. 6, the memory 64 stores an application program, and the processor 61 calls the program code stored in the memory 64 for performing any of the above-mentioned method steps.
The communication bus 62 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. The communication bus 62 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 6, but this is not intended to represent only one bus or type of bus.
The memory 64 may include a volatile memory (RAM), such as a random-access memory (RAM); the memory may also include a non-volatile memory (english: non-volatile memory), such as a flash memory (english: flash memory), a hard disk (english: hard disk drive, abbreviated: HDD) or a solid-state drive (english: SSD); the memory 64 may also comprise a combination of the above-mentioned kinds of memories.
The processor 61 may be a Central Processing Unit (CPU), a Network Processor (NP), or a combination of CPU and NP.
The processor 61 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a Programmable Logic Device (PLD), or a combination thereof. The PLD may be a Complex Programmable Logic Device (CPLD), a field-programmable gate array (FPGA), a General Array Logic (GAL), or any combination thereof.
Optionally, the memory 64 is also used to store program instructions. The processor 61 may call program instructions to implement the memory voltage testing method as shown in the embodiments of fig. 1 to 3 of the present application.
As shown in fig. 7, fig. 7 is a schematic structural diagram of a memory voltage testing system according to an alternative embodiment of the present invention. As shown in fig. 7, in the motherboard, the BMC and the memory device are connected based on an I2C bus. A debugging interface used for connecting a debugging tool is reserved in the mainboard, and the debugging interface is connected with the memory device based on an I2C bus. Further, the CPU is connected to the memory device based on the SVID bus. The memory device comprises two voltage modes of LOOPA and LOOPB, wherein the LOOPA outputs VDDQ voltage, the LOOPB outputs VPP voltage, the output voltage of each power supply is controlled by two registers of Vboost and Vout, namely VDDQ voltage is controlled by two registers of a starting voltage register and an output voltage register, and VPP voltage is also controlled by two registers of a starting voltage register and an output voltage register.
The embodiment of the invention also provides a non-transient computer storage medium, wherein the computer storage medium stores computer executable instructions, and the computer executable instructions can execute the memory voltage testing method in any method embodiment. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, abbreviated as HDD) or a Solid State Drive (SSD), etc.; the storage medium may also comprise a combination of memories of the above kind.
Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope defined by the appended claims.
Claims (10)
1. A memory voltage test method is applied to BMC, the BMC is connected with a memory device, and the method comprises the following steps:
acquiring a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
acquiring a current state corresponding to the memory device;
and adjusting the output voltage of the memory device according to the current state so as to test the memory device.
2. The method of claim 1, wherein adjusting the output voltage of the memory device to test the memory device according to the current state comprises:
switching the control mode of the memory device to a target control mode according to the voltage adjusting instruction;
adjusting an output voltage of the memory device based on the target control manner.
3. The method according to claim 1, wherein the obtaining the current state corresponding to the memory device comprises:
acquiring power state information sent by target equipment;
and determining the current state corresponding to the memory device according to the power state information.
4. The method according to claim 3, wherein the determining the current state of the memory device according to the power status information comprises:
if the power supply state information is high level information, determining that the current state is a normal working state;
and if the power supply state information is low level information, determining that the current state is a power-on and power-off state.
5. The method of claim 1, wherein adjusting the output voltage of the memory device according to the current state comprises:
if the current state is a normal working state, sending a first control instruction to the memory device; the first control instruction is used for indicating the memory device to adjust a voltage output register; the voltage output register is used for adjusting the activation power supply voltage of the memory chip of the memory device and outputting the buffering power supply voltage in a normal working state.
6. The method of claim 1, wherein adjusting the output voltage of the memory device according to the current state comprises:
if the current state is a power-on power-off state, sending a second control instruction to the memory device; the second control instruction is used for indicating the memory device to adjust the starting voltage register; the starting voltage register is used for adjusting the activation power supply voltage of the memory chip of the memory device and outputting the buffering power supply voltage in the power-on and power-off state.
7. The method of claim 2, wherein after adjusting the output voltage of the memory device according to the current state, the method further comprises:
and switching the control mode of the memory device from the target control mode to a normal control mode.
8. A memory voltage testing device is applied to BMC, the BMC is connected with a memory device to be adjusted, and the device comprises:
the first obtaining module is used for obtaining a voltage adjusting instruction, and the voltage adjusting instruction is used for indicating to adjust the output voltage in the memory device;
the second obtaining module is used for obtaining the current state corresponding to the memory device;
and the adjusting module is used for adjusting the output voltage of the memory device according to the current state so as to test the memory device.
9. A computing device comprising a memory and a processor, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the memory voltage testing method of any one of claims 1-7.
10. A memory voltage test system is characterized in that the system comprises a BMC and a memory device, the BMC is connected with the memory device,
the BMC acquires a voltage adjustment instruction, wherein the voltage adjustment instruction is used for indicating to adjust the output voltage in the memory device;
the BMC acquires a current state corresponding to the memory device;
and the BMC adjusts the output voltage of the memory device according to the current state so as to test the memory device.
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| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN112732498A (en) * | 2020-12-29 | 2021-04-30 | 北京浪潮数据技术有限公司 | Test method, device, equipment and storage medium for simulating single-point power-on and power-off of equipment |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109683696A (en) * | 2018-12-25 | 2019-04-26 | 浪潮电子信息产业股份有限公司 | Fault of server power supply detection system, method, apparatus, equipment and medium |
| CN112732498A (en) * | 2020-12-29 | 2021-04-30 | 北京浪潮数据技术有限公司 | Test method, device, equipment and storage medium for simulating single-point power-on and power-off of equipment |
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