CN114120920B - Pixel circuit, driving method thereof, display panel and display device - Google Patents
Pixel circuit, driving method thereof, display panel and display device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0233—Improving the luminance or brightness uniformity across the screen
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Abstract
The embodiment of the invention provides a pixel circuit, a driving method thereof, a display panel and a display device, relates to the technical field of display, and aims to reduce the influence of node electric leakage on driving current. The pixel circuit includes: the grid electrode of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the second node, and the second pole of the driving transistor is electrically connected with the third node; the grid electrode resetting module comprises a first resetting transistor, a second resetting transistor and a regulating and controlling unit, wherein the grid electrode of the first resetting transistor is electrically connected with the first scanning signal line, the first electrode of the first resetting transistor is electrically connected with the resetting signal line, and the second electrode of the first resetting transistor is electrically connected with the first intermediate node; the grid electrode of the second reset transistor is electrically connected with the first scanning signal line, the first electrode of the second reset transistor is electrically connected with the first intermediate node, and the second electrode of the second reset transistor is electrically connected with the first node; the first end of the regulation and control unit receives a high level voltage larger than the reset voltage in the light-emitting period, the second end of the regulation and control unit is electrically connected with the first intermediate node, and the first intermediate node is raised in potential by the high level voltage in the light-emitting period.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the technical field of display, in particular to a pixel circuit, a driving method thereof, a display panel and a display device.
[ background ] A method for producing a semiconductor device
An Organic Light Emitting Diode (OLED) display panel includes a plurality of pixel circuits arranged in a matrix, wherein the pixel circuits include a plurality of transistors, and the pixel circuits transmit driving current to Light Emitting elements based on the cooperation of the plurality of transistors, so as to drive the Light Emitting elements to emit Light.
However, due to the off-state leakage of the transistor, the leakage of a part of nodes in the pixel circuit is severe, which causes the driving current transmitted by the pixel circuit to deviate from the standard value, and further causes the brightness of the light emitting device to deviate, thereby having a bad influence on the display effect.
[ summary of the invention ]
In view of this, embodiments of the present invention provide a pixel circuit, a driving method thereof, a display panel, and a display device, which can effectively reduce the influence of node leakage on driving current.
In one aspect, an embodiment of the present invention provides a pixel circuit, including:
the grid electrode of the driving transistor is electrically connected with a first node, the first pole of the driving transistor is electrically connected with a second node, and the second pole of the driving transistor is electrically connected with a third node;
a gate reset module including a first reset transistor, a second reset transistor, and a regulation unit, wherein,
a gate of the first reset transistor is electrically connected to a first scan signal line, a first pole of the first reset transistor is electrically connected to a reset signal line, a second pole of the first reset transistor is electrically connected to a first intermediate node, and the first reset transistor is configured to write a reset voltage to the first intermediate node in response to an enable level of the first scan signal during a reset period;
a gate of the second reset transistor is electrically connected to the first scan signal line, a first pole of the second reset transistor is electrically connected to the first intermediate node, a second pole of the first reset transistor is electrically connected to a first node, and the second reset transistor is configured to write a voltage of the first intermediate node into the first node in response to an enable level of the first scan signal during the reset period;
the first end of the regulation and control unit receives a high level voltage in a light-emitting period, the high level voltage is larger than the reset voltage, the second end of the regulation and control unit is electrically connected with the first intermediate node, and the regulation and control unit is used for raising the potential of the first intermediate node by using the high level voltage in the light-emitting period.
On the other hand, an embodiment of the present invention provides a driving method of a pixel circuit, where the pixel circuit includes:
the grid electrode of the driving transistor is electrically connected with a first node, the first pole of the driving transistor is electrically connected with a second node, and the second pole of the driving transistor is electrically connected with a third node;
a gate reset module including a first reset transistor, a second reset transistor, and a regulation unit, wherein,
the grid electrode of the first reset transistor is electrically connected with a first scanning signal line, the first pole of the first reset transistor is electrically connected with a reset signal line, and the second pole of the first reset transistor is electrically connected with a first intermediate node;
a gate of the second reset transistor is electrically connected to the first scan signal line, a first pole of the second reset transistor is electrically connected to the first intermediate node, and a second pole of the first reset transistor is electrically connected to the first node;
a first end of the regulation unit receives a high-level voltage in a light-emitting period, the high-level voltage is greater than a reset voltage, and a second end of the regulation unit is electrically connected with the first intermediate node;
the driving cycle of the pixel circuit includes a reset period and a light emitting period, the driving method including:
in the reset period, the first reset transistor writes a reset voltage into the first intermediate node in response to an enable level of the first scan signal, and the second reset transistor writes a voltage of the first intermediate node into the first node in response to an enable level of the first scan signal;
in the light emission period, the regulation unit raises the potential of the first intermediate node by the high level voltage.
In another aspect, an embodiment of the invention provides a display panel including the pixel circuit.
In another aspect, an embodiment of the present invention provides a display device, including the display panel described above.
One of the above technical solutions has the following beneficial effects:
in the embodiment of the invention, the control unit is additionally arranged in the grid reset module, and can raise the potential of the first intermediate node by using high-level voltage in a light-emitting period, so that the first intermediate node keeps a higher potential, the voltage difference between the first node and the first intermediate node is smaller, namely the source-drain voltage of the second reset transistor is smaller, the electric leakage degree from the first node to the first intermediate node is effectively reduced, and the potential of the first node is better kept at V Data -V th The above. Therefore, even if the leakage characteristics of the gate reset transistors used for resetting the gates of the driving transistors in different pixel circuits are different, the potential of the first node in the pixel circuit with serious transistor leakage can be kept stable, the driving current transmitted by the part of the pixel circuit tends to a standard value, the difference of the light-emitting brightness of the light-emitting elements corresponding to the part of the pixel circuit and other pixel circuits is reduced, and bright spots are prevented from appearing in a displayed picture.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention;
FIG. 2 is a timing diagram corresponding to FIG. 1;
fig. 3 is another schematic structural diagram of a pixel circuit according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a structure of a control unit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of another structure of a regulatory unit according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a regulation unit according to an embodiment of the present invention;
fig. 7 is a schematic layout diagram of a pixel circuit without a regulation unit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of another structure of a regulatory unit according to an embodiment of the present invention;
FIG. 9 is a schematic view of another structure of a regulatory unit according to an embodiment of the present invention;
FIG. 10 is a flowchart of a driving method according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the invention;
fig. 12 is a schematic structural diagram of a display panel according to an embodiment of the present invention.
[ detailed description ] embodiments
For better understanding of the technical solutions of the present invention, the following detailed descriptions of the embodiments of the present invention are provided with reference to the accompanying drawings.
It should be understood that the described embodiments are only some embodiments of the invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the description of the invention and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be understood that the term "and/or" as used herein is merely one type of association that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter associated objects are in an "or" relationship.
It should be understood that although the terms first and second may be used to describe the reset transistor and the regulating transistor in the embodiments of the present invention, the reset transistor and the regulating transistor should not be limited to these terms, and these terms are only used to distinguish the reset transistor and the regulating transistor from each other. For example, the first reset transistor may also be referred to as a second reset transistor, and similarly, the second reset transistor may also be referred to as a first reset transistor, without departing from the scope of embodiments of the present invention.
To more clearly explain the problems in the prior art and the technical solutions provided by the present invention, taking the pixel circuit shown in fig. 1 as an example, the present invention first explains the working principle of the pixel circuit:
as shown in fig. 1, fig. 1 is a schematic structural diagram of a pixel circuit according to an embodiment of the present invention, and the pixel circuit includes a driving transistor M0, a gate reset transistor M1, an anode reset transistor M2, a data writing transistor M3, a threshold compensation transistor M4, a first light-emitting control transistor M5, a second light-emitting control transistor M6, and a storage capacitor C.
The gate of the driving transistor M0 is electrically connected to the first node N1, the first pole of the driving transistor M0 is electrically connected to the second node N2, and the second pole of the driving transistor M0 is electrically connected to the third node N3.
The gate of the gate reset transistor M1 is electrically connected to the first Scan signal line Scan1, the first pole of the gate reset transistor M1 is electrically connected to the reset signal line Vref, and the second pole of the gate reset transistor M1 is electrically connected to the first node N1.
The gate of the anode reset transistor M2 is electrically connected to the first Scan signal line Scan1, the first pole of the anode reset transistor M2 is electrically connected to the reset signal line Vref, and the second pole of the anode reset transistor M2 is electrically connected to the anode of the light emitting element D. The gate of the anode reset transistor M2 may be controlled by another scanning signal line, and may be selected according to actual needs.
The gate of the Data writing transistor M3 is electrically connected to the second Scan signal line Scan2, the first pole of the Data writing transistor M3 is electrically connected to the Data line Data, and the second pole of the Data writing transistor M3 is electrically connected to the second node N2.
A gate of the threshold compensation transistor M4 is electrically connected to the second Scan signal line Scan2, a first pole of the threshold compensation transistor M4 is electrically connected to the third node N3, and a second pole of the threshold compensation transistor M4 is electrically connected to the first node N1. The gate of the threshold compensation transistor M4 may be controlled by another scanning signal line, and may be selected according to actual needs.
A gate of the first light emission controlling transistor M5 is electrically connected to the light emission control signal line Emit, a first pole of the first light emission controlling transistor M5 is electrically connected to the power supply signal line PVDD, and a second pole of the first light emission controlling transistor M5 is electrically connected to the second node N2.
The gate of the second light emission control transistor M6 is electrically connected to the light emission control signal line Emit, the first pole of the second light emission control transistor M6 is electrically connected to the third node N3, and the second pole of the second light emission control transistor M6 is electrically connected to the anode of the light emitting element D.
A first plate of the storage capacitor C is electrically connected to the power signal line PVDD, and a second plate of the storage capacitor C is electrically connected to the first node N1.
The gate reset transistor M1 and the threshold compensation transistor M4 are double-gate transistors, that is, the gate reset transistor M1 includes a first reset transistor M11 and a second reset transistor M12 connected in series, the threshold compensation transistor M4 includes a first compensation transistor M41 and a second compensation transistor M42 connected in series, and a first intermediate node O1 is located between the first reset transistor M11 and the second reset transistor M12.
As shown in fig. 2, fig. 2 is a timing diagram corresponding to fig. 1, and a driving period of the pixel circuit includes a reset period t1, a charging period t2, and an emission period t3.
Taking the transistors all being P-type transistors and the enable levels of the first Scan signal line Scan1, the second Scan signal line Scan2 and the emission control signal line Emit all being low level as an example, in the reset period t1, the first Scan signal line Scan1 supplies low level, the second Scan signal line Scan2 and the emission control signal line Emit supply high level respectively, the first reset transistor M11, the second reset transistor M12 and the anode reset transistor M2 are turned on by the low level, and the reset voltage V is used to turn on the transistors respectively ref The gate of the driving transistor M0 and the anode of the light emitting element D are reset. At this time, V O1 ＝V N1 ＝V ref 。
In the charging period t2, the second Scan signal line Scan2 supplies a low level, the first Scan signal line Scan1 and the emission control signal line Emit supply a high level, respectively, and the data writing transistor M3, the first compensation transistor M41, and the second compensation transistor M42 are turned on by the low level, write the data voltage, and compensate the threshold voltage of the driving transistor M0. At this time, V O1 ＝V ref ，V N1 ＝V N3 ＝V Data -V th ，V N2 ＝V Data ，V th Is the threshold voltage of the drive transistor M0.
In the light emission period t3, the light emission control signal line Emit is supplied with the low level, the first Scan signal line Scan1 and the second Scan signal line Scan2 are supplied with the high level, and the first light emission control transistor M5 and the second light emission control transistor M6 are supplied with the low levelIs turned on, and the driving current converted by the driving transistor M0 is transmitted to the anode of the light emitting device D, so as to drive the light emitting device D to emit light. At this time, V O1 ＝V ref ，V N1 ＝V Data -V th ，V N2 ＝V PVDD ，V N3 ＝V PVEE +V OLED ，V PVEE Is the cathode voltage of the light emitting element D, V OLED Is the voltage difference between the anode and the cathode of the light emitting element D.
It is understood that the magnitude of the driving current generated by the pixel circuit depends on the magnitude of the gate-source voltage Vgs of the driving transistor M0 in the light emission period t3, and the smaller the gate-source voltage Vgs of the driving transistor M0 is, the more completely the driving transistor M0 is turned on, and the larger the driving current flows into the light emitting element D. Since the voltage of the source (first electrode) of the driving transistor M0 in the light emission period t3 is a fixed V PVDD Therefore, the magnitude of the gate voltage of the driving transistor M0 determines the magnitude of the driving current flowing into the light emitting element D.
In conjunction with the above analysis, the voltage V of the first intermediate node O1 during the light emission period t3 O1 Is lower V ref And the voltage V of the first node N1 N1 Is a V Data -V th The voltage of the first node N1 is much greater than the voltage of the first intermediate node O1. In the prior art, under the influence of the off-state leakage current of the gate reset transistor M1, the first node N1 leaks electricity to the first intermediate node O1, which results in the potential of the first node N1 being lowered. At this time, the gate-source voltage Vgs of the driving transistor M0 decreases, and the driving current flowing into the light emitting element D increases, which in turn causes the light emission luminance of the light emitting element D to increase and deviate from its standard luminance.
Considering the problem of transistor process fluctuation, the leakage characteristics of the gate reset transistors M1 of different pixel circuits are different, and for the pixel circuit with large off-state leakage current, the leakage of the first node N1 is obvious, the luminance of the light emitting element D is remarkably increased, and then a bright point is formed in the picture. Particularly, when the display panel performs low gray scale image display, the formed bright spots are more easily recognized by human eyes, resulting in poor display effect.
To solve the above problem, embodiments of the present invention provide a pixel circuit, which can effectively reduce the voltage difference between the first node N1 and the first intermediate node O1 in the light-emitting period t3, improve the transistor characteristics of the gate reset transistor, and further improve the luminance increase of the light-emitting element D caused by the leakage of the first node N1.
As shown in fig. 3, fig. 3 is another schematic structural diagram of the pixel circuit according to the embodiment of the present invention, the pixel circuit includes a driving transistor M0, a gate of the driving transistor M0 is electrically connected to a first node N1, a first pole of the driving transistor M0 is electrically connected to a second node N2, and a second pole of the driving transistor M0 is electrically connected to a third node N3.
The pixel circuit further comprises a gate reset module 1, wherein the gate reset module 1 comprises a first reset transistor M11, a second reset transistor M12 and a regulation unit 2.
The gate of the first reset transistor M11 is electrically connected to the first Scan signal line Scan1, the first pole of the first reset transistor M11 is electrically connected to the reset signal line Vref, and the second pole of the first reset transistor M11 is electrically connected to the first intermediate node O1. A gate of the second reset transistor M12 is electrically connected to the first Scan signal line Scan1, a first pole of the second reset transistor M12 is electrically connected to the first intermediate node O1, and a second pole of the first reset transistor M11 is electrically connected to the first node N1.
Referring to fig. 2, the first Scan signal line Scan1 provides an enable level (low level) during the reset period t1, and the first reset transistor M11 functions to reset the voltage V in response to the enable level of the first Scan signal during the reset period t1 ref The first intermediate node O1 is written, and the second reset transistor M12 is configured to write the voltage of the first intermediate node O1 into the first node N1 in response to the enable level of the first scan signal in the reset period t1, so as to write the reset voltage into the first node N1, and thus reset the gate of the driving transistor M0.
The first terminal of the regulating unit 2 is used for receiving a high level voltage VH during the light emitting period t3, the high level voltage VH being greater than the reset voltage V ref The second end of the regulating unit 2 is electrically connected with the first intermediate node O1, and the regulating unit 2 is used for sending outThe light period t3 raises the potential of the first intermediate node O1 with the high-level voltage VH.
In the embodiment of the present invention, by additionally providing a regulation unit 2 in the gate reset module 1, the regulation unit 2 can raise the potential of the first intermediate node O1 by using the high-level voltage VH during the light-emitting period t3, so that the first intermediate node O1 maintains a higher potential. For example, in combination with the above analysis of the operating principle of the pixel circuit, the regulating unit 2 can change the potential of the first intermediate node O1 from the reset voltage V ref Is raised to and V Data -V th A potential close to each other. At this time, the voltage difference between the first node N1 and the first intermediate node O1 is small, that is, the source-drain voltage Vds of the second reset transistor M12 is small, so that the switching characteristic of the second reset transistor is effectively improved, the leakage current prevention performance of the second reset transistor is enhanced, and the potential of the first node N1 is better kept at V Data -V th The above. In this way, even if there is a difference in the leakage characteristics of the gate reset transistors used for resetting the gates of the driving transistors in different pixel circuits, the potential of the first node N1 in the pixel circuit with serious transistor leakage can be maintained stable, so that the driving current transmitted by the pixel circuit tends to a standard value, the difference in the light emission luminance of the light emitting elements D corresponding to the pixel circuit and other pixel circuits can be reduced, and the bright spot can be avoided in the displayed image.
In an embodiment, as shown in fig. 4, fig. 4 is a schematic structural diagram of the regulating unit provided in the embodiment of the present invention, the regulating unit 2 includes a first regulating transistor M7, the first regulating transistor M7 is a P-type transistor, a gate of the first regulating transistor M7 is electrically connected to a source of the first regulating transistor M7, a drain of the first regulating transistor M7 is electrically connected to the first intermediate node O1, wherein the source of the first regulating transistor M7 is configured to receive the high-level voltage VH during the light-emitting period t3.
When the first regulating transistor M7 is a P-type transistor, based on the transistor characteristics of the P-type transistor, when the gate and the source of the first regulating transistor M7 are electrically connected, the gate-source voltage Vgs =0V of the first regulating transistor M7, and at this time, the first regulating transistor M7 is always onIn the off state. In the light emitting period t3, the high level voltage VH received by the source of the first regulating transistor M7 is higher than the reset voltage V of the drain ref Therefore, the first regulating transistor M7 generates a leakage current from the source to the drain, and the leakage current flows to the first intermediate node O1 to raise the potential of the first intermediate node O1, so that the voltage difference between the source and the drain of the second reset transistor can be reduced, the anti-leakage capability of the second reset transistor can be improved, further, the off-state leakage current of the reset module can be reduced, and the stability of the reset module can be improved. The first node N1 is better kept at the target voltage value, and the display effect of the display panel is improved.
Further, referring to fig. 4 again, the gate of the first regulating transistor M7 and the source of the first regulating transistor M7 are electrically connected to the first Scan signal line Scan1, at this time, the high-level voltage VH is the voltage of the non-enable level (high level) provided by the first Scan signal line Scan1, and the first regulating transistor M7 pulls up the potential of the first intermediate node O1 by the non-enable level of the first Scan signal in the light-emitting period t3.
By the arrangement, the grid electrode and the source electrode of the first regulating transistor M7 only need to be electrically connected with the original signal line in the panel, and an additional driving signal line does not need to be additionally arranged for the first regulating transistor M7, so that the circuit structure and the wiring complexity are simplified.
Moreover, when the source of the first control transistor M7 is electrically connected to the first Scan signal line Scan1, the first Scan signal is at a low level during the reset period t1, and at this time, the voltage difference between the source and the drain of the first control transistor M7 is small, and the leakage current is also correspondingly small, so that the leakage current does not affect the voltage transmitted to the first intermediate node O1, thereby preventing the leakage current from affecting the reset of the first node N1 and improving the reset reliability.
When the source of the first control transistor M7 is electrically connected to the first Scan signal line Scan1, with reference to table 1, the pixel circuit A1 in the table is a pixel circuit in which the first control transistor M7 is not provided and the gate reset transistor has slight leakage, the pixel circuit A2 is a pixel circuit in which the first control transistor M7 is not provided and the gate reset transistor has severe leakage, the pixel circuit B1 is a pixel circuit in which the first control transistor M7 is provided and the gate reset transistor has slight leakage, and the pixel circuit B2 is a pixel circuit in which the first control transistor M7 is provided and the gate reset transistor has severe leakage. Comparing the pixel circuit A1 and the pixel circuit A2, the driving current of the pixel circuit A2 is increased to 0.46nA, which is 43.7% higher than that of the pixel circuit A1, due to the absence of the regulation of the first regulating transistor M7. Compared with the pixel circuit B1 and the pixel circuit B2, because the first regulating transistor M7 is arranged in the pixel circuit, and based on the regulation of the first regulating transistor M7 on the voltage of the first intermediate node O1, even if the leakage of the gate reset transistor in the pixel circuit B2 is serious, the potential of the first intermediate node O1 can still be raised by using the regulating unit 2, and the leakage of the first intermediate node O1 from the first node N1 to the first intermediate node O1 is reduced, at this time, the driving current corresponding to the pixel circuit B1 does not change significantly, and is increased by only 3.1% compared with the pixel circuit A1.
TABLE 1
In an implementation manner, as shown in fig. 5, fig. 5 is another schematic structural diagram of a regulating unit provided in the embodiment of the present invention, and the pixel circuit further includes a data writing module 3 and a threshold compensation module 4. The Data writing module 3 is electrically connected with the second scanning signal line Scan2, the Data line Data and the second node N2 respectively; the threshold compensation module 4 is electrically connected to the second Scan signal line Scan2, the third node N3, and the first node N1, respectively.
Referring to fig. 2, the second Scan signal line Scan2 provides an enable level (low level) during the charging period t2, the data writing module 3 is configured to write the data voltage into the second node N2 in response to the enable level of the second Scan signal during the charging period t2, and the threshold compensation module 4 is configured to compensate the threshold voltage of the driving transistor M0 in response to the enable level of the second Scan signal during the charging period t 2. It should be noted that the threshold compensation module 4 can also adopt a single scan line to control the on/off of the scan line, and can be designed according to actual requirements.
Based on this, the gate of the first regulating transistor M7 and the source of the first regulating transistor M7 are electrically connected to the second Scan signal line Scan2, respectively, and at this time, the high level voltage VH is a voltage of a non-enable level (high level) provided by the second Scan signal line Scan2, and in the light emitting period t3, the first regulating transistor M7 pulls up the potential of the first intermediate node O1 by the non-enable level of the second Scan signal.
With the arrangement, the grid electrode and the source electrode of the first regulating transistor M7 are only electrically connected with the original signal line in the panel, and an additional driving signal line does not need to be additionally arranged for the first regulating transistor M7, so that the circuit structure and the wiring complexity are simplified.
In an implementation manner, as shown in fig. 6, fig. 6 is a schematic structural diagram of a further structure of the regulating unit according to an embodiment of the present invention, and the pixel circuit further includes a light-emitting control module 5, where the light-emitting control module 5 is electrically connected to the light-emitting control signal line Emit, the power signal line PVDD, the second node N2, the third node N3, and an anode of the light-emitting element D, respectively.
Referring to fig. 2, the emission control signal line Emit provides an enable level (low level) during the emission period t3, and the emission control module 5 serves to transmit the driving current to the anode of the light emitting element D in response to the enable level of the emission control signal during the emission period t3.
Based on this, the gate of the first regulating transistor M7 and the source of the first regulating transistor M7 are electrically connected to the power signal line PVDD, respectively, and at this time, the high-level voltage VH is the power voltage V provided by the power signal line PVDD PVDD In the light emitting period t3, the first regulating transistor M7 utilizes the power supply voltage V PVDD The potential of the first intermediate node O1 is pulled high.
With the arrangement, the grid electrode and the source electrode of the first regulating transistor M7 are only electrically connected with the original signal line in the panel, and an additional driving signal line does not need to be additionally arranged for the first regulating transistor M7, so that the circuit structure and the wiring complexity are simplified.
Moreover, due to the supply voltage V PVDD Is higher than the reset voltage V ref Is large because ofHere, the leakage current of the first regulating transistor M7 in the light emitting period t3 is large, and the potential of the first intermediate node O1 can be raised to a greater extent, so that the potential of the first intermediate node O1 approaches to the potential of the first node N1.
It should be noted that when the gate and the source of the first control transistor M7 are electrically connected to the second Scan signal line Scan2 or the power signal line PVDD, although both the second Scan signal and the power signal are at a high level in the reset period t1, the first control transistor M7 has a leakage current, because the duration of the reset period t1 is much shorter than the duration of the light emitting period t3, the leakage current does not have a great influence on the potential of the first intermediate node O1, and thus does not affect the normal reset of the gate of the driving transistor M0.
In addition, as shown in fig. 7, fig. 7 is a layout schematic diagram of a pixel circuit without a regulating unit provided in the embodiment of the present invention, and it can be known from the layout that the first Scan signal line Scan1, the second Scan signal line Scan2, and the power signal line PVDD are located near the first reset transistor M11 and the second reset transistor M12 included in the gate reset module 1 and are close to the first reset transistor M11 and the second reset transistor M12. Therefore, after the first regulating transistor M7 is additionally arranged in the gate reset module 1, the first regulating transistor M7 is relatively close to the signal line, and no matter the first regulating transistor M7 is electrically connected with the first scanning signal line Scan1, the second scanning signal line Scan2 or the power signal line PVDD, the original layout of the pixel circuit is changed and the additionally required space is small, the layout design difficulty is hardly increased, and the layout occupied space is not increased.
In addition, it should be further noted that, with reference to fig. 1, the data writing module 3 may specifically include a data writing transistor M3, the threshold compensation module 4 may specifically include a threshold compensation transistor M4, and the light-emitting control module 5 may specifically include a first light-emitting control transistor M5 and a second light-emitting control transistor M6, connection modes and operation principles of these transistors are already described in detail in the above embodiments, and are not repeated herein.
In an implementation manner, as shown in fig. 8, fig. 8 is a schematic structural diagram of the control unit 2 according to an embodiment of the present invention, and the first reset transistor M11 and the second reset transistor M12 are P-type transistors respectively. The regulation and control unit 2 comprises a second regulation and control transistor M8, the second regulation and control transistor M8 is an N-type transistor, the grid electrode of the second regulation and control transistor M8 is electrically connected with the first scanning signal line Scan1, and the source electrode of the second regulation and control transistor M8 is electrically connected with the first intermediate node O1; the drain of the second regulating transistor M8 is for receiving the high-level voltage VH during the light emission period t3.
The second regulating transistor M8 is an N-type transistor, and based on the transistor characteristics of the N-type transistor, in the reset period t1, the first Scan signal line Scan1 provides a low level, the second regulating transistor M8 is turned off, and the voltage of the drain of the second regulating transistor M8 cannot be written into the first intermediate node O1, thereby ensuring that the first intermediate node O1 normally receives the reset signal. Moreover, since the duration of the reset period t1 is short, even if the second modulation transistor M8 has an off-state leak current, the off-state leak current does not have a great influence on the potential of the first intermediate node O1. In the light-emitting period t3, the first Scan signal line Scan1 provides a high level, the second regulating transistor M8 is turned on, the high-level voltage VH received by the drain is written into the first intermediate node O1, and the potential of the first intermediate node O1 is raised.
It should be noted that the second regulating transistor M8 is different from the first regulating transistor M7, the first regulating transistor M7 is turned off in the light-emitting period t3, and the potential of the first intermediate node O1 is raised by using its off-state leakage current, and the second regulating transistor M8 is turned on in the light-emitting period t3, and the voltage of the drain is directly transmitted to the first intermediate node O1, so as to raise the potential of the first intermediate node O1. The semiconductor layer material of the N-type transistor may include at least one of an oxide semiconductor or a silicon semiconductor.
Further, referring to fig. 8 again, the drain of the second regulating transistor M8 is electrically connected to the first Scan signal line Scan1, and at this time, the high level voltage VH received by the drain of the second regulating transistor M8 is the non-enable level (high level) voltage of the first Scan signal, so that in the light emitting period t3, the high level provided by the first Scan signal line Scan1 is transmitted to the first intermediate node O1, and the potential of the first intermediate node O1 is raised.
It should be noted that, in the light-emitting period t3, if the high level voltage of the first scan signal is less than the voltage of the first node N1, after the high level of the first scan signal is written into the first node N1, the voltage of the first node N1 is still higher than the voltage of the first intermediate node O1, but the voltage difference between the first node N1 and the first intermediate node O1 is reduced, at this time, the degree of leakage from the first node N1 to the first intermediate node O1 is small, the light-emitting luminance is not greatly increased, and the bright point can be effectively weakened. If the high level voltage of the first scanning signal is greater than the voltage of the first node N1, after the high level of the first scanning signal is written into the first node N1, the voltage of the first intermediate node O1 is greater than the voltage of the first node N1, so that leakage from the first intermediate node O1 to the first node N1 is generated, and the potential of the first node N1 is raised. When the potential of the first node N1 is raised, the conduction degree of the driving transistor M0 becomes smaller, and accordingly, the driving current also becomes smaller, so that the light emitting luminance of the light emitting element D becomes lower, and a dark spot is generated in a displayed picture. However, dark spots in the picture, especially in the low gray scale picture, are difficult to be recognized by human eyes compared to bright spots, and thus the display effect can be still effectively improved compared to the prior art.
Alternatively, as shown in fig. 9, fig. 9 is a schematic diagram of another structure of the regulating unit according to the embodiment of the present invention, in which the drain of the second regulating transistor M8 is electrically connected to a constant voltage signal line CS for providing a high-level voltage VH, which is greater than the reset voltage and less than the voltage of the first node N1 in the light-emitting period t3. So set up, when the high level voltage VH who utilizes constant voltage signal line CS to provide raised first intermediate node O1, can also guarantee that first intermediate node O1's voltage can not be greater than first node N1's voltage to only weaken the bright spot, and can not produce the dark spot.
Please refer to fig. 5 to 9 again, the pixel circuit further includes an anode reset module 6, and the anode reset module 6 is electrically connected to the first Scan signal line Scan1, the reset signal line Vref, and the anode of the light emitting device D, respectively, and is configured to write a reset voltage into the anode of the light emitting device D in the reset period t1 to reset the anode of the light emitting device D. With reference to fig. 1, the anode reset module 6 may specifically include an anode reset transistor M2, and a connection manner and a working principle of the anode reset transistor M2 have been described in the above embodiments, and are not described herein again.
Based on the same inventive concept, the embodiment of the invention also provides a driving method of the pixel circuit, and the driving method of the pixel circuit is used for driving the pixel circuit shown in fig. 3.
Referring to fig. 3 again, the pixel circuit includes: a gate of the driving transistor M0 is electrically connected to the first node N1, a first pole of the driving transistor M0 is electrically connected to the second node N2, and a second pole of the driving transistor M0 is electrically connected to the third node N3; the gate reset module 1 comprises a first reset transistor M11, a second reset transistor M12 and a regulation and control unit 2, wherein the gate of the first reset transistor M11 is electrically connected with a first scanning signal line Scan1, the first pole of the first reset transistor M11 is electrically connected with a reset signal line Vref, and the second pole of the first reset transistor M11 is electrically connected with a first intermediate node O1; a gate electrode of the second reset transistor M12 is electrically connected to the first Scan signal line Scan1, a first electrode of the second reset transistor M12 is electrically connected to the first intermediate node O1, and a second electrode of the first reset transistor M11 is electrically connected to the first node N1; the first terminal of the regulating unit 2 receives a high level voltage VH during the light emitting period t3, the high level voltage VH is greater than the reset voltage, and the second terminal of the regulating unit 2 is electrically connected to the first intermediate node O1.
Referring to fig. 2, a driving cycle of the pixel circuit includes a reset period t1 and a light emitting period t3, as shown in fig. 10, fig. 10 is a flowchart of a driving method provided in an embodiment of the present invention, and the driving method includes:
step S1: in the reset period t1, the first reset transistor M11 writes a reset voltage into the first intermediate node O1 in response to the enable level of the first scan signal, and the second reset transistor M12 writes a voltage of the first intermediate node O1 into the first node N1 in response to the enable level of the first scan signal.
Step S2: in the light emission period t3, the regulation unit 2 raises the potential of the first intermediate node O1 with the high-level voltage VH.
In the embodiment of the present invention, by raising the potential of the first intermediate node O1 in the light-emitting period t3 by using the regulating unit 2, the voltage difference between the first node N1 and the first intermediate node O1 can be reduced, so as to effectively reduce the leakage degree from the first node N1 to the first intermediate node O1, so that the current value of the driving current transmitted by the pixel circuit tends to a standard value, thereby reducing the light-emitting luminance difference of the light-emitting elements D corresponding to different pixel circuits, and avoiding the bright point appearing in the displayed image.
In one embodiment, with reference to fig. 4 to 6, the regulation unit 2 includes a first regulation transistor M7, the first regulation transistor M7 is a P-type transistor, a gate of the first regulation transistor M7 is electrically connected to a source of the first regulation transistor M7, and a drain of the first regulation transistor M7 is electrically connected to the first intermediate node O1; the source of the first regulating transistor M7 receives the high-level voltage VH during the light emission period t3.
The process of raising the potential of the first intermediate node O1 by the regulation unit 2 includes: the first regulating transistor M7 is turned off, and the off-state leakage current of the first regulating transistor M7 flows from the source of the first regulating transistor M7 to the drain of the first regulating transistor M7, raising the potential of the first intermediate node O1, thereby reducing the voltage difference between the first node N1 and the first intermediate node O1, and reducing the leakage degree of the first node N1 to the first intermediate node O1.
Specifically, the source of the first regulating transistor M7 is electrically connected to the first Scan signal line Scan1, or the source of the first regulating transistor M7 is electrically connected to the second Scan signal line Scan2, or the source of the first regulating transistor M7 is electrically connected to the power signal line PVDD.
Alternatively, in another embodiment, with reference to fig. 8 and 9, the first reset transistor M11 and the second reset transistor M12 are P-type transistors, respectively; the regulation and control unit 2 comprises a second regulation and control transistor M8, the second regulation and control transistor M8 is an N-type transistor, the gate of the second regulation and control transistor M8 is electrically connected with the first scanning signal line Scan1, and the source of the second regulation and control transistor M8 is electrically connected with the first intermediate node O1; the drain of the second regulation transistor M8 is for receiving the high level voltage VH during the light emission period t3.
The process of raising the potential of the first intermediate node O1 by the regulation unit 2 includes: the second control transistor M8 is turned on, and the voltage of the drain of the second control transistor M8 is written into the source of the second control transistor M8 to raise the potential of the first intermediate node O1, so that the voltage difference between the first node N1 and the first intermediate node O1 is reduced, the first node N1 is prevented from leaking electricity to the first intermediate node O1, and the bright spot phenomenon caused by the potential drop of the first node N1 is prevented from occurring.
Specifically, the drain of the second modulation transistor M8 is electrically connected to the first Scan signal line Scan1, or the drain of the second modulation transistor M8 is electrically connected to the constant voltage signal line CS, and the driving process of the above structure is already described in the above embodiment, and is not described again here.
Based on the same inventive concept, an embodiment of the present invention further provides a display panel, as shown in fig. 11, and fig. 11 is a schematic structural diagram of the display panel provided in the embodiment of the present invention, where the display panel includes the pixel circuit 100. The specific structure of the pixel circuit 100 has been described in detail in the above embodiments, and is not described herein again.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, as shown in fig. 12, fig. 12 is a schematic structural diagram of a display panel provided in an embodiment of the present invention, and the display device includes the display panel 200. Of course, the display device shown in fig. 12 is only a schematic illustration, and the display device may be any electronic device with a display function, such as a mobile phone, a tablet computer, a notebook computer, an electronic book, or a television.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (12)
1. A pixel circuit, comprising:
the grid electrode of the driving transistor is electrically connected with a first node, the first pole of the driving transistor is electrically connected with a second node, and the second pole of the driving transistor is electrically connected with a third node;
a gate reset module including a first reset transistor, a second reset transistor, and a regulation unit, wherein,
a gate of the first reset transistor is electrically connected to a first scan signal line, a first pole of the first reset transistor is electrically connected to a reset signal line, a second pole of the first reset transistor is electrically connected to a first intermediate node, and the first reset transistor is configured to write a reset voltage to the first intermediate node in response to an enable level of the first scan signal during a reset period;
a gate of the second reset transistor is electrically connected to the first scan signal line, a first pole of the second reset transistor is electrically connected to the first intermediate node, a second pole of the first reset transistor is electrically connected to the first node, and the second reset transistor is configured to write a voltage of the first intermediate node into the first node in response to an enable level of the first scan signal during the reset period;
a first end of the regulating unit receives a high-level voltage in a light-emitting period, the high-level voltage is greater than the reset voltage, a second end of the regulating unit is electrically connected with the first intermediate node, and the regulating unit is used for raising the potential of the first intermediate node by using the high-level voltage in the light-emitting period;
the control unit comprises a first control transistor, the first control transistor is a P-type transistor, the grid electrode of the first control transistor is electrically connected with the source electrode of the first control transistor, and the drain electrode of the first control transistor is electrically connected with the first intermediate node;
the source of the first regulating transistor is for receiving the high level voltage during the light emitting period.
2. The pixel circuit according to claim 1,
the grid electrode of the first regulating transistor and the source electrode of the first regulating transistor are respectively and electrically connected with the first scanning signal line.
3. The pixel circuit according to claim 1, further comprising:
a data writing module electrically connected to the second scan signal line, the data line, and the second node, respectively, for writing a data voltage into the second node in response to an enable level of the second scan signal during a charging period;
a threshold compensation module electrically connected to the second scan signal line, the third node and the first node, respectively, for compensating a threshold voltage of the driving transistor in response to an enable level of the second scan signal during the charging period;
the grid electrode of the first regulating transistor and the source electrode of the first regulating transistor are electrically connected with the second scanning signal line respectively.
4. The pixel circuit according to claim 1, further comprising:
a light emission control module electrically connected to the light emission control signal line, the power signal line, the second node, the third node, and an anode of the light emitting element, respectively, for transmitting a driving current to the anode of the light emitting element in response to an enable level of the light emission control signal during the light emission period;
a gate of the first regulation transistor and a source of the first regulation transistor are electrically connected to the power signal line, respectively.
5. The pixel circuit of claim 1,
the first reset transistor and the second reset transistor are respectively P-type transistors;
the control unit comprises a second control transistor, the second control transistor is an N-type transistor, the grid electrode of the second control transistor is electrically connected with the first scanning signal line, and the source electrode of the second control transistor is electrically connected with the first intermediate node;
the drain of the second regulating transistor is for receiving the high level voltage during the light emitting period.
6. The pixel circuit of claim 5,
the drain electrode of the second regulating transistor is electrically connected with the first scanning signal line.
7. The pixel circuit of claim 5,
the drain electrode of the second regulating transistor is electrically connected with the constant voltage signal line;
the constant voltage signal line is used for providing a high level voltage, and the high level voltage is greater than a reset voltage and less than the voltage of the first node in the light emitting period.
8. A driving method of a pixel circuit is characterized in that,
the pixel circuit includes:
the grid electrode of the driving transistor is electrically connected with a first node, the first pole of the driving transistor is electrically connected with a second node, and the second pole of the driving transistor is electrically connected with a third node;
a gate reset module including a first reset transistor, a second reset transistor, and a regulation unit, wherein,
the grid electrode of the first reset transistor is electrically connected with a first scanning signal line, the first pole of the first reset transistor is electrically connected with a reset signal line, and the second pole of the first reset transistor is electrically connected with a first intermediate node;
a gate of the second reset transistor is electrically connected to the first scan signal line, a first pole of the second reset transistor is electrically connected to the first intermediate node, and a second pole of the first reset transistor is electrically connected to the first node;
a first end of the regulation unit receives a high-level voltage in a light-emitting period, the high-level voltage is greater than a reset voltage, and a second end of the regulation unit is electrically connected with the first intermediate node;
the driving cycle of the pixel circuit includes a reset period and a light emitting period, and the driving method includes:
in the reset period, the first reset transistor writes a reset voltage into the first intermediate node in response to an enable level of the first scan signal, and the second reset transistor writes a voltage of the first intermediate node into the first node in response to an enable level of the first scan signal;
in the light emission period, the regulation unit raises the potential of the first intermediate node by the high level voltage.
9. The driving method according to claim 8,
the control unit comprises a first control transistor, the first control transistor is a P-type transistor, the grid electrode of the first control transistor is electrically connected with the source electrode of the first control transistor, and the drain electrode of the first control transistor is electrically connected with the first intermediate node;
a source of the first regulating transistor receives a high level voltage in the light emitting period;
the process of raising the potential of the first intermediate node by the regulation unit includes: and the first regulating transistor is turned off, and the off-state leakage current of the first regulating transistor flows from the source electrode of the first regulating transistor to the drain electrode of the first regulating transistor, so that the potential of the first intermediate node is raised.
10. The driving method according to claim 8,
the first reset transistor and the second reset transistor are respectively P-type transistors;
the control unit comprises a second control transistor, the second control transistor is an N-type transistor, the grid electrode of the second control transistor is electrically connected with the first scanning signal line, and the source electrode of the second control transistor is electrically connected with the first intermediate node;
a drain of the second regulating transistor for receiving the high level voltage during the light emitting period;
the process that the regulation and control unit raises the potential of the first intermediate node comprises the following steps: and the second regulating transistor is conducted, the voltage of the drain electrode of the second regulating transistor is written into the source electrode of the second regulating transistor, and the potential of the first intermediate node is raised.
11. A display panel comprising the pixel circuit according to any one of claims 1 to 7.
12. A display device comprising the display panel according to claim 11.
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| KR102566551B1 (en) * | 2016-12-05 | 2023-08-14 | 삼성디스플레이주식회사 | Display device and method for driving the same |
| KR102348667B1 (en) * | 2017-06-15 | 2022-01-06 | 엘지디스플레이 주식회사 | Shift register and display apparatus comprising the same |
| CN110085170B (en) * | 2019-04-29 | 2022-01-07 | 昆山国显光电有限公司 | Pixel circuit, driving method of pixel circuit and display panel |
| KR102642869B1 (en) * | 2019-09-19 | 2024-03-04 | 삼성디스플레이 주식회사 | Display device |
| TWI713006B (en) * | 2019-09-24 | 2020-12-11 | 友達光電股份有限公司 | Pixel circuit |
| CN111508435B (en) * | 2020-04-29 | 2021-08-03 | 昆山国显光电有限公司 | Pixel driving circuit, display panel and terminal equipment |
| CN111613177A (en) * | 2020-06-28 | 2020-09-01 | 上海天马有机发光显示技术有限公司 | Pixel circuit, driving method thereof, display panel and display device |
| CN112259050B (en) * | 2020-10-30 | 2023-01-06 | 武汉天马微电子有限公司 | Display panel, driving method thereof and display device |
| CN214377609U (en) * | 2021-02-07 | 2021-10-08 | 昆山国显光电有限公司 | Pixel circuit, display panel and display device |
| CN113012642A (en) * | 2021-03-04 | 2021-06-22 | 京东方科技集团股份有限公司 | Pixel circuit, display panel and driving method |
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