CN114116342A - Excitation control method of application register component - Google Patents

Abstract

The invention discloses an excitation control method of an application register component, which comprises the steps of establishing an interface and a transaction which are required by a tested device, wherein the transaction corresponds to the interface; creating a register component in a verification environment of UVM, wherein the register component acquires and temporarily stores state information data of a device to be tested; the register component transmits state information data to other components and objects in the UVM through the transmission component of the UVM; creating an execution event in an excitation component of the UVM, wherein the excitation component acquires state information data through a transmission component and triggers the execution event; an execution component in the stimulus component applies the execution event and the state information data to generate and control the test stimulus. The invention combines the communication between the UVM components and the configuration database to realize the control of the generation and the sending of the stimulus according to the state of the DUT, and provides a new technical route and thought selection for the generation and the control of the stimulus so as to meet the working habits of different developers.

Description

Excitation control method of application register component

Technical Field

The invention relates to the technical field of chip verification, in particular to an excitation control method of an application register component.

Background

Generally, in order to verify a DUT (Device Under Test) designed by RTL (Register Transfer Level), it is necessary to apply corresponding input stimuli to the DUT, and verify the DUT by monitoring and comparing output results of the DUT. However, in the verification process, it is necessary to determine what stimulus is to be applied to the DUT next according to the internal state of the DUT, and therefore, it is necessary to know the internal state of the DUT in the sequence and generate the sequence _ item.

In the prior art, the following two implementation methods of fig. 1 and fig. 2 exist:

fig. 1 is a first implementation method, that is, an internal state signal in a DUT is encapsulated into an interface, and then the interface is transmitted to a verification environment through config _ db, at this time, since a sequence stimulus is mounted on a corresponding sequence r, a virtual interface handle of the internal state signal of the DUT can be taken in the sequence, and the sequence can monitor a value on the interface, so that what stimulus is to be applied to the DUT next step is finally implemented in the interface according to the internal state signal of the DUT.

Fig. 2 shows a second implementation method, in order to verify the correctness of the DUT operation function, a corresponding reference model is usually written, and then the same stimulus is applied to both to compare the output results of both, and if they are consistent, the function is considered to be expected, otherwise, where a problem may occur, further debugging determination is needed. In short, there should also be a part of internal state signals corresponding to the DUT in the reference model, and then the handle of the reference model is directly passed to the sequence, and then the sequence can be taken to the handle of the reference model because the sequence is also mounted on the sequence, so that it can finally decide what kind of stimulus to be applied to the DUT next according to the DUT internal state signals corresponding to the reference model.

Disclosure of Invention

According to an embodiment of the present invention, a method for controlling an excitation of an application register component is provided, which includes the following steps:

creating an interface and a transaction required by the tested device, wherein the transaction corresponds to the interface;

creating a register component in a verification environment of UVM, wherein the register component acquires and temporarily stores state information data of a device to be tested;

the register component transmits state information data to other components and objects in the UVM through the transmission component of the UVM;

creating an execution event in an excitation component of the UVM, wherein the excitation component acquires state information data through a transmission component and triggers the execution event;

an execution component in the stimulus component applies the execution event and the state information data to generate and control the test stimulus.

Further, the interface includes: the input interface and the output interface respectively comprise a clock control block.

Further, the registering component acquiring and temporarily storing the state information data comprises the following sub-steps:

the packaging component of the UVM acquires the state information of the tested device;

packaging the state information of the tested device by the packaging assembly to obtain state information data;

the register component acquires and temporarily stores the state information data from the packaging component.

Further, the step of the incentive component acquiring the status information data through the transmission component comprises the following sub-steps:

creating an acquisition method in a register component;

the excitation component acquires the handle of the register component through the transmission component;

the excitation component uses the handle of the register component to call the acquisition method, and the excitation component uses the acquisition method to acquire the state information data.

According to the excitation control method of the application register component, the generation and the sending of the excitation are controlled according to the state of the DUT by combining the communication between the UVM components and the configuration database, and a new technical route and a new thought selection are provided for the generation and the control of the excitation so as to meet working habits of different developers.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and are intended to provide further explanation of the claimed technology.

Drawings

FIG. 1 is a schematic diagram of a prior art excitation control method using register elements;

FIG. 2 is a schematic diagram of a second prior art excitation control method using register elements;

FIG. 3 is a flowchart of an excitation control method using register elements according to an embodiment of the present invention;

FIG. 4 is a flowchart of the substeps of step S2 according to an embodiment of the present invention;

FIG. 5 is a flowchart of the substeps of step S4 according to an embodiment of the present invention;

FIG. 6 is an abstracted DUT example block diagram illustrating an example precision matching module;

FIG. 7 is a schematic diagram of an excitation control method using register elements according to an embodiment of the present invention;

fig. 8 is a schematic diagram of communications between application uvm _ tlm _ analysis _ fifo in fig. 7.

Detailed Description

The present invention will be further explained by describing preferred embodiments of the present invention in detail with reference to the accompanying drawings.

First, an excitation control method based on a Universal Verification Methodology (UVM) according to an embodiment of the present invention will be described with reference to fig. 3 to 8, where the excitation control method is used for chip Verification and has a wide application range.

As shown in fig. 3, the excitation control method of the application register component according to the embodiment of the present invention includes the following steps:

in S1, interfaces and transactions required by the Device Under Test (DUT), which correspond to the interfaces, are created as shown in fig. 3 and 7.

Further, the interface includes: the input interface and the output interface respectively comprise a clock control block, so that driving and monitoring are facilitated.

In S2, as shown in fig. 3 and 7, a register component (tlm _ analysis _ fifo) is created in the verification environment (env) of the UVM, and the register component (tlm _ analysis _ fifo) acquires and temporarily stores state information data of the Device Under Test (DUT).

Further, the register component (tlm _ analysis _ fifo) acquires and temporarily stores the status information data, comprising the sub-steps of:

in S21, the UVM package assembly (monitor) acquires status information of the Device Under Test (DUT), as shown in fig. 4.

In S22, as shown in fig. 4, the package component (monitor) packages the state information of the Device Under Test (DUT) and obtains state information data.

In S23, as shown in fig. 4, the register element (tlm _ analysis _ fifo) acquires and temporarily stores the state information data from the package element (monitor).

In S3, the register component (tlm _ analysis _ fifo) transfers the state information data to other components and objects in the UVM through the transfer component (config _ db) of the UVM, as shown in fig. 3.

In S4, as shown in fig. 3, an execution event is created in the stimulus component (sequence) of the UVM, and the stimulus component (sequence) acquires the state information data through the pass component (config _ db) and triggers the execution event.

Further, the obtaining of the status information data by the stimulus component (sequence) through the passing component (config _ db) comprises the sub-steps of:

in S41, as shown in fig. 5, a fetch method is created in the register element (tlm _ analysis _ fifo).

In S42, as shown in fig. 5, the stimulus component (sequence) acquires the handle of the register component (tlm _ analysis _ fifo) through the pass component (config _ db).

In S43, as shown in fig. 5, the stimulus component (sequence) calls the acquisition method using the handle of the register component (tlm _ analysis _ fifo), and the stimulus component (sequence) acquires the state information data using the acquisition method.

In S5, as shown in fig. 3, the execution component (sequence) in the stimulus component (sequence) applies the execution event and state information data to generate and control the test stimulus, so as to provide more implementation method choices for the verifier in the actual chip verification work.

This embodiment generates and controls test stimuli for the DUT as follows:

sending a write request, fully writing the internal storage space until write failure occurs, namely the storage space is fully written, and monitoring whether the total written data quantity is consistent with expectation or not at the moment, thereby helping to judge whether the storage space and the write request operation are successfully executed or not; and then sending a read request to read (delete) the previously written data until a read (delete) failure occurs, namely the storage space is emptied, monitoring whether the total written data quantity is consistent with the expectation, and monitoring and comparing whether the read data is consistent with the previously written data, thereby helping to judge whether the read-write function is correct.

As shown in fig. 7, according to the stimulus control method using register elements in the embodiment of the present invention, in the UVM verification platform, the present embodiment adds the register element (tlm _ analysis _ fifo) to the verification environment (env), and acquires the status information data broadcasted by the package component (monitor) through the UVM communication port, where the status information data includes the status information of the DUT, and then sends the status information data to the execution component (sequence), so as to finally realize the generation and control of the input stimulus by the execution component (sequence).

The present invention is exemplified by taking an accurate matching module as an example of a DUT, where the accurate matching module is used to complete mapping between key (addr) and pointer (data), and the module is often used in an ethernet switching chip in an instantiated manner. For the sake of example, the exact match module may be simply understood as a dictionary-type database (database) with basic write and read (delete) functions.

Therefore, a block diagram of the DUT obtained after abstraction is shown in fig. 6, and a verification platform corresponding to the DUT is built as shown in fig. 6.

The input ports are:

clk: a clock signal;

rst _ n: a low level reset signal;

vld: a data valid signal;

cmd: 1' b 0: a write request signal;

1' b 1: a read (delete) request signal;

addr: an address signal; data: a data signal.

The output port thereof has:

vld: a data valid signal;

rslt: a request execution success or failure signal; 1' b0, execution failed; 1' b1, execution was successful;

data: the data corresponding to the previous read (delete) request.

It can be seen that the patent is still built based on a typical UVM authentication platform, but UVM _ tlm _ analysis _ fifo is added mainly in the env authentication environment for communication connection, and the UVM configuration database is used for communication.

Further, as shown in fig. 8, the implementation principle of the present invention is UVM fifo communication, in the figure, circles and squares identify communication ports, and the communication between the component a and the component B is completed by using these ports and their interface methods, so UVM _ tlm _ analysis _ fifo mainly functions as a data buffer and a communication connection.

Further, as shown in fig. 8, the components a and uvm _ tlm _ analysis _ fifo are connected through put series ports. The component A calls interface methods (put, try _ put and can _ put) related to the put series port to send the transaction data to uvm _ tlm _ analysis _ fifo, then uvm _ tlm _ analysis _ fifo receives the data sent by the component A by using the put series interface methods realized in the component A and buffers the data into uvm _ tlm _ analysis _ fifo, and simultaneously broadcasts the received data to the outside by using the put _ ap port; the components B and uvm _ tlm _ analysis _ fifo are connected through get or peek family ports. The component B calls the get or peek series method to acquire the transaction data from the uvm _ tlm _ analysis _ fifo, and then the uvm _ tlm _ analysis _ fifo fetches the data in the cache to the component B using the get or peek series interface method implemented inside it, while broadcasting the data fetched from the cache to the outside using the get _ ap port.

In the above, with reference to fig. 3 to 8, a stimulus control method for applying a register component according to an embodiment of the present invention is described, and the control of generation and transmission of a stimulus according to a state of a DUT is implemented in combination with communication between UVM components and a configuration database, so as to provide a new technical route and a new concept choice for the generation and control of the stimulus to meet working habits of different developers.

It should be noted that, in the present specification, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.

Claims (4)

1. An excitation control method using a register component, comprising the steps of:

creating an interface and a transaction required by a device under test, wherein the transaction corresponds to the interface;

creating a register component in a verification environment of UVM, wherein the register component acquires and temporarily stores state information data of the device under test;

the register component transmits the state information data to other components and objects in the UVM through a transmission component of the UVM;

creating an execution event in an excitation component of the UVM, the excitation component acquiring the state information data through the transfer component and triggering the execution event;

and an execution component in the excitation component generates and controls test excitation by applying the execution event and the state information data.

2. The method for stimulus control of an application register unit according to claim 1, wherein said interface comprises: the input interface and the output interface respectively comprise a clock control block.

3. The excitation control method for the application register unit according to claim 1, wherein the register unit obtains and temporarily stores the status information data, comprising the sub-steps of:

the packaging component of the UVM acquires the state information of the device under test;

the packaging assembly packages the state information of the tested device to obtain the state information data;

the registering component acquires and temporarily stores the state information data from the packaging component.

4. An actuation control method for an application register element according to claim 1, wherein said actuation element acquiring said status information data via said transfer element comprises the sub-steps of:

creating an acquisition method in the register component;

the excitation component acquires the handle of the register component through the transmission component;

the excitation component calls the acquisition method by using the handle of the register component, and the excitation component acquires the state information data by using the acquisition method.

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