CN114116137A - Simulation method and device for error correcting code in storage system, storage medium and equipment - Google Patents
Simulation method and device for error correcting code in storage system, storage medium and equipment Download PDFInfo
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- CN114116137A CN114116137A CN202111470342.6A CN202111470342A CN114116137A CN 114116137 A CN114116137 A CN 114116137A CN 202111470342 A CN202111470342 A CN 202111470342A CN 114116137 A CN114116137 A CN 114116137A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
- G06F9/45504—Abstract machines for programme code execution, e.g. Java virtual machine [JVM], interpreters, emulators
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
Abstract
The application discloses a simulation method and device, a storage medium and equipment of an error correcting code in a storage system, wherein the method comprises the following steps: performing binomial distribution operation on the first coded data frame by taking a preset parameter as an input parameter based on a binomial distribution random number generation algorithm to obtain a quantity parameter; based on a uniform distribution random number generation algorithm, performing uniform distribution operation on the first coded data frame to obtain the bit flipping positions with the number parameters different from each other, and outputting an error pattern, wherein the error pattern comprises the error positions in the bit flipping positions; adding the error pattern into the first coding data frame, and performing flip bit calculation to obtain a second coding data frame; and decoding the second coded data frame, outputting a decoding result and collecting the decoding result. The method and the device reduce the calculation amount of binomial distribution operation and uniform distribution operation, reduce development cost, have flexible implementation mode and improve universality.
Description
Technical Field
The present application relates to the field of data storage technologies, and in particular, to a method and an apparatus for simulating an error correction code in a storage system, a storage medium, and a computer device.
Background
Hard decision reading is one of the most important reading modes of a solid state disk (NAND) memory, and the reading mode is characterized in that voltage comparison is only performed once between every two adjacent threshold voltages, the reading mode is rough, only whether stored information is bit 1 or bit 0 can be read, more detailed information cannot be given, subsequent error correction is not facilitated, but the reading delay caused by the reading mode is minimum, and therefore the reading mode with the highest priority is adopted in the whole product life cycle.
Hard-decision reads introduce errors with a certain probability, and as the lifetime of the memory gradually increases, the error probability is synchronously raised. Therefore, the solid state disk storage controller needs to adopt a relatively powerful Error Control Coding (ECC) as a countermeasure, and in the prior art, referring to fig. 1, a storage system can be highly generalized by using a model, wherein a Binary Symmetric Channel (BSC) is a widely recognized Channel model and is commonly used in system simulation shown in 0, the BSC Channel is a discrete memoryless Channel, and has only two symbols, i.e., 0 and 1, in input and output, and the probability of sending 0 and receiving 1 and sending 1 and receiving 0 (i.e., bit Error) is the same, so the Channel is Symmetric. At this time, the conditional error probability (CP) is represented by p, and the transition probability of the binary symmetric channel is shown as 0.
In the prior art, when a BSC channel is simulated, probability operation must be performed on each bit passing through the channel to determine whether the bit is turned over, and a uniformly distributed random number generator or function is usually called once every probability operation, so that the amount of calculation is very large.
Disclosure of Invention
In view of this, the present application provides a simulation method and apparatus for error correction codes in a storage system, a storage medium, and a computer device, which reduce the computation amount of binomial distribution and uniform distribution, reduce the development cost, have a very flexible implementation manner, and improve the universality.
According to an aspect of the present application, there is provided an emulation method of an error correction code in a memory system, the method including:
performing binomial distribution operation on the first coded data frame by taking a preset parameter as an input parameter based on a binomial distribution random number generation algorithm to obtain a quantity parameter;
based on a uniform distribution random number generation algorithm, performing uniform distribution operation on the first coded data frame to obtain the bit flipping positions with the number parameters different from each other, and outputting an error pattern, wherein the error pattern comprises the error positions in the bit flipping positions;
adding the error pattern into the first coded data frame, and performing flip bit calculation on the first coded data frame to obtain a second coded data frame;
and decoding the second coded data frame, outputting a decoding result and collecting the decoding result.
Optionally, the preset parameters include a length value of the encoded data frame and an original bit error probability value, where the length value of the encoded data frame is designated as N and the original bit error probability value is designated as p.
Optionally, the binomial distribution operation is performed at least 1 time, and the uniform distribution operation is performed at least pN times.
Optionally, the adding the error pattern to the first encoded data frame and performing flip bit calculation on the first encoded data frame to obtain a second encoded data frame specifically includes:
and adding the error pattern into the first coding data frame, and inverting the bits at the inverted bit positions in the first coding data frame according to the error pattern.
Optionally, the decoding the second encoded data frame, outputting a decoding result, and collecting specifically includes:
decoding the second encoded data frame by using a decoding module, and outputting the decoding result;
and writing the decoding result into a recording file or displaying the decoding result on a monitor, wherein the decoding result comprises the encoded data frame and the error pattern after decoding is finished.
Optionally, the method further comprises:
and identifying the decoding result based on a preset simulation suspension condition, judging whether the simulation process is suspended or not, and repeating the simulation process if the simulation process is not suspended, wherein the preset simulation suspension condition comprises the number of times of decoding failure and the number of frames for completing decoding.
Optionally, the simulation method of the error correction code in the storage system is performed at the host side or at the host side and the hardware platform or at the hardware platform.
According to another aspect of the present application, there is provided an emulation apparatus of an error correction code in a memory system, the apparatus including:
the binomial distribution calculation module is used for carrying out binomial distribution operation on the first coding data frame by taking a preset parameter as an input parameter based on a binomial distribution random number generation algorithm to obtain a quantity parameter;
a uniform distribution calculation module, configured to perform uniform distribution calculation on the first encoded data frame based on a uniform distribution random number generation algorithm, obtain bit flipping positions with different number parameters, and output an error pattern, where the error pattern includes an error position in the bit flipping positions;
the flip bit calculation module is used for adding the error pattern into the first coded data frame and performing flip bit calculation on the first coded data frame to obtain a second coded data frame;
and the decoding module is used for decoding the second coded data frame, outputting a decoding result and collecting the decoding result.
Optionally, the binomial distribution calculating module is specifically configured to:
the preset parameters comprise a length value of an encoding data frame and an original bit error probability value, wherein the length value of the encoding data frame is marked as N, and the original bit error probability value is marked as p.
Optionally, the binomial distribution calculating module and the uniform distribution calculating module are specifically configured to:
the binomial distribution operation is performed at least 1 time, and the uniform distribution operation is performed at least pN times.
Optionally, the flipped bit calculating module is specifically configured to:
and adding the error pattern into the first coding data frame, and inverting the bits at the inverted bit positions in the first coding data frame according to the error pattern.
Optionally, the decoding module is specifically configured to:
decoding the second encoded data frame by using a decoding module, and outputting the decoding result;
and writing the decoding result into a recording file or displaying the decoding result on a monitor, wherein the decoding result comprises the encoded data frame and the error pattern after decoding is finished.
Optionally, the apparatus for emulating an error correction code in a storage system further includes:
and the simulation stopping judgment module is used for identifying the decoding result based on a preset simulation stopping condition, judging whether the simulation process is stopped or not, and repeating the simulation process if the simulation process is not stopped, wherein the preset simulation stopping condition comprises the number of times of decoding failure and the number of frames for completing decoding.
Optionally, the emulation apparatus for an error correction code in the storage system is specifically configured to: at the host side or at the host side and the hardware platform or at the hardware platform.
According to yet another aspect of the present application, there is provided a storage medium having stored thereon a computer program which, when executed by a processor, implements a method of simulating error correction codes in a storage system as described above.
According to yet another aspect of the present application, there is provided a computer device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, the processor implementing the method for emulating an error correction code in a storage system as described above when executing the program.
By means of the technical scheme, the simulation method and device for the error correcting code in the storage system, the storage medium and the computer equipment are provided, the simulation method for the error correcting code in the storage system obtains the number of errors of each frame of coded data after a channel simulation process through binomial distribution calculation, obtains different error positions through uniform distribution calculation, and reduces N times of random number operation of each coded data frame to 1 time of binomial distribution random operation and pN times of uniform distribution random number operation, so that the calculation amount is greatly reduced, the development cost is reduced, the realization mode is flexible, and the universality is high.
The foregoing description is only an overview of the technical solutions of the present application, and the present application can be implemented according to the content of the description in order to make the technical means of the present application more clearly understood, and the following detailed description of the present application is given in order to make the above and other objects, features, and advantages of the present application more clearly understandable.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:
FIG. 1 is a diagram of a generalized model of a prior art storage system;
FIG. 2 is a diagram of a BSC channel model in the prior art;
FIG. 3 is a logic flow diagram of a method for emulating an error correction code in a memory system according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of ECC simulation logic provided in accordance with an embodiment of the present application;
FIG. 5 is a schematic diagram of an ECC simulation system according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an emulation apparatus for an error correction code in a memory system according to an embodiment of the present application.
Detailed Description
The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.
In this embodiment, an emulation method for an error correction code in a storage system is provided, where the method is applied to a computer device, as shown in fig. 3, the method includes:
specifically, the error number of each frame of encoded data after passing through a BSC channel is obtained by a Binomial Distribution random number generation algorithm, specifically, for an ECC code containing N bits, after passing through a BSC channel with a conditional error probability p, it is equivalent to performing N independent repeated bernoulli tests, where E represents the number of bit flipping occurrences in the N-fold bernoulli test, the possible value of E is 0, 1, …, N, and for each k (0 ≦ k ≦ N), an event { E ═ k } is "flipping bit number k", a discrete probability Distribution of a random variable E is a Binomial Distribution (Binomial Distribution), in the memory field, p is usually represented by a Raw bit error probability (RBER), and when a specific Raw bit error probability is determined as a simulation condition, the bit number of each frame of errors can be randomly determined by a Binomial Distribution function, the error locations of the bits are then determined according to a uniform distribution function.
102, performing uniform distribution operation on the first encoded data frame based on a uniform distribution random number generation algorithm to obtain bit flip positions with mutually different quantity parameters, and outputting an error pattern, wherein the error pattern comprises error positions in the bit flip positions;
specifically, E different bit flipping positions are generated by using a uniform distribution random number generation algorithm according to a uniform distribution function, the error positions of the bits are determined, and finally an error pattern is output, wherein the error pattern can simultaneously contain E and all the error positions or only contain the error positions.
specifically, an error pattern output by the BSC channel simulation is added to the encoded data frame, that is, bits at corresponding flipped bit positions in the encoded data frame are inverted according to the error pattern.
And 104, decoding the second coded data frame, outputting a decoding result and collecting the decoding result.
Specifically, the ECC decoding module decodes the encoded data frame to which the error pattern is added, and outputs a decoding result, where the decoding result includes information such as whether decoding is successful, iteration times, the number and position of found error bits, and the encoded data frame obtained after decoding is successful.
By applying the technical scheme of the embodiment, the simulation method of the error correcting code in the storage system comprises the steps of obtaining the number of errors of each frame of coded data after a channel simulation process through binomial distribution calculation, obtaining different error positions through an evenly-distributed random number generator, and reducing N times of random number operation of each coded data frame to 1 time of binomial distribution random number operation and pN times of evenly-distributed random number operation, so that the calculation amount is greatly reduced, the development cost is reduced, the realization mode is flexible, and the universality is high.
In this embodiment of the present application, optionally, the preset parameter includes a length value of the encoded data frame and an original bit error probability value, where the length value of the encoded data frame is designated as N, and the original bit error probability value is designated as p.
In the above embodiment, the preset parameter setting step is executed only during initialization, and is configured to calibrate the encoded data frame length N and the original bit error probability p, where N and p are input parameters, and a quantity integer is obtained by using a binomial distribution random number generation algorithm, and is calibrated as E.
In this embodiment of the present application, optionally, the binomial distribution operation is performed at least 1 time, and the uniform distribution operation is performed at least pN times.
In the above embodiment, since RBER in the NAND memory life cycle is usually less than 10 "2, the present application only needs at least 1 second-term distribution random operation and pN uniform distribution random number operation on average, and the average calculation amount on channel simulation is reduced to below 1/100 compared with the prior art.
In this embodiment of the application, optionally, the adding the error pattern to the first encoded data frame and performing flip bit calculation on the first encoded data frame to obtain a second encoded data frame specifically includes: and adding the error pattern into the first coding data frame, and inverting the bits at the inverted bit positions in the first coding data frame according to the error pattern.
In the above embodiment, the error pattern inverts the bits at the corresponding flipped bit positions in the encoded data frame, if the ECC encoder outputs data before bit mapping, i.e. 1 becomes 0 and 0 becomes 1, otherwise, L becomes + L and + L becomes-L, where L is a positive integer.
In this embodiment of the present application, optionally, the decoding the second encoded data frame, outputting a decoding result, and collecting the decoding result specifically includes: decoding the second encoded data frame by using a decoding module, and outputting the decoding result; and writing the decoding result into a recording file or displaying the decoding result on a monitor, wherein the decoding result comprises the encoded data frame and the error pattern after decoding is finished.
In the above embodiment, the ECC decoding module decodes the encoded data frame to which the error pattern is added, outputs the decoding result, collects the output of the ECC decoding module and the output of the error pattern of the BSC, and writes necessary information into a recording file or displays the necessary information on a monitor, where the decoding result includes information such as whether decoding is successful, the number of iterations, the number and positions of found error bits, and the encoded data frame obtained after decoding is successful.
In this embodiment of the present application, optionally, the method further includes: and identifying the decoding result based on a preset simulation suspension condition, judging whether the simulation process is suspended or not, and repeating the simulation process if the simulation process is not suspended, wherein the preset simulation suspension condition comprises the number of times of decoding failure and the number of frames for completing decoding.
In the above embodiment, the simulation termination condition determining step determines whether to terminate the current simulation according to information such as the number of decoding failures, the number of already decoded frames, and the like, and if the simulation process is determined to be terminated, the simulation process is not performed any more, and the decoding result can be used as an output result; if the simulation process is not stopped, the simulation process is continuously repeated on the first coding data frame.
In this embodiment of the present application, optionally, the method for simulating the error correction code in the storage system is performed at the host side, or performed at the host side and the hardware platform, or performed at the hardware platform.
In the above embodiment, referring to fig. 5, taking the configuration of a BSC channel simulation system at a Host end as an example, the system includes a Host and an ECC module, where the Host implements a BSC channel simulation function, controls a plurality of ECC modules to perform simulation, and records a simulation result, and the Host further includes the following functional modules:
and (3) control software: coordinating a plurality of thread groups to simultaneously generate mutually independent BSC simulation channels, receiving various output and state parameters sent back by each ECC module through an interface, and writing necessary results into a record file;
and (3) thread group: the simulation system comprises 1 or more CPU threads, BSC channel simulation software runs on each thread, and the output generated by the simulation system is a complete or partial error pattern which needs to be added on each coded data frame to be simulated. In addition, in order to improve the calculation efficiency, a binomial distribution and uniform distribution random number generation function (such as the viRngBinomial and vsrnnguniform functions of Intel) written based on a parallel instruction set can be adopted, and compared with the traditional method, the calculation rate can be improved by more than one order of magnitude;
interface: sending error patterns generated by each thread group to each ECC module through interfaces and protocols (including but not limited to PCIE protocol, NVMe protocol and TCP/IP protocol) of a computer and external hardware equipment, controlling the modules to simulate and receiving feedback information of the modules;
recording a file: recording various information of the simulation process, including but not limited to the state log of each ECC module, simulation result and other information;
in addition, the ECC module simulates according to an instruction and a complete or partial error pattern below a host interface, and reports a simulation result and the state information of the module to the host, and an ECC platform built through hardware, including but not limited to an FPGA board card and an ASIC chip board card, must include an ECC decoder on the hardware platform, but an ECC encoder is not a necessary option.
If the operation speed or the interface transmission speed of the Host is limited, part or all of the binomial distribution or uniform distribution random number generation module in the BSC channel simulation can be transplanted to a hardware platform to be realized. The hardware platform may be on the ECC module or a separate hardware platform.
When the hardware platform is arranged on the ECC modules, each ECC module can obtain a complete error pattern only by combining the partial error pattern transmitted by the host with the local partial error pattern; when the hardware platform is an independent hardware platform, the host end is only responsible for simulation control and result collection, and BSC channel simulation is completely realized by hardware except host.
Further, as a specific implementation of the method in fig. 3 and fig. 4, an embodiment of the present application provides an emulation apparatus for an error correction code in a storage system, as shown in fig. 6, the apparatus includes: the binomial distribution calculation module is used for carrying out binomial distribution operation on the first coding data frame by taking a preset parameter as an input parameter based on a binomial distribution random number generation algorithm to obtain a quantity parameter; a uniform distribution calculation module, configured to perform uniform distribution calculation on the first encoded data frame based on a uniform distribution random number generation algorithm, obtain bit flipping positions with different number parameters, and output an error pattern, where the error pattern includes an error position in the bit flipping positions; the flip bit calculation module is used for adding the error pattern into the first coded data frame and performing flip bit calculation on the first coded data frame to obtain a second coded data frame; and the decoding module is used for decoding the second coded data frame, outputting a decoding result and collecting the decoding result.
The binomial distribution calculation module is specifically configured to: the preset parameters comprise a length value of an encoding data frame and an original bit error probability value, wherein the length value of the encoding data frame is marked as N, and the original bit error probability value is marked as p.
The binomial distribution calculation module and the uniform distribution calculation module are specifically used for performing binomial distribution calculation for at least 1 time, and performing uniform distribution calculation for at least pN times.
Wherein the flipped bit calculation module is specifically configured to: and adding the error pattern into the first coding data frame, and inverting the bits at the inverted bit positions in the first coding data frame according to the error pattern.
Wherein the decoding module is specifically configured to: decoding the second encoded data frame by using a decoding module, and outputting the decoding result; and writing the decoding result into a recording file or displaying the decoding result on a monitor, wherein the decoding result comprises the encoded data frame and the error pattern after decoding is finished.
The emulation apparatus for an error correction code in the storage system further includes: and the simulation stopping judgment module is used for identifying the decoding result based on a preset simulation stopping condition, judging whether the simulation process is stopped or not, and repeating the simulation process if the simulation process is not stopped, wherein the preset simulation stopping condition comprises the number of times of decoding failure and the number of frames for completing decoding.
The emulation apparatus for an error correction code in a storage system is specifically configured to: at the host side or at the host side and the hardware platform or at the hardware platform.
It should be noted that other corresponding descriptions of the functional units related to the emulation apparatus for an error correction code in a storage system provided in the embodiment of the present application may refer to corresponding descriptions in the methods in fig. 3 to fig. 4, and are not described herein again.
Based on the methods shown in fig. 3 to 4, correspondingly, the present application further provides a storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the computer program implements the method for simulating the error correction code in the storage system shown in fig. 3 to 4.
Based on such understanding, the technical solution of the present application may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.), and includes several instructions for enabling a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method according to the implementation scenarios of the present application.
Based on the above methods shown in fig. 3 to fig. 4 and the virtual device embodiment shown in fig. 6, in order to achieve the above object, an embodiment of the present application further provides a computer device, which may specifically be a personal computer, a server, a network device, and the like, where the computer device includes a storage medium and a processor; a storage medium for storing a computer program; a processor for executing a computer program to implement the above-described emulation method of an error correction code in a memory system as shown in fig. 3 to 4.
Optionally, the computer device may also include a user interface, a network interface, a camera, Radio Frequency (RF) circuitry, sensors, audio circuitry, a WI-FI module, and so forth. The user interface may include a Display screen (Display), an input unit such as a keypad (Keyboard), etc., and the optional user interface may also include a USB interface, a card reader interface, etc. The network interface may optionally include a standard wired interface, a wireless interface (e.g., a bluetooth interface, WI-FI interface), etc.
It will be appreciated by those skilled in the art that the present embodiment provides a computer device architecture that is not limiting of the computer device, and that may include more or fewer components, or some components in combination, or a different arrangement of components.
The storage medium may further include an operating system and a network communication module. An operating system is a program that manages and maintains the hardware and software resources of a computer device, supporting the operation of information handling programs, as well as other software and/or programs. The network communication module is used for realizing communication among components in the storage medium and other hardware and software in the entity device.
Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by software plus a necessary general hardware platform, and also can reduce the calculation amount of the binomial distribution operation and the uniform distribution operation through hardware implementation, thereby reducing the development cost, and the implementation manner is flexible and the universality is improved.
Those skilled in the art will appreciate that the figures are merely schematic representations of one preferred implementation scenario and that the blocks or flow diagrams in the figures are not necessarily required to practice the present application. Those skilled in the art will appreciate that the modules in the devices in the implementation scenario may be distributed in the devices in the implementation scenario according to the description of the implementation scenario, or may be located in one or more devices different from the present implementation scenario with corresponding changes. The modules of the implementation scenario may be combined into one module, or may be further split into a plurality of sub-modules.
The above application serial numbers are for description purposes only and do not represent the superiority or inferiority of the implementation scenarios. The above disclosure is only a few specific implementation scenarios of the present application, but the present application is not limited thereto, and any variations that can be made by those skilled in the art are intended to fall within the scope of the present application.
Claims (10)
1. A method for emulating an error correction code in a memory system, the method comprising:
performing binomial distribution operation on the first coded data frame by taking a preset parameter as an input parameter based on a binomial distribution random number generation algorithm to obtain a quantity parameter;
based on a uniform distribution random number generation algorithm, performing uniform distribution operation on the first coded data frame to obtain the bit flipping positions with the number parameters different from each other, and outputting an error pattern, wherein the error pattern comprises the error positions in the bit flipping positions;
adding the error pattern into the first coded data frame, and performing flip bit calculation on the first coded data frame to obtain a second coded data frame;
and decoding the second coded data frame, outputting a decoding result and collecting the decoding result.
2. The method of claim 1, wherein the preset parameters comprise a length value of the encoded data frame and an original bit error probability value, wherein the encoded data frame length value is designated as N and the original bit error probability value is designated as p.
3. The method of claim 2, wherein the binomial distribution operation is performed at least 1 time and the uniform distribution operation is performed at least pN times.
4. The method according to claim 1, wherein the adding the error pattern to the first encoded data frame and performing a flip bit calculation on the first encoded data frame to obtain a second encoded data frame specifically comprises:
and adding the error pattern into the first coding data frame, and inverting the bits at the inverted bit positions in the first coding data frame according to the error pattern.
5. The method according to claim 1, wherein said decoding the second encoded data frame, outputting the decoding result and collecting comprises:
decoding the second encoded data frame by using a decoding module, and outputting the decoding result;
and writing the decoding result into a recording file or displaying the decoding result on a monitor, wherein the decoding result comprises the encoded data frame and the error pattern after decoding is finished.
6. The method of claim 1, further comprising:
and identifying the decoding result based on a preset simulation suspension condition, judging whether the simulation process is suspended or not, and repeating the simulation process if the simulation process is not suspended, wherein the preset simulation suspension condition comprises the number of times of decoding failure and the number of frames for completing decoding.
7. The method according to claim 1, wherein the emulation method of the error correction code in the storage system is performed at a host side or at the host side and a hardware platform or at the hardware platform.
8. An apparatus for emulating an error correction code in a memory system, the apparatus comprising:
the binomial distribution calculation module is used for carrying out binomial distribution operation on the first coding data frame by taking a preset parameter as an input parameter based on a binomial distribution random number generation algorithm to obtain a quantity parameter;
a uniform distribution calculation module, configured to perform uniform distribution calculation on the first encoded data frame based on a uniform distribution random number generation algorithm, obtain bit flipping positions with different number parameters, and output an error pattern, where the error pattern includes an error position in the bit flipping positions;
the flip bit calculation module is used for adding the error pattern into the first coded data frame and performing flip bit calculation on the first coded data frame to obtain a second coded data frame;
and the decoding module is used for decoding the second coded data frame, outputting a decoding result and collecting the decoding result.
9. A storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the method of any of claims 1 to 7.
10. A computer device comprising a storage medium, a processor and a computer program stored on the storage medium and executable on the processor, characterized in that the processor implements the method of any one of claims 1 to 7 when executing the computer program.
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| CN105247793A (en) * | 2013-05-24 | 2016-01-13 | 爱思开海力士有限公司 | Miscorrection detection for error correcting codes |
| US20190268018A1 (en) * | 2018-02-28 | 2019-08-29 | Hewlett Packard Enterprise Development Lp | Error correction code words with binomial bit error distribution |
| CN111989745A (en) * | 2018-04-16 | 2020-11-24 | 国际商业机器公司 | General purpose high and low random bit error correction logic |
| CN109669669A (en) * | 2018-12-06 | 2019-04-23 | 青岛镕铭半导体有限公司 | Error code generation method and error code generator |
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