CN114095724A

CN114095724A - Method for realizing and detecting rolling line period of TDICMOS (time domain coherent ICMOS)

Info

Publication number: CN114095724A
Application number: CN202111444410.1A
Authority: CN
Inventors: 余达; 薛栋林; 薛旭成; 石俊霞; 宁永慧; 朱立禄; 李嘉
Original assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Current assignee: Changchun Institute of Optics Fine Mechanics and Physics of CAS
Priority date: 2021-11-30
Filing date: 2021-11-30
Publication date: 2022-02-25
Anticipated expiration: 2041-11-30
Also published as: CN114095724B

Abstract

A method for realizing and detecting a rolling line period of a TDICMOS relates to the technical field of TDICMOS imaging, and solves the problems that when an existing multi-spectrum TDICMOS detector is used for imaging, the rolling line period which is being executed is interrupted due to local timing deviation or transmission interval deviation in the execution process of the rolling line period; a 422 analysis and line period processing module of the imaging system adopts a state machine to realize the control of a RAM of a ping-pong structure and the rolling output line period; the rolling timing position is not compared with the local time by adopting the calculated execution sub-time, but is executed by adopting a counter timing mode of a local clock, so that the interruption of a continuous execution process within one second caused by updating of an externally input time code is avoided. To achieve a relatively accurate delay, the time taken for the state machine to cycle is deducted during counting.

Description

Method for realizing and detecting rolling line period of TDICMOS (time domain coherent ICMOS)

Technical Field

The invention relates to a method for realizing and detecting a rolling line period of a TDICMOS (time domain transfer function), in particular to a method for realizing and detecting a rolling line period of a TDICMOS (time domain transfer function) obtained by a high dynamic transfer function.

Background

When the multi-spectral-band TDICMOS detector is used for imaging, fine image motion compensation is needed for obtaining high-dynamic transfer function imaging, so that the running line period can be adjusted for multiple times within 1 second, and the line period is enabled to change in a rolling mode. One convenient method is to send the execution time and the multi-packet period values at intervals of 1s, and then have the imaging unit execute the packet period values in order of equal time intervals. During the execution of the rolling line cycle, the rolling line cycle being executed may be interrupted due to a deviation in local timing or a deviation in transmission interval.

Disclosure of Invention

The invention provides a method for realizing and detecting a rolling line period of a multi-spectral band TDICMOS (time domain coherent integration multiple-spectral band) detector, aiming at solving the problems that the rolling line period is interrupted and the like in the process of executing the rolling line period due to the deviation of local timing or the deviation of a sending interval during the imaging of the existing multi-spectral band TDICMOS detector.

The method for realizing and detecting the rolling line period of the TDICMOS is realized by a dynamic line period imaging system of the TDICMOS with high camera synchronization and fine image motion compensation; a 422 analysis and line period processing module of the imaging system adopts a state machine to realize the control of a RAM of a ping-pong structure and the rolling output line period;

the control selection state machine of the RAM of the ping-pong structure is circularly realized, and the specific process comprises the following steps:

after power-on, firstly entering an idle waiting state S0, and in an S0 state, when detecting that an input start signal RAM2_ renew is high level, entering a state S1 of preparing to select a RAM2 group; when detecting that the input start signal RAM2_ renew is low and the start signal RAM3_ renew is high, entering a ready-to-select RAM3 group state s 2; in the s1 state, when it is detected that the execution time of RAM2 meets the requirement that the identification signal RAM2_ use _ mark is high level, the state s3 of starting to read out the line period parameters from the RAM2 group is entered; in the s3 state, after setting the state flag signal ram2_ use, which ram2 has started executing, to high level, return to s 0; in the s2 state, when it is detected that the execution time of RAM3 meets the requirement that the identification signal RAM3_ use _ mark is high level, the state s4 of starting to read out the line period parameters from the RAM3 group is entered; in the s4 state, after setting the state flag signal ram3_ use that ram3 has started executing to high level, return to the s0 state;

the cycle process of the execution state machine of the rolling output line period is as follows:

after power-on, firstly, the state of the standby Sa0 without operation is entered, and in the Sa0 state, when the current selection execution RAM2 is detected and the execution time stored in the RAM2 is equal to the local time, the state of the RAM2 is entered and the execution state Sa1 is started; when the current execution selection RAM3 is detected and the execution time stored in the RAM3 is equal to the local time, the method enters a RAM3 execution starting state Sa3, reads out the line period data in the RAM2 in an Sa1 state, sends the read-out line period data as new line period data to a time sequence driving module, generates a new driving time sequence, and then enters a RAM2 execution time counting state s2 a; in the sa3 state, reading out the row period data in the RAM3, sending the read-out row period data as new row period data to the timing sequence driving module, generating a new driving timing sequence, and then entering a RAM3 execution times counting state sa 4; in the sa2 state, the execution frequency is increased by 1, then the RAM2 is entered to execute the complete judgment state sa0_ RAM2, in the sa4 state, the execution frequency is increased by 1, then the RAM3 is entered to execute the complete judgment state sa0_ RAM3, in the sa0_ RAM2 state, if the RAM2 is executed in 1s, the state sa0 is entered; if the execution times are not finished, entering a sa1 state; in the sa0_ RAM3 state, if the RAM3 is executed within 1s, the state sa0 is entered; if the execution times are not finished, the state of sa3 is entered.

The invention has the beneficial effects that:

1. in the detection method, the rolling timing position is not compared with the local time by adopting the calculated execution sub-time, but is executed by adopting a counter timing mode of a local clock, so that the interruption of a continuous execution process within one second caused by updating of an externally input time code is avoided. In order to realize relatively accurate time delay, the time occupied by the circulation of the state machine is deducted during counting;

2. the detection method of the invention only judges whether the execution time is the same as the local time under the idle state machine on the circular design of the state machine, and if the execution time is the same as the local time, the idle state machine is not entered into the circular sub-state machine; entering an idle state machine only after the continuous operation within one second is finished; therefore, the continuous operation within one second can be further ensured not to be interrupted, and the problem of conflict between two groups in a ping-pong mode is not specially carried out

3. In the detection method of the invention, the last line period parameter enters the idle state machine after starting to output, and then starts to judge whether a new execution parameter is received, so that the input execution time can be tolerated since the input execution time has deviation.

4. In the detection method, the microsecond counter for judging whether the pulse per second is effective can be cleared only when the falling edge of the pulse per second is detected or the count value reaches 2999999; the flag for judging whether the pulse per second is valid is to judge whether the count value of the microsecond counter is 2999999, and the pulse per second is judged to be invalid as long as the count value is equal to the count value; and the pulse of seconds can be set active only after detecting the falling edge (low for 900us consecutively) on which the pulse of seconds is active. The time code valid flag is that the time code can be received; the time code is invalid as an indication that the time code has not been received for 3 consecutive seconds.

5. In the detection method, the final processing mode is that the targeted processing is carried out according to different state combinations of the second pulse and the effective mark signal of the time code, the microsecond counter reaches 999999 to clear, and simultaneously the second counter is added with 1. When both the second pulse and the second count value are invalid, the cumulative error cannot be eliminated, but the relative count value of 1000100 is obtained, and the time keeping accuracy is higher.

Drawings

FIG. 1 is a functional block diagram of a rolling line periodic imaging system;

FIG. 2 is a cycle diagram of a control selection state machine for a ping-pong architecture RAM;

fig. 3 is a cycle diagram of an execution state machine that scrolls output rows.

Detailed Description

The implementation and detection method of the rolling line period of the TDICMOS according to the embodiment is described with reference to fig. 1 to 3, and the method is implemented by a dynamic line period imaging system of the TDICMOS with high camera synchronization and fine image motion compensation; as shown in fig. 1, the imaging controller outputs a main secondary line periodic signal, a backup line periodic signal, a main secondary pulse, a backup secondary pulse, a 422 serial communication bus, and a main and backup identification signal to the high-resolution multispectral camera imaging unit. An imaging FPGA in an imaging unit of the high-resolution multispectral camera comprises a local time keeping module, a 422 analysis and line period processing module, a time sequence driving module and a data training and fusion module;

the local time keeping module carries out time keeping operation according to the input main and standby identification signals, the main minute second pulse, the backup second pulse and the 422 serial communication bus, and outputs a local timing second value and a local timing microsecond value to the 422 analysis and line period processing module. The 422 analysis and row period processing module compares local time represented by a local timing second value and a local timing microsecond value with execution time sent by a 422 bus according to the received master and slave identification signals, and selects and uses a master slave row period signal or a slave row period signal to generate a panchromatic row starting pulse, a multispectral row starting pulse, panchromatic row period length data and multispectral row period length data required by the time sequence driving module. The transfer and control level signal output by the time sequence driving module is converted into a transfer and control driving signal through an external driving and level conversion circuit and then is sent to the detector for normal work. The output working time sequence of the detector is generated in the time sequence driving module, and the working time sequence mainly depends on the full-color and multi-spectrum row starting pulse and the corresponding row period length data which are input from the 422 analysis and row period module. The serial image data output from the detector is output to the 2711 module through the data training and integrating module, and finally output through the data transmission interface.

The control selection state machine cycle of the RAM with the ping-pong structure is shown in fig. 2, and the control of the state machine is mainly performed in the 422 analysis and row period processing module in fig. 1. Power up first enters the s0 (idle waiting) state. In the S0 state, when RAM2_ renew is detected to be high, the routine proceeds to S1 (preparation for selecting RAM2 group); when RAM2_ renew is detected to be low and RAM3_ renew is detected to be high, s2 is entered (ready to select RAM3 set). In the s1 state, when RAM2_ use _ mark is detected as high, s3 is entered (RAM2 group selected). In the s3 state, ram2_ use is set high, and then s0 is returned. In the s2 state, when RAM3_ use _ mark is detected as high, s4 is entered (RAM3 group selected). In the s3 state, ram3_ use is set high, and then s0 is returned. The input start signals ram2_ renew and ram3_ renew are mutually exclusive, and only one is high; in addition, the high levels of the two alternate.

The execution state machine loop for the rolling output line period is shown in fig. 3, and the state machine is mainly controlled by the 422 analysis and line period processing module in fig. 1. Power-up first enters the s0 (standby with no operation) state. In the S0 state, when it is detected that the RAM2 is currently selected for execution and the execution time stored in the RAM2 is equal to the local time, the process proceeds to S1 (the RAM2 starts execution); when it is detected that the execution of the RAM3 is currently selected and the execution time stored in the RAM3 is equal to the local time, the flow proceeds to S3 (the RAM3 starts execution). In the s1 state, row cycle data in the RAM2 is read out and executed, and then s2(RAM2 execution count) is entered. In the s3 state, row cycle data in the RAM3 is read out and executed, and then s4(RAM3 execution count) is entered. In the s2 state, the number of executions is increased by 1, and then s0_ RAM2 is entered (determination of whether RAM2 execution is complete). In the s4 state, the number of executions is increased by 1, and then s0_ RAM3 is entered (determination of whether RAM3 execution is complete). In the s0_ ram2 state, if ram2 is done in 1s, then proceed to s 0; if the number of executions is not completed, s1 is entered. In the s0_ ram3 state, if ram3 is done in 1s, then proceed to s 0; if the number of executions is not completed, s3 is entered.

In the embodiment, the rolling timing position is not compared with the local time by adopting the calculated execution sub-time, but is executed by adopting a counter timing mode of a local clock, so that the interruption of a continuous execution process within one second caused by updating of an externally input time code is avoided. In order to realize relatively accurate time delay, the time occupied by the circulation of the state machine is deducted during counting;

in the embodiment, on the circular design of the state machine, only the idle state machine is used for judging whether the execution time is the same as the local time, and if the execution time is the same as the local time, the idle state machine is not entered into the circular sub-state machine; entering an idle state machine only after the continuous operation within one second is finished; therefore, the continuous operation within one second can be further ensured not to be interrupted, and the problem of conflict between two groups in a ping-pong mode is not specially carried out;

in this embodiment, the idle state machine is entered after the last line period parameter starts to be outputted, and then it is determined whether a new execution parameter is received.

In this embodiment, the criterion for pulse per second loss is that no pulse per second can be detected for 3 consecutive seconds; if the pulse per second is lost, 1000100 is counted each time, the second value is added by 1, so that the timing deviation is larger, the accumulated deviation is eliminated by a time code sent by 422, the local time keeping precision is poorer, is not 20us, and is possibly 120us at most; there is also a cumulative effect if the 422 time code is wrong or cannot be transmitted.

In this embodiment, the microsecond counter for judging whether the pulse per second is valid can be cleared only when the falling edge of the pulse per second is detected or the count value reaches 2999999; the flag for judging whether the pulse per second is valid is to judge whether the count value of the microsecond counter is 2999999, and the pulse per second is judged to be invalid as long as the count value is equal to the count value; the microsecond counter can be cleared only after the falling edge of the second pulse (continuous 900us is low level) is detected; and (4) judging that the microsecond count value at the moment is in an allowable range (999999 +/-100) before zero clearing, and considering that the second pulse is effective, otherwise, the second pulse is invalid.

The time code valid flag is that the time code can be received; the time code is invalid as an indication that the time code has not been received for 3 consecutive seconds.

The local time counting processing mode is that the specific processing is carried out according to different state combinations of the second pulse and the effective mark signal of the time code, the microsecond counter reaches 999999 to clear, and simultaneously the second counter is added with 1. When both the second pulse and the second count value are invalid, the cumulative error cannot be eliminated, but the relative count value of 1000100 is obtained, and the time keeping accuracy is higher.

(1) When the pulse per second is effective and the time code is effective, the microsecond counter is cleared by the pulse per second (when the count reaches 900, whether the other microsecond counter is 0 or not is judged, so that whether burrs exist or not can be judged); the second counter adds 1 after detecting the rising edge of the second pulse, and replaces the value of the second counter after receiving the time code parameter;

(2) when the pulse per second is effective and the time code is invalid, the microsecond counter is cleared by the pulse per second; the second counter is cleared after detecting the rising edge of the second pulse;

(3) when the pulse per second is invalid and the time code is valid, the microsecond counter is cleared by the fact that the count value of the microsecond counter reaches 99999999; adding 1 to the second counter after detecting that the count value of the microsecond counter reaches 999999, and replacing the value of the second counter after receiving the time code parameter;

(4) when the pulse per second is invalid and the time code is invalid, the microsecond counter is cleared by the fact that the count value of the microsecond counter reaches 999999; the second counter increments by 1 upon detecting that the microsecond counter reaches 99999999.

In this embodiment, there are two methods for detecting the correctness of the rolling line cycle:

the first method belongs to real-time judgment in the judgment process: and testing the line period length of the driving signal and the trigger pulse which is started to be executed by the new line period by using an oscilloscope. One pulse is triggered at the reception of a rolling line period, one pulse at a time. And judging whether the length of the line period in the execution stage is correct or not and whether the length of the interval executed in the new line period is correct or not (corresponding to whether the number of the line period lengths executed in 1s and the number of the trigger pulses are correct or not) by using an oscilloscope.

The second method belongs to post judgment after the execution process: storing data output by the data transmission interface, extracting auxiliary data, and judging whether the line cycle length of an execution time period in the auxiliary data is consistent with an expected value or not and whether the execution starting time of a new line cycle length is consistent with an expected time or not;

in this embodiment, in the rolling line period mode, the minimum line period to the maximum line period need to be traversed, the line period values are tested one by one, the duration time of each line period value is 6s, the image in the whole process is stored by quick look, and the image is subsequently interpreted by a playback mode. The light source used in the test is an integrating sphere, and whether abnormal mutation exists in the gray value of each line of image is counted in a line unit by means of quickly looking at the image to be interpreted.

In the embodiment, the detector adopts a TDICMOS detector of a long-light-core company; the 2711 module adopts a TLK2711 chip; the driving and level conversion circuit is mainly based on a level conversion chip ISL 7457; the imaging controller mainly adopts an FPGA and a refreshing chip of Shanghai Compound denier microelectronics company; the imaging FPGA uses XilInx XQ5VFX 100T.

Claims

The method for realizing and detecting the rolling line period of the TDICMOS is realized by a dynamic line period imaging system of the TDICMOS with high camera synchronization and fine image motion compensation; the method is characterized in that: a 422 analysis and line period processing module of the imaging system adopts a state machine to realize the control of a RAM of a ping-pong structure and the rolling output line period;

the control selection state machine of the RAM of the ping-pong structure is circularly realized, and the specific process comprises the following steps:

after power-on, firstly entering an idle waiting state S0, and in an S0 state, when detecting that an input start signal RAM2_ renew is high level, entering a state S1 of preparing to select a RAM2 group; when detecting that the input start signal RAM2_ renew is low and the start signal RAM3_ renew is high, entering a ready-to-select RAM3 group state s 2; in the s1 state, when it is detected that the execution time of RAM2 meets the requirement that the identification signal RAM2_ use _ mark is high level, the state s3 of starting to read out the line period parameters from the RAM2 group is entered; in the s3 state, after setting the state flag signal ram2_ use, which ram2 has started executing, to high level, return to s 0; in the s2 state, when it is detected that the execution time of RAM3 meets the requirement that the identification signal RAM3_ use _ mark is high level, the state s4 of starting to read out the line period parameters from the RAM3 group is entered; in the s4 state, after setting the state flag signal ram3_ use that ram3 has started executing to high level, return to the s0 state; the input start signals ram2_ renew and ram3_ renew are mutually exclusive, and only one of the input start signals ram2_ renew and ram3_ renew is high at the same time; in addition, the high levels of the two are alternately appeared;

the cycle process of the execution state machine of the rolling output line period is as follows:

after power-on, firstly, the state of the standby Sa0 without operation is entered, and in the Sa0 state, when the current selection execution RAM2 is detected and the execution time stored in the RAM2 is equal to the local time, the state of the RAM2 is entered and the execution state Sa1 is started; when the current execution selection of the RAM3 is detected and the execution time stored in the RAM3 is equal to the local time, the method enters a RAM3 execution starting state Sa3, reads out line cycle data in the RAM2 and executes new line cycle data in an Sa1 state, and then enters a RAM2 execution number counting state s2 a; in the sa3 state, the row cycle data in the RAM3 is read out and new row cycle data is executed, and then the RAM3 execution number count state sa4 is entered; in the sa2 state, the execution frequency is increased by 1, then the RAM2 is entered to execute the complete judgment state sa0_ RAM2, in the sa4 state, the execution frequency is increased by 1, then the RAM3 is entered to execute the complete judgment state sa0_ RAM3, in the sa0_ RAM2 state, if the RAM2 is executed in 1s, the state sa0 is entered; if the execution times are not finished, entering a sa1 state; in the sa0_ RAM3 state, if the RAM3 is executed within 1s, the state sa0 is entered; if the execution times are not finished, the state of sa3 is entered.
2. The method for implementing and detecting a rolling line period of a TDICMOS according to claim 1, wherein: the input start signals ram2_ renew and ram3_ renew are mutually exclusive, and only one of the input start signals ram2_ renew and ram3_ renew is high at the same time; the high levels of the two are alternately present.
3. The method for implementing and detecting a rolling line period of a TDICMOS according to claim 1, wherein: on the aspect of the cycle design of the state machine, judging whether the execution time is the same as the local time only under the idle state machine, and if the execution time is the same as the local time, entering the circulating sub-state machine, but not entering the idle state machine; the idle state machine is entered only after a one second continuation has been performed.
4. The method for implementing and detecting a rolling line period of a TDICMOS according to claim 1, wherein: judging whether the main second pulse and the backup second pulse are effective or not based on the counting value of the microsecond counter; the microsecond counter can be cleared only when the falling edge of the second pulse is detected or the count value reaches 2999999; when the counting value of the microsecond counter reaches 2999999, the second pulse is judged to be invalid, otherwise, the second pulse is invalid.
5. The method for implementing and detecting a rolling line period of a TDICMOS according to claim 1, wherein: the time code valid flag is the time code received by the local time keeping module; the time code is invalid as a time code is not received for 3 consecutive seconds.
6. The method for implementing and detecting a rolling line period of a TDICMOS according to claim 1, wherein: the local timing processing mode is to process according to different state combinations of the second pulse and the effective mark signal of the time code:

(1) when the second pulse is effective and the time code is effective, the microsecond counter is a second counter which is cleared by the second pulse, 1 is added after the rising edge of the second pulse is detected, and the value of the second counter is replaced after the time code parameter is received;

(2) when the pulse per second is effective and the time code is invalid, the microsecond counter is reset by the pulse per second; the second counter is cleared after detecting the rising edge of the second pulse;

(3) when the pulse per second is invalid and the time code is valid, the microsecond counter is cleared by the fact that the count value of the microsecond counter reaches 999999; adding 1 to the second counter after detecting that the count value of the microsecond counter reaches 999999, and replacing the value of the second counter after receiving the time code parameter;

(4) when the pulse per second is invalid and the time code is invalid, resetting the microsecond counter when the count value of the microsecond counter reaches 99999999; the second counter increments by 1 upon detecting that the microsecond counter reaches 99999999.
7. The method for implementing and detecting a rolling line period of a TDICMOS according to claim 1, wherein: in the rolling row period mode, traversing from the minimum row period to the maximum row period, testing row period values one by one, wherein the duration time of each row period value is 6s, storing images in the whole process by adopting image acquisition ground detection equipment connected with a data transmission interface, and subsequently judging by adopting a playback mode; the light source used in the test is an integrating sphere, and the image acquisition ground inspection equipment judges the image mode and counts whether the gray value of each line of image has abnormal mutation or not in a row unit.
8. The method for implementing and detecting a rolling line period of a TDICMOS according to claim 1, wherein: in the dynamic line period imaging system of the TDICMOS with high camera shooting synchronism and fine image motion compensation, an imaging controller outputs a main share line period signal, a backup line period signal, a main share second pulse, a backup second pulse, a 422 serial communication bus and a main and backup identification signal to a high-resolution multispectral camera imaging unit; an imaging FPGA in an imaging unit of the high-resolution multispectral camera comprises a local time keeping module, a 422 analysis and line period processing module, a time sequence driving module and a data training and fusion module;

the local time keeping module carries out time keeping operation according to the input main and standby identification signals, the main minute second pulse, the backup second pulse and the 422 serial communication bus, and outputs a local timing second value and a local timing microsecond value to the 422 analysis and line period processing module. The 422 analysis and row period processing module compares local time represented by a local timing second value and a local timing microsecond value with execution time sent by a 422 bus according to the received master and slave identification signals, and selects and uses a master slave row period signal or a slave row period signal to generate a panchromatic row starting pulse, a multispectral row starting pulse, panchromatic row period length data and multispectral row period length data required by the time sequence driving module; the transfer and control level signal output by the time sequence driving module is converted into a transfer and control driving signal through an external driving and level conversion circuit and then is sent to the detector for normal work; the output working time sequence of the detector is generated in the time sequence driving module, and during working, the full-color and multi-spectral line starting pulse and corresponding line period length data are input from the 422 analysis and line period module; the serial image data output from the detector is output to the 2711 module through the data training and integrating module, and finally output through the data transmission interface.