CN114094838A - Synchronous rectification control method, circuit, device, equipment and storage medium - Google Patents

Synchronous rectification control method, circuit, device, equipment and storage medium Download PDF

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Publication number
CN114094838A
CN114094838A CN202111358218.0A CN202111358218A CN114094838A CN 114094838 A CN114094838 A CN 114094838A CN 202111358218 A CN202111358218 A CN 202111358218A CN 114094838 A CN114094838 A CN 114094838A
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tube
drain
mos
control
state
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CN114094838B (en
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宇文超敏
宋泽琳
颜权枫
雷龙
翟志伟
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Gree Electric Appliances Inc of Zhuhai
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Gree Electric Appliances Inc of Zhuhai
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33569—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements
    • H02M3/33576—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer
    • H02M3/33592—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only having several active switching elements having at least one active switching element at the secondary side of an isolation transformer having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
    • H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
    • H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M7/219—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only in a bridge configuration
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)
  • Rectifiers (AREA)

Abstract

The embodiment of the invention relates to a synchronous rectification control method, a circuit, a device, equipment and a storage medium, wherein the synchronous rectification control method comprises the following steps: acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in a target synchronous rectifier circuit; determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage; determining control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state; and controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit. Therefore, the synchronous rectification control can be realized by using simple circuits and algorithm logics, the direct short circuit is prevented, the control effect is good, and the real-time performance is strong.

Description

Synchronous rectification control method, circuit, device, equipment and storage medium
Technical Field
The embodiment of the invention relates to the technical field of synchronous rectification, in particular to a synchronous rectification control method, a circuit, a device, equipment and a storage medium.
Background
In the application of low-voltage and large-current output, the LLC resonant converter is widely used because of its soft switching characteristic. Through reasonable design, a primary side switching tube of a transformer of the LLC converter can realize ZVS (zero voltage switching) switching-on, and a secondary side rectifier diode can realize ZCS (zero current switching) switching-off, so that loss can be effectively reduced, and efficiency is improved; on the basis, the loss of the secondary rectifier of the transformer becomes the main loss of the LLC converter, and the improvement of the LLC converter efficiency is greatly limited; in order to solve the problem of large loss of the rectifier, the synchronous rectification technology is mostly adopted at present.
In the prior art, a synchronous rectification control method is mainly divided into a hardware control scheme and a software control scheme. The hardware control scheme generally includes two kinds, one is to use a driver IC, and one is a conventional self-driving circuit. The control scheme using the driving IC is limited by the specification of the driving chip, the adjustment is limited, and the control effect is limited. The traditional self-driving circuit connects the drain electrode of a secondary side rectifier tube to the grid electrode of another rectifier tube, takes VDS as a driving signal of another path, has too simple structure, does not contain any protection logic circuit and has lower reliability; or, the voltage bias circuit is used as a driving signal source of the rectifier tube, which has the problems of complicated circuit logic, more related devices and high cost.
The software control scheme mainly comprises a current mode control scheme based on detecting the current of the rectifier tube and a voltage mode control scheme based on detecting the voltage Vds of the rectifier tube. The current type control scheme can realize better control effect, but when the current flowing through the rectifier tube is larger, the sensor required for detecting the current is large in size and high in cost; the voltage type control scheme has the problems of complex control logic, poor real-time performance and the like.
Disclosure of Invention
In view of this, in order to solve the technical problems of the complicated synchronous rectification circuit and the complicated control logic, embodiments of the present invention provide a synchronous rectification control method, circuit, apparatus, device, and storage medium.
In a first aspect, an embodiment of the present invention provides a synchronous rectification control method, including:
acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in a target synchronous rectifier circuit;
determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage;
determining control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state;
and controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit.
In one possible embodiment, the determining the control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state includes:
in the first state is on and the second state is on; or, when the first state is off and the second state is off, the control strategy is a first control strategy;
when the first state is on and the second state is off, the control strategy is a second control strategy;
the control strategy is a third control strategy when the first state is off and the second state is on.
In one possible embodiment, the controlling the first MOS transistor and the second MOS transistor based on the control strategy includes:
controlling the first MOS tube to be switched off and controlling the second MOS tube to be switched off based on the first control strategy;
or the like, or, alternatively,
controlling the first MOS tube to be conducted and controlling the second MOS tube to be switched off based on the second control strategy;
or the like, or, alternatively,
and controlling the first MOS tube to be switched off and controlling the second MOS tube to be switched on based on the third control strategy.
In a possible implementation manner, the determining, according to the first drain-source voltage, a first state corresponding to a first rectifier tube corresponding to the first MOS tube includes:
inputting the first drain-source voltage into the inverting terminal of the first comparator, and inputting the reference voltage into the non-inverting terminal of the first comparator;
comparing the first drain-source voltage with the reference voltage to obtain a first comparison result;
when the first comparison result is that the first drain-source voltage is smaller than the reference voltage, the first comparator outputs a high level, and the first state of the first rectifying tube is determined to be on;
when the first comparison result is that the first drain-source voltage is not less than the reference voltage, the first comparator outputs a low level, and the first state of the first rectifying tube is determined to be off.
In a possible implementation manner, the determining, according to the second drain-source voltage, a second state corresponding to a second rectifier tube corresponding to the second MOS tube includes:
inputting the second drain-source voltage into the inverting terminal of a second comparator, and inputting the reference voltage into the non-inverting terminal of the second comparator;
comparing the second drain-source voltage with the reference voltage to obtain a second comparison result;
when the second comparison result is that the second drain-source voltage is smaller than the reference voltage, the second comparator outputs a high level, and the second state of the second rectifier tube is determined to be on;
and when the second comparison result shows that the second drain-source voltage is not less than the reference voltage, the second comparator outputs a low level, and the second state of the second rectifying tube is determined to be off.
In one possible embodiment, the method further comprises:
judging whether a synchronous rectification control mode is started, and controlling the synchronous rectification control mode to be started and controlling the first MOS tube and the second MOS tube to be switched off when the synchronous rectification control mode is not started;
and when the synchronous rectification control mode is started, executing the synchronous rectification control method.
In a second aspect, an embodiment of the present invention provides a synchronous rectification control circuit, including:
the device comprises a target synchronous rectification circuit, a resonant circuit and a control module, wherein the target synchronous rectification circuit is a circuit on the secondary side of a transformer, and the resonant circuit is a circuit on the primary side of the transformer;
the synchronous rectification circuit includes: the device comprises a detection module, a first rectifying tube and a second rectifying tube;
the first end of detection module is connected with the first end of first rectifier tube, the second end of detection module with the first end of second rectifier tube is connected, the third end of detection module with the first end of control module is connected, the second end of control unit with the second end of first rectifier tube is connected, the third end of control module with the second end of second rectifier tube is connected, the fourth end of control module with resonant circuit's first end is connected, the fifth end of control module with resonant circuit's second end is connected, the sixth end of control module with resonant circuit's third end is connected, the seventh end of control module with the first end of target synchronous rectifier circuit is connected.
In one possible embodiment, the detection module comprises: the first comparator, the second comparator, the first optical coupler and the second optical coupler; the first rectifier tube comprises a first MOS tube and a first diode, the cathode of the first diode is connected with the drain electrode of the first MOS tube, the anode of the first diode is connected with the source electrode of the first MOS tube, the second rectifier tube comprises a second MOS tube and a second diode, the cathode of the second diode is connected with the drain electrode of the second MOS tube, and the anode of the second diode is connected with the source electrode of the second MOS tube.
The inverting terminal of first comparator with the drain electrode of first MOS pipe is connected, the inverting terminal of second comparator with the drain electrode of second MOS pipe is connected, the in-phase terminal of first comparator with the in-phase terminal of second comparator is connected with reference voltage, the output process of first comparator first opto-coupler with control module's first end is connected, the output process of second comparator the second opto-coupler with control module's first end is connected, control module's second end with the grid of first MOS pipe is connected, control module's third end with the grid of second MOS pipe is connected.
In a third aspect, an embodiment of the present invention provides a synchronous rectification control device, including:
the acquisition module is used for acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in the target synchronous rectifier circuit;
the determining module is used for determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage;
the determining module is configured to determine control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state;
and the control module is used for controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit.
In a fourth aspect, an embodiment of the present invention provides an apparatus, including: a processor and a memory, the processor being configured to execute a synchronous rectification control program stored in the memory to implement the synchronous rectification control method according to any one of the first aspect.
In a fifth aspect, an embodiment of the present invention provides a storage medium, where the storage medium stores one or more programs, and the one or more programs are executable by one or more processors to implement the synchronous rectification control method according to any one of the above first aspects.
According to the synchronous rectification control scheme provided by the embodiment of the invention, a first drain-source voltage of a first MOS tube in a first rectifier tube in a target synchronous rectification circuit and a second drain-source voltage of a second MOS tube in a second rectifier tube are obtained; determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage; determining control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state; and controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit. The synchronous rectification function is effectively realized through a simple hardware circuit and control logic, direct short circuit is prevented, the control effect is good, and the real-time performance is strong.
Drawings
Fig. 1 is a schematic flow chart of a synchronous rectification control method according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of another synchronous rectification control method according to an embodiment of the present invention;
fig. 3 is a schematic flowchart of another synchronous rectification control method according to an embodiment of the present invention;
fig. 4 is a schematic flowchart of another synchronous rectification control method according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a synchronous rectification control circuit according to an embodiment of the present invention;
fig. 6 is a schematic circuit structure diagram of a detection module according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of a synchronous rectification control device according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of an apparatus according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
For the convenience of understanding of the embodiments of the present invention, the following description will be further explained with reference to specific embodiments, which are not to be construed as limiting the embodiments of the present invention.
Fig. 1 is a schematic flow chart of a synchronous rectification control method according to an embodiment of the present invention, and as shown in fig. 1, the method specifically includes:
s11, acquiring a first drain-source voltage of a first MOS tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in the target synchronous rectifier circuit.
The synchronous rectification control method provided by the embodiment of the invention is applied to a synchronous rectification circuit, the synchronous rectification circuit can be a synchronous rectification circuit based on half-bridge LLC resonance, and the synchronous rectification control is carried out by determining a corresponding control mode by acquiring the state of a rectification tube in the synchronous rectification circuit.
In this embodiment, the method is applied to a synchronous rectification circuit based on half-bridge LLC resonance, where the circuit includes a resonance circuit and a synchronous rectification circuit, the resonance circuit on the primary side of the transformer adopts a half-bridge LLC topology, and the synchronous rectification circuit on the secondary side of the transformer adopts a synchronous rectification topology. The resonant circuit adopts a PFM frequency modulation control algorithm of an algorithm unit in the control module, the synchronous rectification circuit adopts a voltage type control algorithm, a sampling unit of the control module samples resonant current and resonant output voltage in real time, related sampling values participate in algorithm calculation, and a PWM unit of the control module outputs a driving signal with adjustable frequency and 50% duty ratio so as to control the first MOS tube and the second MOS tube.
The target synchronous rectification circuit is a synchronous rectification topology, and the target synchronous rectification circuit can comprise: first rectifier tube and second rectifier tube, first rectifier tube includes: first MOS pipe and first diode, include in the second rectifier cell: the first drain-source voltage is the voltage between the drain electrode and the source electrode of the first MOS tube, and the second drain-source voltage is the voltage between the drain electrode and the source electrode of the second MOS tube.
Further, a detection module is preset, and the detection module comprises: the first detection module is used for acquiring voltage between a drain electrode and a source electrode of the first MOS tube as first drain-source electrode voltage; and the second detection module is used for acquiring the voltage between the drain electrode and the source electrode of the second MOS tube as the voltage of the second drain electrode and the source electrode.
S12, determining a first state corresponding to a first rectifier tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifier tube corresponding to the second MOS tube according to the second drain-source voltage.
In this embodiment, the two ends of the first MOS transistor are connected in anti-parallel with the first diode as the first rectifier, that is, the drain of the first MOS transistor is connected to the cathode of the first diode, the source of the first MOS transistor is connected to the anode of the first diode, the two ends of the second MOS transistor are connected in anti-parallel with the second diode as the second rectifier, that is, the drain of the second MOS transistor is connected to the cathode of the second diode, and the source of the second MOS transistor is connected to the anode of the second diode. The first state is used for indicating the current corresponding working state of the first rectifying tube, the second state is used for indicating the current corresponding working state of the second rectifying tube, and the working state can comprise on and off.
Furthermore, a preset rule is preset in the detection module and is used for determining the working state of the rectifier tube through drain-source voltage, determining the first state according to the first drain-source voltage through the preset rule, and determining the second state according to the second drain-source voltage through the preset rule.
S13, determining the control strategies of the first MOS tube and the second MOS tube according to the first state and the second state.
In this embodiment, a control algorithm is preset in an algorithm unit of the control module in advance, and is used for determining a corresponding control strategy according to the first state and the second state, and the control module may be an MCU.
Specifically, a first state and a second state sent by a detection module are obtained in real time through a universal I/O pin in a control module, an algorithm unit detects the first state and the second state input by the universal I/O pin in real time, and the algorithm unit determines a corresponding control strategy according to a control algorithm.
And S14, controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit.
In this embodiment, a PWM unit in the control module is controlled to send out a corresponding first driving signal and a second driving signal according to a control strategy, where the first driving signal is used to control a first MOS transistor, and the second driving signal is used to control a second MOS transistor, so as to control a target synchronous rectification circuit by controlling the on/off of the first MOS transistor and the second MOS transistor.
Fig. 2 is a schematic flow chart of another synchronous rectification control method according to an embodiment of the present invention, and as shown in fig. 2, the method specifically includes:
and S21, judging whether the synchronous rectification control mode is started or not.
In this embodiment, the synchronous rectification mode is used to indicate a mode capable of performing synchronous rectification control, and a judgment program preset in an algorithm unit of the control module is used to judge whether the synchronous rectification function is enabled, where the judgment program is used to indicate that the synchronous rectification control mode is turned on when enabled, and is used to indicate that the synchronous rectification control mode is not turned on when not enabled, and the synchronous rectification function is not enabled in an initial state.
And S22, when the judgment result is that the synchronous rectification control mode is started, acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectification tube and a second drain-source voltage of a second MOS tube in a second rectification tube in the target synchronous rectification circuit.
In this embodiment, when the synchronous rectification control mode is turned on as a result of the determination, the details are described in S11, which is not described herein, in the same manner as the step S11.
In an alternative of this embodiment, when the determination result is that the synchronous rectification control mode is not turned on, the synchronous rectification control mode is controlled to be turned on, that is, a synchronous rectification function is set to be enabled, and the first MOS transistor and the second MOS transistor are turned off.
Specifically, the algorithm module generates a control instruction to control the enabling of the synchronous rectification function and control the turning off of the driving signals of the first MOS tube and the second MOS tube.
S23, inputting the first drain-source voltage into the inverting terminal of the first comparator, and inputting the reference voltage into the non-inverting terminal of the first comparator; and inputting the second drain-source voltage into the inverting terminal of the second comparator, and inputting the reference voltage into the non-inverting terminal of the second comparator.
In this embodiment, the synchronous rectification circuit includes a detection module, which can obtain a first drain-source voltage and a second drain-source voltage, and the detection module is composed of a first comparator, a second comparator, a first optical coupler and a second optical coupler. The reference voltage is generated by a voltage division circuit by taking the ground of the secondary side of the transformer as a reference ground, the reference voltage value is a negative voltage value, and the reference voltage value is a preset small voltage value. The inverting end of the first comparator is connected with the drain electrode of the first MOS tube and used for obtaining a first drain-source voltage, the inverting end of the second comparator is connected with the drain electrode of the second MOS tube and used for obtaining a second drain-source voltage, and the inverting end of the first comparator and the inverting end of the second comparator are connected with a reference voltage.
S24, determining a first state corresponding to a first rectifier tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifier tube corresponding to the second MOS tube according to the second drain-source voltage.
In this embodiment, the diode connected in anti-parallel at two ends of the MOS transistor is used as the rectifying transistor, that is, the drain of the MOS transistor is connected to the cathode of the diode, and the source of the MOS transistor is connected to the anode of the diode. The synchronous rectification is full-wave rectification, when the same-name end of the transformer is high potential, the diode is firstly conducted at the moment, and then the drain-source voltage of the synchronous rectification tube is the conduction voltage drop (negative voltage value) of the diode.
Comparing the first drain-source voltage with the reference voltage through a first comparator to obtain a first comparison result; when the first comparison result is that the first drain-source voltage is smaller than the reference voltage, the first comparator outputs a high level at the moment, the high level is sent to a general I/O pin of the control module through a first optical coupler, an algorithm unit of the control module detects the high level input by the general I/O pin in real time, and the algorithm unit determines that a first state corresponding to the first rectifier tube at present is on according to a preset algorithm; and when the first comparison result shows that the first drain-source voltage is not less than the reference voltage, the first comparator outputs a low level, and the current corresponding state of the first rectifying tube is determined to be off.
And comparing the second drain-source voltage with the reference voltage through a second comparator to obtain a second comparison result. When the second comparison result is that the voltage of the second drain-source electrode is smaller than the reference voltage, the second comparator outputs a high level at the moment, the high level is sent to a general I/O pin of the control module through a second optical coupler, an algorithm unit of the control module detects the high level input by the general I/O pin in real time, and the algorithm unit determines that the second state corresponding to the second rectifier tube at present is on according to a preset algorithm; and when the second comparison result is that the voltage of the second drain-source electrode is not less than the reference voltage, the second comparator outputs a low level, and the second state corresponding to the second rectifier tube is determined to be off.
S25, being on in the first state and on in the second state; or, when the first state is off and the second state is off, the control strategy is a first control strategy; and controlling the first MOS tube to be switched off and controlling the second MOS tube to be switched off based on the first control strategy.
In this embodiment, a control algorithm is preset in an algorithm unit of the control module in advance, and is used for determining a corresponding control strategy according to the first state and the second state. When the control strategy is a first control strategy, the PWM unit in the control module is controlled to send out a corresponding first driving signal and a second driving signal according to the first control strategy, the first driving signal is used for controlling the first MOS tube to be switched off, the second driving signal is used for controlling the second MOS tube to be switched off, and the target synchronous rectification circuit is controlled by controlling the first MOS tube and the second MOS tube to be switched off.
Fig. 3 is a schematic flow chart of another synchronous rectification control method according to an embodiment of the present invention, and as shown in fig. 3, the method specifically includes:
s31, acquiring a first drain-source voltage of a first MOS tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in the target synchronous rectifier circuit.
In the present embodiment, the details are described in S11, which is not described here, as in the above step S11.
S32, inputting the first drain-source voltage into the inverting terminal of the first comparator, and inputting the reference voltage into the non-inverting terminal of the first comparator; and inputting the second drain-source voltage into the inverting terminal of the second comparator, and inputting the reference voltage into the non-inverting terminal of the second comparator.
In the present embodiment, the details are described in S23, which is not described here, as in the above step S23.
S33, determining that a first state corresponding to the first rectifying tube corresponding to the first MOS tube is on according to the first drain-source voltage, and determining that a second state corresponding to the second rectifying tube corresponding to the second MOS tube is off according to the second drain-source voltage.
In this embodiment, the diode connected in anti-parallel at two ends of the MOS transistor is used as the rectifying transistor, that is, the drain of the MOS transistor is connected to the cathode of the diode, and the source of the MOS transistor is connected to the anode of the diode. Comparing the first drain-source voltage with the reference voltage through a first comparator to obtain a first comparison result; when the first comparison result is that the first drain-source voltage is smaller than the reference voltage, the first comparator outputs a high level at the moment, the high level is sent to a general I/O pin of the control module through a first optical coupler, an algorithm unit of the control module detects the high level input by the general I/O pin in real time, and the algorithm unit determines that a first state corresponding to the first rectifier tube at present is on according to a preset algorithm.
And comparing the second drain-source voltage with the reference voltage through a second comparator to obtain a second comparison result. And when the second comparison result is that the voltage of the second drain-source electrode is not less than the reference voltage, the second comparator outputs a low level, the low level is sent to a general I/O pin of the control module through a second optical coupler, an algorithm unit of the control module detects the low level input by the general I/O pin in real time, and the algorithm unit determines that the second state corresponding to the second rectifier tube at present is off according to a preset algorithm.
S34, when the first state is on and the second state is off, the control strategy is a second control strategy; and controlling the first MOS tube to be conducted and controlling the second MOS tube to be switched off based on the second control strategy.
In this embodiment, a control algorithm is preset in an algorithm unit of the control module in advance, and is used for determining a corresponding control strategy according to the first state and the second state. And when the control strategy is a second control strategy, controlling a PWM unit in the control module to send out a corresponding first driving signal and a second driving signal according to the second control strategy, wherein the first driving signal is used for controlling the conduction of a first MOS (metal oxide semiconductor) tube, and the second driving signal is used for controlling the disconnection of a second MOS tube, so that the control of the target synchronous rectification circuit is realized by controlling the disconnection of the first MOS tube and the second MOS tube.
Fig. 4 is a schematic flowchart of another synchronous rectification control method according to an embodiment of the present invention, and as shown in fig. 4, the method specifically includes:
s41, acquiring a first drain-source voltage of a first MOS tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in the target synchronous rectifier circuit.
In the present embodiment, the details are described in S11, which is not described here, as in the above step S11.
S42, inputting the first drain-source voltage into the inverting terminal of the first comparator, and inputting the reference voltage into the non-inverting terminal of the first comparator; and inputting the second drain-source voltage into the inverting terminal of the second comparator, and inputting the reference voltage into the non-inverting terminal of the second comparator.
In the present embodiment, the details are described in S23, which is not described here, as in the above step S23.
S43, determining that a first state corresponding to the first rectifying tube corresponding to the first MOS tube is off according to the first drain-source voltage, and determining that a second state corresponding to the second rectifying tube corresponding to the second MOS tube is on according to the second drain-source voltage.
In this embodiment, the diode connected in anti-parallel at two ends of the MOS transistor is used as the rectifying transistor, that is, the drain of the MOS transistor is connected to the cathode of the diode, and the source of the MOS transistor is connected to the anode of the diode. Comparing the first drain-source voltage with the reference voltage through a first comparator to obtain a first comparison result; when the first comparison result shows that the first drain-source voltage is not smaller than the reference voltage, the first comparator outputs a low level, the low level is sent to a general I/O pin of the control module through a first optical coupler, an algorithm unit of the control module detects the low level input by the general I/O pin in real time, and the algorithm unit determines that the first state corresponding to the first rectifier tube at present is off according to a preset algorithm.
And comparing the second drain-source voltage with the reference voltage through a second comparator to obtain a second comparison result. And when the second comparison result is that the voltage of the second drain-source electrode is smaller than the reference voltage, the second comparator outputs a high level at the moment, the high level is sent to a general I/O pin of the control module through a second optical coupler, an algorithm unit of the control module detects the high level input by the general I/O pin in real time, and the algorithm unit determines that the second state corresponding to the second rectifier tube at present is on according to a preset algorithm.
S44, when the first state is off and the second state is on, the control strategy is a third control strategy; and controlling the first MOS tube to be switched off and controlling the second MOS tube to be switched on based on the third control strategy.
In this embodiment, a control algorithm is preset in an algorithm unit of the control module in advance, and is used for determining a corresponding control strategy according to the first state and the second state. And when the control strategy is a third control strategy, controlling a PWM unit in the control module to send out a corresponding first drive signal and a second drive signal according to the third control strategy, wherein the first drive signal is used for controlling the first MOS tube to be switched off, and the second drive signal is used for controlling the second MOS tube to be switched on, so that the target synchronous rectification circuit is controlled by controlling the first MOS tube and the second MOS tube to be switched off.
Fig. 5 is a schematic structural diagram of a synchronous rectification control circuit according to an embodiment of the present invention.
Fig. 6 is a schematic circuit structure diagram of a detection module according to an embodiment of the present invention.
Wherein the reference numerals of fig. 5 are explained as follows:
101: a PWM unit; 102: an arithmetic unit; 103: a protection unit; 104: a sampling unit; 105: a detection module; 106: a load; 107: a control module; VDC: a power source; q1: a first MOS tube of the resonant circuit; q2: a second MOS tube of the resonance circuit; c1: a first capacitor; c2: a second capacitor; c3: a third capacitor; lr: an inductance; t1: a transformer; SR 1: a first MOS tube of the synchronous rectification circuit; SR 2: a second MOS tube of the synchronous rectification circuit; d1: a first diode of the synchronous rectification circuit; d2: a second diode of the synchronous rectification circuit; GND 1: the ground of the primary side of the transformer; GND 2: the secondary side of the transformer is grounded.
The reference numerals of fig. 6 are illustrated as: u1: a first comparator; u2: a second comparator; vds 1: a first drain-source voltage; vds 2: a second drain-source voltage; vref 1: a reference voltage; 1001: a first optical coupler; 1002 a second optocoupler; 107: and a control module.
In this embodiment, the circuit is a synchronous rectification circuit based on half-bridge LLC resonance, and includes: the device comprises a target synchronous rectification circuit, a resonant circuit and a control module, wherein the target synchronous rectification circuit is a circuit on the secondary side of a transformer, and the resonant circuit is a circuit on the primary side of the transformer; the control module can be an MCU;
the synchronous rectification circuit includes: the device comprises a detection module, a first rectifying tube and a second rectifying tube;
the first end of detection module is connected with the first end of first rectifier tube, the second end of detection module with the first end of second rectifier tube is connected, the third end of detection module with the first end of control module is connected, the second end of control unit with the second end of first rectifier tube is connected, the third end of control module with the second end of second rectifier tube is connected, the fourth end of control module with resonant circuit's first end is connected, the fifth end of control module with resonant circuit's second end is connected, the sixth end of control module with resonant circuit's third end is connected, the seventh end of control module with the first end of target synchronous rectifier circuit is connected.
In one possible embodiment, the control module comprises: the device comprises a sampling unit, a protection unit, an algorithm unit and a PWM unit. The detection module comprises: the first comparator, the second comparator, the first optical coupler and the second optical coupler; the first rectifier tube comprises a first MOS tube and a first diode, the cathode of the first diode is connected with the drain electrode of the first MOS tube, the anode of the first diode is connected with the source electrode of the first MOS tube, the second rectifier tube comprises a second MOS tube and a second diode, the cathode of the second diode is connected with the drain electrode of the second MOS tube, and the anode of the second diode is connected with the source electrode of the second MOS tube;
the inverting terminal of first comparator with the drain electrode of first MOS pipe is connected, the inverting terminal of second comparator with the drain electrode of second MOS pipe is connected, the in-phase terminal of first comparator with the in-phase terminal of second comparator is connected with reference voltage, the output process of first comparator first opto-coupler with control module's first end is connected, the output process of second comparator the second opto-coupler with control module's first end is connected, control module's first end can be MCU input mode's general IO mouth. The second end of the control module is connected with the grid electrode of the first MOS tube of the synchronous rectification circuit, the third end of the control module is connected with the grid electrode of the second MOS tube of the synchronous rectification circuit, the fourth end of the control module is connected with the grid electrode of the second MOS tube of the resonant circuit, the fifth end of the control module is connected with the grid electrode of the first MOS tube of the resonant circuit, and the second end, the third end, the fourth end and the fifth end of the control module can be PWM pins.
The circuit provided in this embodiment may be a circuit as shown in fig. 5 and fig. 6, and may perform all the steps of the method shown in fig. 1 to 4, so as to achieve the technical effects of the method shown in fig. 1 to 4, which is described with reference to fig. 1 to 4 for brevity and will not be described herein again.
Fig. 7 is a schematic structural diagram of a synchronous rectification control device according to an embodiment of the present invention.
An obtaining module 71, configured to obtain a first drain-source voltage of a first MOS transistor in a first rectifier tube and a second drain-source voltage of a second MOS transistor in a second rectifier tube in a target synchronous rectification circuit;
a determining module 72, configured to determine, according to the first drain-source voltage, a first state corresponding to a first rectifier tube corresponding to the first MOS transistor, and determine, according to the second drain-source voltage, a second state corresponding to a second rectifier tube corresponding to the second MOS transistor;
the determining module 72 is further configured to determine control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state;
and the control module 73 is configured to control the first MOS transistor and the second MOS transistor based on the control strategy so as to control the target synchronous rectification circuit.
In a possible embodiment, the determining module 72 is specifically configured to turn on in the first state and turn on in the second state; or, when the first state is off and the second state is off, the control strategy is a first control strategy;
when the first state is on and the second state is off, the control strategy is a second control strategy;
the control strategy is a third control strategy when the first state is off and the second state is on.
In a possible embodiment, the control module 73 is specifically configured to control the first MOS transistor to be turned off and control the second MOS transistor to be turned off based on the first control strategy; or, controlling the first MOS tube to be conducted and controlling the second MOS tube to be switched off based on the second control strategy; or, the first MOS tube is controlled to be switched off and the second MOS tube is controlled to be switched on based on the third control strategy.
In a possible implementation manner, the control module 73 is specifically configured to input the first drain-source voltage to an inverting terminal of the first comparator, and input a reference voltage to a non-inverting terminal of the first comparator;
comparing the first drain-source voltage with the reference voltage to obtain a first comparison result;
when the first comparison result is that the first drain-source voltage is smaller than the reference voltage, the first comparator outputs a high level, and the first state of the first rectifying tube is determined to be on;
when the first comparison result is that the first drain-source voltage is not less than the reference voltage, the first comparator outputs a low level, and the first state of the first rectifying tube is determined to be off.
In a possible implementation manner, the control module 73 is specifically configured to input the second drain-source voltage to an inverting terminal of the second comparator, and input a reference voltage to a non-inverting terminal of the second comparator;
comparing the second drain-source voltage with the reference voltage to obtain a second comparison result;
when the second comparison result is that the second drain-source voltage is smaller than the reference voltage, the second comparator outputs a high level, and the second state of the second rectifier tube is determined to be on;
and when the second comparison result shows that the second drain-source voltage is not less than the reference voltage, the second comparator outputs a low level, and the second state of the second rectifying tube is determined to be off.
In a possible embodiment, the control module 73 is specifically configured to determine whether a synchronous rectification control mode is turned on, and when the synchronous rectification control mode is not turned on, control the synchronous rectification control mode to be turned on, and control the first MOS transistor and the second MOS transistor to be turned off;
and when the synchronous rectification control mode is started, executing the synchronous rectification control method.
The apparatus provided in this embodiment may be the apparatus shown in fig. 7, and may perform all the steps of the method shown in fig. 1 to 4, so as to achieve the technical effects of the method shown in fig. 1 to 4, and for brevity, it is not described herein again.
Fig. 8 is a schematic structural diagram of an apparatus according to an embodiment of the present invention, where the apparatus 800 shown in fig. 8 includes: at least one processor 801, memory 802, at least one network interface 804, and other user interfaces 803. The various components in the electronic device 800 are coupled together by a bus system 805. It is understood that the bus system 805 is used to enable communications among the components connected. The bus system 805 includes a power bus, a control bus, and a status signal bus in addition to a data bus. For clarity of illustration, however, the various buses are labeled as bus system 805 in fig. 8.
The user interface 803 may include, among other things, a display, a keyboard, or a pointing device (e.g., a mouse, trackball, touch pad, or touch screen, among others.
It will be appreciated that the memory 802 in embodiments of the invention may be either volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. The non-volatile Memory may be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically Erasable PROM (EEPROM), or a flash Memory. Volatile Memory can be Random Access Memory (RAM), which acts as external cache Memory. By way of illustration and not limitation, many forms of RAM are available, such as Static random access memory (Static RAM, SRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic random access memory (Synchronous DRAM, SDRAM), Double Data Rate Synchronous Dynamic random access memory (ddr Data Rate SDRAM, ddr SDRAM), Enhanced Synchronous SDRAM (ESDRAM), synchlronous SDRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 802 described herein is intended to comprise, without being limited to, these and any other suitable types of memory.
In some embodiments, memory 802 stores elements, executable units or data structures, or a subset thereof, or an expanded set thereof as follows: an operating system 8021 and application programs 8022.
The operating system 8021 includes various system programs, such as a framework layer, a core library layer, a driver layer, and the like, and is used for implementing various basic services and processing hardware-based tasks. The application program 8022 includes various application programs, such as a Media Player (Media Player), a Browser (Browser), and the like, for implementing various application services. A program implementing a method according to an embodiment of the present invention may be included in application program 8022.
In the embodiment of the present invention, the processor 801 is configured to execute the method steps provided by each method embodiment by calling the program or instruction stored in the memory 802, specifically, the program or instruction stored in the application 8022, and for example, includes:
acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in a target synchronous rectifier circuit;
determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage;
determining control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state;
and controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit.
In one possible embodiment, the first state is on and the second state is on; or, when the first state is off and the second state is off, the control strategy is a first control strategy;
when the first state is on and the second state is off, the control strategy is a second control strategy;
the control strategy is a third control strategy when the first state is off and the second state is on.
In one possible embodiment, the first MOS transistor is controlled to be turned off and the second MOS transistor is controlled to be turned off based on the first control strategy; or, controlling the first MOS tube to be conducted and controlling the second MOS tube to be switched off based on the second control strategy; or, the first MOS tube is controlled to be switched off and the second MOS tube is controlled to be switched on based on the third control strategy.
In one possible implementation, the first drain-source voltage is input to an inverting terminal of the first comparator, and the reference voltage is input to a non-inverting terminal of the first comparator;
comparing the first drain-source voltage with the reference voltage to obtain a first comparison result;
when the first comparison result is that the first drain-source voltage is smaller than the reference voltage, the first comparator outputs a high level, and the first state of the first rectifying tube is determined to be on;
when the first comparison result is that the first drain-source voltage is not less than the reference voltage, the first comparator outputs a low level, and the first state of the first rectifying tube is determined to be off.
In one possible implementation, the second drain-source voltage is input to an inverting terminal of the second comparator, and the reference voltage is input to a non-inverting terminal of the second comparator;
comparing the second drain-source voltage with the reference voltage to obtain a second comparison result;
when the second comparison result is that the second drain-source voltage is smaller than the reference voltage, the second comparator outputs a high level, and the second state of the second rectifier tube is determined to be on;
and when the second comparison result shows that the second drain-source voltage is not less than the reference voltage, the second comparator outputs a low level, and the second state of the second rectifying tube is determined to be off.
In a possible implementation manner, whether a synchronous rectification control mode is started or not is judged, and when the synchronous rectification control mode is not started, the synchronous rectification control mode is controlled to be started, and the first MOS transistor and the second MOS transistor are controlled to be turned off;
and when the synchronous rectification control mode is started, executing the synchronous rectification control method.
The methods disclosed in the embodiments of the present invention described above may be implemented in the processor 801 or implemented by the processor 801. The processor 801 may be an integrated circuit chip having signal processing capabilities. In implementation, the steps of the above method may be performed by integrated logic circuits of hardware or instructions in the form of software in the processor 801. The Processor 801 may be a general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other Programmable logic device, discrete Gate or transistor logic device, or discrete hardware components. The various methods, steps and logic blocks disclosed in the embodiments of the present invention may be implemented or performed. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of the method disclosed in connection with the embodiments of the present invention may be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software elements in the decoding processor. The software elements may be located in ram, flash, rom, prom, or eprom, registers, among other storage media that are well known in the art. The storage medium is located in the memory 802, and the processor 801 reads the information in the memory 802, and combines the hardware to complete the steps of the method.
It is to be understood that the embodiments described herein may be implemented in hardware, software, firmware, middleware, microcode, or any combination thereof. For a hardware implementation, the Processing units may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), general purpose processors, controllers, micro-controllers, microprocessors, other electronic units configured to perform the functions described herein, or a combination thereof.
For a software implementation, the techniques described herein may be implemented by means of units performing the functions described herein. The software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.
The device provided in this embodiment may be the device shown in fig. 8, and may perform all the steps of the synchronous rectification control method shown in fig. 1 to 4, so as to achieve the technical effect of the synchronous rectification control method shown in fig. 1 to 4, which is described with reference to fig. 1 to 4 for brevity and will not be described herein again.
The embodiment of the invention also provides a storage medium (computer readable storage medium). The storage medium herein stores one or more programs. Among others, the storage medium may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as read-only memory, flash memory, a hard disk, or a solid state disk; the memory may also comprise a combination of memories of the kind described above.
When one or more programs in the storage medium are executable by one or more processors, the synchronous rectification control method executed on the device side is realized.
The processor is used for executing the synchronous rectification control program stored in the memory so as to realize the following steps of the synchronous rectification control method executed on the equipment side:
acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in a target synchronous rectifier circuit;
determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage;
determining control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state;
and controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit.
In one possible embodiment, the first state is on and the second state is on; or, when the first state is off and the second state is off, the control strategy is a first control strategy;
when the first state is on and the second state is off, the control strategy is a second control strategy;
the control strategy is a third control strategy when the first state is off and the second state is on.
In one possible embodiment, the first MOS transistor is controlled to be turned off and the second MOS transistor is controlled to be turned off based on the first control strategy; or, controlling the first MOS tube to be conducted and controlling the second MOS tube to be switched off based on the second control strategy; or, the first MOS tube is controlled to be switched off and the second MOS tube is controlled to be switched on based on the third control strategy.
In one possible implementation, the first drain-source voltage is input to an inverting terminal of the first comparator, and the reference voltage is input to a non-inverting terminal of the first comparator;
comparing the first drain-source voltage with the reference voltage to obtain a first comparison result;
when the first comparison result is that the first drain-source voltage is smaller than the reference voltage, the first comparator outputs a high level, and the first state of the first rectifying tube is determined to be on;
when the first comparison result is that the first drain-source voltage is not less than the reference voltage, the first comparator outputs a low level, and the first state of the first rectifying tube is determined to be off.
In one possible implementation, the second drain-source voltage is input to an inverting terminal of the second comparator, and the reference voltage is input to a non-inverting terminal of the second comparator;
comparing the second drain-source voltage with the reference voltage to obtain a second comparison result;
when the second comparison result is that the second drain-source voltage is smaller than the reference voltage, the second comparator outputs a high level, and the second state of the second rectifier tube is determined to be on;
and when the second comparison result shows that the second drain-source voltage is not less than the reference voltage, the second comparator outputs a low level, and the second state of the second rectifying tube is determined to be off.
In a possible implementation manner, whether a synchronous rectification control mode is started or not is judged, and when the synchronous rectification control mode is not started, the synchronous rectification control mode is controlled to be started, and the first MOS transistor and the second MOS transistor are controlled to be turned off;
and when the synchronous rectification control mode is started, executing the synchronous rectification control method.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware, a software module executed by a processor, or a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are merely exemplary embodiments of the present invention, and are not intended to limit the scope of the present invention, and any modifications, equivalent substitutions, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.

Claims (11)

1. A synchronous rectification control method, comprising:
acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in a target synchronous rectifier circuit;
determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage, and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage;
determining control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state;
and controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit.
2. The method of claim 1, wherein determining the control strategy for the first MOS transistor and the second MOS transistor according to the first state and the second state comprises:
in the first state is on and the second state is on; or, when the first state is off and the second state is off, the control strategy is a first control strategy;
when the first state is on and the second state is off, the control strategy is a second control strategy;
the control strategy is a third control strategy when the first state is off and the second state is on.
3. The method of claim 2, wherein the controlling the first MOS transistor and the second MOS transistor based on the control strategy comprises:
controlling the first MOS tube to be switched off and controlling the second MOS tube to be switched off based on the first control strategy;
or the like, or, alternatively,
controlling the first MOS tube to be conducted and controlling the second MOS tube to be switched off based on the second control strategy;
or the like, or, alternatively,
and controlling the first MOS tube to be switched off and controlling the second MOS tube to be switched on based on the third control strategy.
4. The method of claim 1, wherein determining the first state corresponding to the first rectifier cell corresponding to the first MOS transistor according to the first drain-source voltage comprises:
inputting the first drain-source voltage into the inverting terminal of the first comparator, and inputting the reference voltage into the non-inverting terminal of the first comparator;
comparing the first drain-source voltage with the reference voltage to obtain a first comparison result;
when the first comparison result is that the first drain-source voltage is smaller than the reference voltage, the first comparator outputs a high level, and the first state of the first rectifying tube is determined to be on;
when the first comparison result is that the first drain-source voltage is not less than the reference voltage, the first comparator outputs a low level, and the first state of the first rectifying tube is determined to be off.
5. The method of claim 1, wherein determining the second state corresponding to the second rectifier cell corresponding to the second MOS transistor according to the second drain-source voltage comprises:
inputting the second drain-source voltage into the inverting terminal of a second comparator, and inputting the reference voltage into the non-inverting terminal of the second comparator;
comparing the second drain-source voltage with the reference voltage to obtain a second comparison result;
when the second comparison result is that the second drain-source voltage is smaller than the reference voltage, the second comparator outputs a high level, and the second state of the second rectifier tube is determined to be on;
and when the second comparison result shows that the second drain-source voltage is not less than the reference voltage, the second comparator outputs a low level, and the second state of the second rectifying tube is determined to be off.
6. The method of claim 1, further comprising:
judging whether a synchronous rectification control mode is started, and controlling the synchronous rectification control mode to be started and controlling the first MOS tube and the second MOS tube to be switched off when the synchronous rectification control mode is not started;
and when the synchronous rectification control mode is started, executing the synchronous rectification control method.
7. A synchronous rectification control circuit, comprising:
the device comprises a target synchronous rectification circuit, a resonant circuit and a control module, wherein the target synchronous rectification circuit is a circuit on the secondary side of a transformer, and the resonant circuit is a circuit on the primary side of the transformer;
the synchronous rectification circuit includes: the device comprises a detection module, a first rectifying tube and a second rectifying tube;
the first end of detection module is connected with the first end of first rectifier tube, the second end of detection module with the first end of second rectifier tube is connected, the third end of detection module with the first end of control module is connected, the second end of control unit with the second end of first rectifier tube is connected, the third end of control module with the second end of second rectifier tube is connected, the fourth end of control module with resonant circuit's first end is connected, the fifth end of control module with resonant circuit's second end is connected, the sixth end of control module with resonant circuit's third end is connected, the seventh end of control module with the first end of target synchronous rectifier circuit is connected.
8. The circuit of claim 7, wherein the detection module comprises: the first comparator, the second comparator, the first optical coupler and the second optical coupler; the first rectifier tube comprises a first MOS tube and a first diode, the cathode of the first diode is connected with the drain electrode of the first MOS tube, the anode of the first diode is connected with the source electrode of the first MOS tube, the second rectifier tube comprises a second MOS tube and a second diode, the cathode of the second diode is connected with the drain electrode of the second MOS tube, and the anode of the second diode is connected with the source electrode of the second MOS tube;
the inverting terminal of first comparator with the drain electrode of first MOS pipe is connected, the inverting terminal of second comparator with the drain electrode of second MOS pipe is connected, the in-phase terminal of first comparator with the in-phase terminal of second comparator is connected with reference voltage, the output process of first comparator first opto-coupler with control module's first end is connected, the output process of second comparator the second opto-coupler with control module's first end is connected, control module's second end with the grid of first MOS pipe is connected, control module's third end with the grid of second MOS pipe is connected.
9. A synchronous rectification control device, comprising:
the acquisition module is used for acquiring a first drain-source voltage of a first MOS (metal oxide semiconductor) tube in a first rectifier tube and a second drain-source voltage of a second MOS tube in a second rectifier tube in the target synchronous rectifier circuit;
the determining module is used for determining a first state corresponding to a first rectifying tube corresponding to the first MOS tube according to the first drain-source voltage and determining a second state corresponding to a second rectifying tube corresponding to the second MOS tube according to the second drain-source voltage;
the determining module is configured to determine control strategies of the first MOS transistor and the second MOS transistor according to the first state and the second state;
and the control module is used for controlling the first MOS tube and the second MOS tube based on the control strategy so as to control the target synchronous rectification circuit.
10. An apparatus, comprising: the synchronous rectification control system comprises a processor and a memory, wherein the processor is used for executing a synchronous rectification control program stored in the memory so as to realize the synchronous rectification control method of any one of claims 1-6.
11. A storage medium storing one or more programs executable by one or more processors to implement the synchronous rectification control method of any one of claims 1 to 6.
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CN109861566A (en) * 2019-03-28 2019-06-07 南京和若源电气有限公司 A kind of circuit of synchronous rectification, synchronous rectification method and wireless charging device
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CN107425728A (en) * 2017-02-28 2017-12-01 东南大学 The digital optimal control method and its system of a kind of LLC full-bridge converters synchronous rectification
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