CN114094436B - Driving device and method for processing driving current - Google Patents
Driving device and method for processing driving current Download PDFInfo
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- CN114094436B CN114094436B CN202210061220.XA CN202210061220A CN114094436B CN 114094436 B CN114094436 B CN 114094436B CN 202210061220 A CN202210061220 A CN 202210061220A CN 114094436 B CN114094436 B CN 114094436B
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Abstract
The present disclosure relates to a driving apparatus and method for processing a driving current. The driving device comprises a main driving circuit and a driving circuit, wherein the main driving circuit is used for outputting a main driving current to an output end of the driving device; a first auxiliary drive line for outputting a first auxiliary drive current to the output terminal; the second auxiliary driving circuit is used for outputting a second auxiliary driving current, and the three currents are superposed to form a target current; the control circuit is respectively connected with the three driving circuits and acquires main driving signals and auxiliary driving signals; controlling a main driving circuit to output main driving current according to a corresponding rule according to the main driving signal; controlling a first auxiliary driving circuit to output a first auxiliary driving current according to the main driving signal and the auxiliary driving signal and a corresponding rule; and controlling a second auxiliary driving circuit to output a second auxiliary driving current according to the auxiliary driving signal and the corresponding rule. The scheme can de-emphasize the rising edge of the output signal and pre-emphasize the falling edge, so that the requirements of different rates of the rising edge and the falling edge of the device to be driven can be met.
Description
Technical Field
The present disclosure relates generally to the field of power electronics. More particularly, the present disclosure relates to a driving apparatus and method for processing a driving current.
Background
The laser has excellent performance and low cost, so that the laser is widely applied to data optical fiber communication systems. However, there is attenuation of the optical signal of the laser, which affects the data transmission of the laser, and the effect is more significant the higher the transmission rate of the data is. The effects of laser optical signal attenuation can now be overcome by using pre-emphasis techniques in the driver of the laser.
For example, a Vertical-Cavity Surface-Emitting Laser ("VCSEL") has a non-ideal characteristic that a rising edge speed of an optical signal is fast and a falling edge speed of the optical signal is slow in photoelectric conversion. However, current pre-emphasis techniques can only pre-emphasize or de-emphasize both the rising and falling edges of the laser drive signal. This same polarity emphasis often results in either an overcompensation of the rising edge or an undercompensation of the falling edge of the laser optical signal, which does not properly compensate for the attenuation of the optical signal.
Disclosure of Invention
At least in view of the above drawbacks in the background art, the embodiments of the present disclosure provide a driving apparatus and a method for processing a driving current. The driving device and the driving method can de-emphasize the rising edge of the output signal and pre-emphasize the falling edge at the same time, thereby meeting the requirements of different rates of the rising edge and the falling edge of the equipment to be driven.
In a first aspect, the present disclosure provides a driving device for processing a driving current, comprising: a main drive line for outputting a main drive current to an output terminal of the drive device; the first auxiliary driving circuit is used for outputting a first auxiliary driving current to the output end so that the main driving current and the first auxiliary driving current are superposed at the output end to form a superposed current; the second auxiliary driving circuit is used for outputting a second auxiliary driving current to the output end so that the superposed current and the second auxiliary driving current are superposed at the output end to form a target current; and a control circuit connected to the main drive line, the first auxiliary drive line, and the second auxiliary drive line, respectively, and configured to: acquiring a main driving signal and an auxiliary driving signal; controlling the main driving circuit to output main driving current to the output end according to the main driving signal and a corresponding rule; controlling the first auxiliary driving circuit to output a first auxiliary driving current to the output end according to the main driving signal and the auxiliary driving signal and a corresponding rule so as to be superposed with the main driving current to form the superposed current; and controlling the second auxiliary driving circuit to output a second auxiliary driving current to the output end according to a corresponding rule according to the auxiliary driving signal so as to be superposed with the superposed current to form the target current.
In one embodiment, the control circuit includes: a first controllable switch connected in the main drive line and configured to: acquiring the main driving signal; and according to the main driving signal, turning on or turning off to control the main driving line to output or not output the main driving current to the output end; a second controllable switch assembly connected in the first auxiliary drive line and configured to: acquiring the main drive signal and the auxiliary drive signal; and according to the main drive signal and the auxiliary drive signal, the first auxiliary drive circuit is controlled to output or not output the first auxiliary drive current to the output end; and a third controllable switch assembly connected in the second auxiliary drive line and configured to: acquiring the auxiliary driving signal; and according to the auxiliary driving signal, the second auxiliary driving circuit is switched on or switched off so as to control the second auxiliary driving circuit to output or not output the second auxiliary driving current to the output end.
In one embodiment, the second controllable switch assembly comprises: a second controllable switch for: acquiring the auxiliary driving signal; and according to the auxiliary driving signal, turning on or turning off to control the first auxiliary driving line to output or not output the first auxiliary driving current to the output end; and a third controllable switch electrically connected to the second controllable switch and configured to: acquiring the main driving signal; and the first auxiliary driving circuit is switched on or switched off according to the main driving signal so as to control the first auxiliary driving circuit to output or not output the first auxiliary driving current to the output end together with the second controllable switch.
In one embodiment, the first controllable switch comprises: the control end is connected with the input negative end of a main driving signal and is used for acquiring the main driving signal; the communication line is respectively electrically connected with the control end, a main current source of the main driving line and the output end, and is used for switching on or off according to the main driving signal so as to control the main current source to output or not output the main driving current to the output end; and wherein the second controllable switch comprises: the control end is connected with the input positive end of the auxiliary driving signal and is used for acquiring the auxiliary driving signal; and the communication line is respectively and electrically connected with the control end, the first auxiliary current source of the first auxiliary driving line and the communication line of the first controllable switch, and is used for switching on or off according to the auxiliary driving signal so as to control the first auxiliary current source to output or not output the first auxiliary driving current to the output end through the communication line of the second controllable switch and the communication line of the first controllable switch.
In one embodiment, the third controllable switch assembly comprises: a fourth controllable switch for: acquiring the auxiliary driving signal; and according to the auxiliary driving signal, the second auxiliary driving circuit is switched on or switched off so as to control the second auxiliary driving circuit to output or not output the second auxiliary driving current to the output end.
In one embodiment, the main drive line is further configured to output a main drive current to a first bypass output terminal of the driving device, and the control circuit is further configured to control the main drive line to output a main drive current to the first bypass output terminal according to the main drive signal.
In one embodiment, the control circuit further comprises: a fifth controllable switch connected in a connection line of the main drive line and the first bypass output and configured to: acquiring the main driving signal; and according to the main driving signal, the main driving circuit is switched on or switched off to control the main driving circuit to output or not output the main driving current to the first bypass output end.
In one embodiment, the second auxiliary drive line is further for outputting a third auxiliary drive current to a second bypass output of the drive device, and the control circuit is further for controlling the second auxiliary drive line to output the third auxiliary drive current to the second bypass output in dependence on the auxiliary drive signal.
In one embodiment, the control circuit further comprises: a sixth controllable switch connected in the connection line of the second auxiliary drive line and the second bypass output and configured to: acquiring the auxiliary driving signal; and according to the auxiliary driving signal, the second auxiliary driving circuit is switched on or switched off to control the second auxiliary driving circuit to output or not output the third auxiliary driving current to the second bypass output end.
In one embodiment, the second auxiliary drive line comprises a delayed current source and the fourth controllable switch comprises: the control end is connected with the input negative end of the auxiliary driving signal and is used for acquiring the auxiliary driving signal; and a communication line electrically connected to the control terminal, the delay current source and the output terminal, respectively, and configured to be turned on or off according to the auxiliary driving signal to control the delay current source to output or not output the second auxiliary driving current to the output terminal; and wherein the sixth controllable switch comprises: the control end is connected with the input negative end of the auxiliary driving signal and is used for acquiring the auxiliary driving signal; and a communication line electrically connected to the control terminal, the delay current source, and the second bypass output terminal, respectively, and configured to be turned on or off according to the auxiliary driving signal to control the delay current source to output or not output the third auxiliary driving current to the second bypass output terminal.
In one embodiment, the auxiliary drive signal is a delayed signal of the main drive signal. In a second aspect, the present disclosure also provides a method for processing a driving current, which is applied to a driving apparatus that processes a driving current, and which includes a main driving line, a first auxiliary driving line, and a second auxiliary driving line; the method comprises the following steps: acquiring a main driving signal and an auxiliary driving signal; controlling the main driving circuit to output main driving current to the output end of the driving device according to the main driving signal and a corresponding rule; controlling the first auxiliary driving circuit to output a first auxiliary driving current to the output end according to the main driving signal and the auxiliary driving signal and a corresponding rule so as to be superposed with the main driving current to form a superposed current; and controlling the second auxiliary driving circuit to output a second auxiliary driving current to the output end according to the corresponding rule according to the auxiliary driving signal so as to be superposed with the superposed current to form a target current.
Based on the above description of the disclosed embodiments, those skilled in the art will understand that the present disclosure can superpose the main driving current, the first auxiliary driving current and the second auxiliary driving current to form the rising edge de-emphasis current and the falling edge pre-emphasis current through the setting of the output rules of the main driving current, the first auxiliary driving current and the second auxiliary driving current, so that the rising edge de-emphasis and the falling edge pre-emphasis of the output signal can be performed simultaneously. Therefore, the output signal can meet the requirement that the rising edge and the falling edge of the device to be driven have different rates, and the attenuation of the optical signal of the VCSEL waiting driving device can be compensated better.
Drawings
The above and other objects, features and advantages of exemplary embodiments of the present disclosure will become readily apparent from the following detailed description read in conjunction with the accompanying drawings. In the drawings, several embodiments of the disclosure are illustrated by way of example and not by way of limitation, and like or corresponding reference numerals indicate like or corresponding parts and in which:
fig. 1 is a circuit diagram of a prior art VCSEL driver with pre-emphasis function;
FIG. 2 is a waveform diagram of a main signal, a delayed signal, a main drive stage current, a delayed drive stage current, a pre-emphasis current, and a drive current of the driver of FIG. 1;
FIG. 3 is a schematic block diagram of a driving apparatus for processing a driving current according to an embodiment of the disclosure;
FIG. 4 is a functional block diagram of a drive device provided in another embodiment of the present disclosure;
fig. 5 is a specific circuit of a driving apparatus according to an embodiment of the present disclosure;
fig. 6 is a waveform diagram of a driving signal of the driving apparatus of fig. 5 and a driving current output to an output terminal;
fig. 7 is a flowchart illustrating a method for processing a driving current according to an embodiment of the disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some, but not all embodiments of the present disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.
Fig. 1 is a circuit diagram of a prior art VCSEL driver 100 with pre-emphasis. The driver 100 is a differential structure and comprises a main drive stage and a delay drive stage. The main drive stage is coupled to a main current source iman to provide a main drive stage current I1, and the delay drive stage is coupled to a delay drive current source IDELAY to provide a delay drive stage current I2.
The Main signal Main is input to the Main driving stage to control it to output a Main driving stage current I1 to the output terminal a of the driver 100. The Main signal Main is delayed to generate a Delay signal Delay, which is input to the Delay driver stage to control the Delay driver stage to output a Delay driver stage current I2 to the output terminal a. And after the main driving stage current I1 and the delay driving stage current I2 are superposed at the output end a, pre-emphasis is completed, and a pre-emphasis current is generated. The pre-emphasis current is subtracted from the bias current generated by the bias current source IBIAS to obtain the driving current Iout of the driver 100. Further, the driving current Iout is output to the VCSEL as an output signal (i.e. a driving signal of the VCSEL) to drive the VCSEL to generate an optical signal.
Fig. 2 shows waveforms of the Main signal Main, the Delay signal Delay, the Main driving stage current I1 (denoted by the symbol Imain as the magnitude of I1), the Delay driving stage current I2 (denoted by Id as the magnitude of I2), the pre-emphasis current (i.e., I1+ I2), and the driving current Iout of the driver 100 in fig. 1, respectively.
As can be seen from the waveform diagram of the driving current Iout, the rising edge and the falling edge of the output signal are both pre-emphasis currents. This manner of emphasizing the same polarity on the rising and falling edges results in overcompensation for the rising edge of the faster VCSEL and undercompensation for the falling edge of the slower VCSEL, which does not properly compensate for the optical signal attenuation.
In view of this, the embodiments of the present disclosure provide a driving apparatus and method for processing a driving current. The scheme can output the main driving current, the first auxiliary driving current and the second auxiliary driving current to the output end of the driving device according to the corresponding rule by controlling the three driving lines. The drive currents are overlapped to form a rising edge de-emphasis current and a falling edge pre-emphasis current through regular setting, so that the rising edge of the output signal can be de-emphasized and the falling edge of the output signal can be pre-emphasized at the same time. Therefore, the output signal can meet the requirement that the rising edge and the falling edge of the device to be driven have different rates, and the attenuation of the optical signal of the VCSEL waiting driving device can be compensated better.
Fig. 3 is a schematic block diagram of a driving apparatus 300 for processing a driving current according to an embodiment of the present disclosure.
As shown in fig. 3, the driving apparatus 300 may include a main driving line 301, a first auxiliary driving line 302, a second auxiliary driving line 303, and a control circuit 304. The main driving line 301 may be used to output a main driving current to the output terminal b of the driving apparatus 300. In one implementation scenario, the main drive line 301 may include a main current source to output a main drive current to the output b of the drive device 300. In addition, the main current source may be a direct current source.
The first auxiliary driving circuit 302 may be configured to output a first auxiliary driving current to the output terminal b, so that the main driving current and the first auxiliary driving current are superimposed at the output terminal to form a superimposed current. In one implementation scenario, the first auxiliary drive line 302 may include a first auxiliary current source to output a first auxiliary drive current to the output b of the drive device. In addition, the first auxiliary current source may be a direct current source.
The second auxiliary driving circuit 303 may be configured to output a second auxiliary driving current to the output terminal b, so that the superimposed current and the second auxiliary driving current are superimposed at the output terminal to form a target current. In one implementation scenario, the second auxiliary drive line 303 may comprise a second auxiliary current source to output a second auxiliary drive current to the output b of the drive device. In addition, the second auxiliary current source may be a direct current source.
The control circuit 304 may be connected to the main drive line 301, the first auxiliary drive line 302, and the second auxiliary drive line 303, respectively, and configured to acquire a main drive signal and an auxiliary drive signal. In one implementation scenario, the primary drive signal may be a primary signal that drives a device to be driven (e.g., a VCSEL), and the secondary drive signal may be a delayed signal of the primary drive signal. The delay time of the delay signal may be specifically set as needed, and may be any time within one signal period of the main drive signal, for example, 1/2 or 3/4 periods.
After acquiring the main driving signal and the auxiliary driving signal, the control circuit 304 may control the main driving circuit 301 to output the main driving current to the output end according to the corresponding rule according to the main driving signal. The rule here may be, for example, a correspondence between the high and low levels of the main drive signal and whether or not the main drive current is output to the output terminal.
In addition, the control circuit 304 may further control the first auxiliary driving line 302 to output the first auxiliary driving current to the output terminal according to the corresponding rule according to the main driving signal and the auxiliary driving signal, so as to form a superimposed current by superimposing the first auxiliary driving current with the main driving current. The rule for outputting the first auxiliary driving current to the output terminal may be similar to the rule described above, and may be, for example, a correspondence relationship between high and low levels of the main driving signal and the auxiliary driving signal and whether or not to output the first auxiliary driving current to the output terminal.
Further, the control circuit 304 may further control the second auxiliary driving circuit to output a second auxiliary driving current to the output terminal b according to the corresponding rule according to the auxiliary driving signal, so as to form the target current by being superimposed with the superimposed current. Similarly to the above rule, the rule for outputting the second auxiliary driving current may be a corresponding relationship between the high and low levels of the auxiliary driving signal and whether to output the second auxiliary driving current to the output terminal.
The output rules of the main driving current, the first auxiliary driving current and the second auxiliary driving current are set so that the main driving current, the first auxiliary driving current and the second auxiliary driving current are superposed to form a rising edge de-emphasis current and a falling edge pre-emphasis current, so that the rising edge of an output signal can be de-emphasized and the falling edge of the output signal can be pre-emphasized at the same time. Therefore, the output signal can meet the requirement that the rising edge and the falling edge of the device to be driven have different rates, and the attenuation of the optical signal of the VCSEL waiting driving device can be compensated better.
The control circuit 304 may be implemented by various specific circuits, for example, it may be implemented by a controllable switch and/or a controllable switch component which is simple and reliable in control manner, easy to implement, and low in cost. For example, in the embodiment shown in fig. 4, the control circuit 304 may include a first controllable switch 3041, a second controllable switch assembly 3042, and a third controllable switch assembly 3043. The first controllable switch 3041 may be connected in the main driving line 301 and configured to obtain a main driving signal, and turn on or off according to the main driving signal to control the main driving line 301 to output or not output a main driving current to an output terminal. In one implementation, the first controllable switch 3041 may include a field effect transistor or a triode. Reference numeral 400 in fig. 4 denotes a driving device.
In order to facilitate a full understanding of the arrangement of the controllable switches and/or controllable switch groups of the present disclosure, the following will be further described in conjunction with the specific circuit of the driving apparatus 500 in fig. 5 and the waveforms of the driving signal and the driving current output to the output terminal shown in fig. 6 (Iout in fig. 6 is the driving current).
As can be seen from fig. 5, the first controllable switch 3041 may include an NMOS ("N-Metal-Oxide-Semiconductor") transistor Q1. The gate of the NMOS transistor Q1 may be connected to the negative input terminal of the Main driving signal, so as to obtain the Main driving signal Main. The NMOS transistor Q1 may have a source and a drain connected to the Main driving line 301, a drain connected to the output terminal b of the driving device 500, and a source connected to the Main current source IMAIN for turning on or off according to the received Main driving signal Main, thereby turning on or off the Main driving line 301.
Based on the connection relationship of the first controllable switch 3041 in the driving apparatus 500, the waveform of the Main driving signal Main shown in fig. 6 and the waveform of the Main driving current Imain output to the output terminal b, the output rule of the Main driving current Imain is that when the Main driving signal Main is at a low level, the NMOS transistor Q1 is turned on, so that the Main driving circuit 301 is turned on, and the Main driving current Imain (generated by the Main current source Imain in the Main driving circuit 301) can be output to the output terminal b. Accordingly, when the Main driving signal Main is at a high level, the NMOS transistor Q1 is turned off, so that the Main driving line 301 is cut off, and the Main driving current Imain is not output to the output terminal b.
The second controllable switch assembly 3042 may be connected to the first auxiliary driving line 302, and configured to obtain the Main driving signal Main and the auxiliary driving signal Delay, and turn on or off according to the Main driving signal Main and the auxiliary driving signal Delay, so as to control the first auxiliary driving line 302 to output or not output the first auxiliary driving current Iv to the output terminal b. The second controllable switch assembly 3042 may include a plurality of controllable switches, e.g., 2 or 3, etc., based on different application scenarios. In addition, the controllable switch may include a field effect transistor or a triode, similar to the first controllable switch 3041 described above.
Further, the third controllable switch assembly 3043 may be connected in the second auxiliary driving line 303 and configured to obtain the auxiliary driving signal Delay, and turn on or off according to the auxiliary driving signal Delay, so as to control the second auxiliary driving line 303 to output or not output the second auxiliary driving current Iz to the output end b. In addition, the third controllable switch assembly 3043 may include 1 controllable switch, and may also include a plurality of controllable switches, for example, 2 or 3, etc. In addition, the controllable switch may also comprise a field effect transistor or a triode.
According to the scheme, the corresponding driving circuit can be controlled to be switched on or switched off by controlling each controllable switch or controllable switch assembly, so that the corresponding driving signals can be output to the output end of the driving device according to the corresponding rule, and then the driving signals are superposed at the output end to form the target current.
As can be seen from the above description of the embodiments, the second controllable switch assembly 3042 may include a plurality of controllable switches. The second controllable switch assembly 3042 will be described below with the example of including 2 controllable switches. In particular, the second controllable switch assembly 3042 may include a second controllable switch and a third controllable switch. The second controllable switch may be configured to obtain an auxiliary driving signal, and turn on or off according to the auxiliary driving signal Delay to control the first auxiliary driving line 302 to output or not output the first auxiliary driving current Iv to the output terminal b.
A specific structure of a second controllable switch assembly is disclosed in fig. 5. As can be seen from fig. 5, the second controllable switch may include an NMOS transistor Q2, and the gate of the NMOS transistor Q2 may be connected to the positive input terminal of the auxiliary driving signal for obtaining the auxiliary driving signal Delay. The source and the drain of the NMOS transistor Q2 may be connected in the first auxiliary driving line 302, and the source thereof may be connected with a first auxiliary current source to be turned on or off according to the received auxiliary driving signal Delay, thereby implementing turning on or off of the first auxiliary driving line 302.
Specifically, when the auxiliary driving signal Delay is at a high level, the NMOS transistor Q2 is turned on, so that the first auxiliary driving line 302 is turned on, and the first auxiliary driving current Iv (generated by the first auxiliary current source in the first auxiliary driving line 302) may be output to the output terminal b. Accordingly, when the auxiliary driving signal Delay is at a low level, the NMOS transistor Q2 is turned off, so that the first auxiliary driving line 302 is cut off, and the first auxiliary driving current Iv is not output to the output terminal b.
The third controllable switch may be electrically connected to the second controllable switch and configured to obtain the Main driving signal Main, and turn on or off according to the Main driving signal Main to control the first auxiliary driving line 302 to output or not output the first auxiliary driving current Iv to the output terminal b together with the second controllable switch.
The third controllable switch may also include an NMOS transistor (not shown), and the gate of the NMOS transistor may be connected to the negative input terminal of the Main driving signal, so as to obtain the Main driving signal Main. The source and the drain of the NMOS transistor may be connected in the first auxiliary driving line 302, the source thereof may be connected to the drain of the NMOS transistor Q2, and the drain thereof may be connected to the output terminal b of the driving apparatus 500, so as to be turned on or off according to the received Main driving signal Main, thereby implementing the turning on or off of the first auxiliary driving line 302.
Based on the connection relationship of the second controllable switch element 3042 in the driving apparatus 500, and the waveforms of the Main driving signal Main and the auxiliary driving signal Delay shown in fig. 6, and the waveform of the first auxiliary driving current Iv output to the output terminal b, the output rule of the first auxiliary driving current Iv is that when the Main driving signal Main is at a low level and the auxiliary driving signal Delay is at a high level, the NMOS transistor serving as the third controllable switch and the NMOS transistor Q2 are turned on, so that the first auxiliary driving line 302 is turned on, and the first auxiliary driving current Iv can be output to the output terminal b.
In other cases, for example, when the Main driving signal Main and the auxiliary driving signal Delay are at the same level (both are at low level or both are at high level) or the Main driving signal Main is at high level, and the auxiliary driving signal Delay is at low level, the NMOS transistor and the NMOS transistor Q2 as the third controllable switch cannot be turned on at the same time, so that the first auxiliary driving line 302 is open-circuited, and the first auxiliary driving current Iv is not output to the output terminal b.
The output rule of the first auxiliary drive current Iv is described above in connection with the embodiment. It is understood that the structure of the second controllable switch assembly 3042 is merely exemplary and not limiting, and those skilled in the art can adapt the configuration to meet the requirements of different application scenarios. For example, in the implementation scenario shown in fig. 5, the first auxiliary current source and the second auxiliary current source may use one current source IDELAY. Based on this, the third controllable switch and the first controllable switch may share one NMOS transistor (e.g., NMOS transistor Q1).
In one embodiment, the third controllable switch assembly 3043 may include a fourth controllable switch. The fourth controllable switch may be configured to obtain an auxiliary driving signal Delay, and turn on or off according to the auxiliary driving signal Delay to control the second auxiliary driving line to output or not output the second auxiliary driving current Iz to the output end b.
A specific structure of a third controllable switch assembly is further disclosed in fig. 5. In the embodiment shown in fig. 5, the fourth controllable switch may also include an NMOS transistor Q3, and the gate of the NMOS transistor Q3 may be connected to the negative input terminal of the auxiliary driving signal, so as to obtain the auxiliary driving signal Delay. The source and the drain of the NMOS transistor Q3 may be connected in the second auxiliary driving line 303, the source thereof may be connected with a second auxiliary current source, and the drain thereof may be connected with the output terminal b of the driving device 500, so as to be turned on or off according to the received auxiliary driving signal Delay, thereby implementing the turning on or off of the second auxiliary driving line 303.
Specifically, when the auxiliary driving signal Delay is at a low level, the NMOS transistor Q3 is turned on, so that the second auxiliary driving line 303 is turned on, and the second auxiliary driving current Iz (generated by the second auxiliary current source) may be output to the output terminal b. Accordingly, when the auxiliary driving signal Delay is at a high level, the NMOS transistor Q3 is turned off, so that the second auxiliary driving line 303 is cut off, and the second auxiliary driving current Iz is not output to the output terminal b.
Based on the connection relationship of the fourth controllable switch in the driving device, the waveform of the auxiliary driving signal Delay shown in fig. 6, and the waveform of the second auxiliary driving current Iz output to the output terminal b, it can be known that the output rule of the second auxiliary driving current Iz output to the output terminal b is that when the auxiliary driving signal Delay is at a low level, the NMOS transistor Q3 is turned on, so that the second auxiliary driving line 303 is turned on, and the second auxiliary driving current Iz can be output to the output terminal b. Accordingly, when the auxiliary driving signal Delay is at a high level, the NMOS transistor Q3 is turned off, so that the second auxiliary driving line 303 is turned off, and the second auxiliary driving current Iz is not output to the output terminal b.
After the target current is obtained in the above manner, the output current Iout may be obtained by subtracting the target current from the bias current generated by the bias current source IBIAS, and output to a device to be driven, such as the VCSEL in fig. 5, so as to drive the device.
The output rules of the main driving current, the first auxiliary driving current and the second auxiliary driving current are described above by taking the controllable switches as NMOS transistors as examples. It is understood that, depending on the application, other switching elements, such as PMOS transistors, may be used for each of the controllable switches. At this time, the connection relationship between the input end of the driving signal and the controllable switch can be rearranged, so that the driving signal can output the driving current according to the corresponding relationship between the high and low levels of the driving signal and whether the driving current is output to the output end. For example, the gate of the PMOS transistor serving as the first controllable switch 3041 may be connected to the positive input terminal of the main drive signal.
As can be seen from the foregoing description of the embodiments, in some scenarios, the driving current does not need to be output to the output terminal b. The driving current can be output to the bypass output terminal at this time. For example, the main drive line 301 may also be used to output a main drive current Imain to the first bypass output c of the drive device. Based on this, the control circuit 304 may also be configured to control the Main driving line 301 to output the Main driving current Imain to the first bypass output terminal c according to the Main driving signal Main.
Similarly to the previous embodiment, the control circuit 304 in this embodiment may also control the connection between the main driving circuit 301 and the first bypass output end c to be switched on or off by the controllable switch. Further, the control circuit 304 may comprise a fifth controllable switch. The fifth controllable switch may be connected in a connection line between the Main driving line 301 and the first bypass output terminal c and configured to obtain the Main driving signal Main, and turn on or off according to the Main driving signal Main to control the Main driving line 301 to output or not output the Main driving current Imain to the first bypass output terminal c.
The specific circuit of the main drive line 301 connected to the bypass output is further disclosed in fig. 5. As can be seen from fig. 5, the fifth controllable switch may also include an NMOS transistor Q4, and the gate of the NMOS transistor Q4 may be connected to the positive input terminal of the Main driving signal Main for obtaining the Main driving signal Main. The NMOS transistor Q4 may have a source and a drain connected to a connection line between the Main driving line 301 and the first bypass output terminal c, a drain connected to the first bypass output terminal c, and a source connected to the Main current source IMAIN, so as to be turned on or off according to the received Main driving signal Main, thereby implementing turning on or off of the connection line between the Main driving line 301 and the first bypass output terminal c.
Specifically, when the Main driving signal Main is at a high level, the NMOS transistor Q4 is turned on, so that the connection line is turned on, and the Main driving current Imain can be output to the first bypass output terminal c. Accordingly, when the Main driving signal Main is at a low level, the NMOS transistor Q4 is turned off, so that the connection line is cut off, and the Main driving current Imain is not output to the first bypass output terminal c.
Similarly to the main drive line 301, the second auxiliary drive line 302 may also be used to output a third auxiliary drive current to the second bypass output of the drive device. In particular, the second auxiliary drive line 302 may be connected to a second bypass output of the drive device to output a third auxiliary drive current thereto. Based on this, the control circuit 304 may also be configured to control the second auxiliary driving line 303 to output the third auxiliary driving current to the second bypass output terminal according to the auxiliary driving signal Delay.
In one embodiment, the control circuit 304 may further include a sixth controllable switch. The sixth controllable switch may be connected in a connection line between the second auxiliary driving line 303 and the second bypass output terminal, and configured to acquire the auxiliary driving signal Delay, and turn on or off according to the auxiliary driving signal Delay to control the second auxiliary driving line 303 to output or not output the second auxiliary driving current to the second bypass output terminal.
The specific circuit of this part is also disclosed in fig. 5. As can be seen from fig. 5, the sixth controllable switch may also include an NMOS transistor Q5, and the gate of the NMOS transistor Q5 may be connected to the negative input terminal of the auxiliary driving signal, so as to obtain the auxiliary driving signal Delay. The source and the drain of the NMOS transistor Q5 may be connected in a connection line between the second auxiliary driving line 303 and the second bypass output terminal, the drain thereof may be connected to the second bypass output terminal, and the source thereof may be connected to the second auxiliary current source to be turned on or off according to the received auxiliary driving signal Delay, thereby implementing turning on or off of the connection line between the second auxiliary driving line 303 and the second bypass output terminal.
Specifically, when the auxiliary drive signal Delay is at a low level, the NMOS transistor Q5 is turned on, so that the second auxiliary drive line 303 is turned on, and the third auxiliary drive current may be output to the second bypass output terminal. Accordingly, when the auxiliary driving signal Delay is at a high level, the NMOS transistor Q5 is turned off, so that the second auxiliary driving line 303 is cut off, and the third auxiliary driving current is not output to the second bypass output terminal.
In the implementation scenario shown in fig. 5, one current source IDELAY may be used for the first and second auxiliary current sources. In addition, as can be seen from fig. 6, the magnitude of the rising edge de-emphasis current and the magnitude of the falling edge pre-emphasis current may correspond to the magnitudes of the first auxiliary driving current and the second auxiliary driving current, respectively, for example, the magnitude of the rising edge de-emphasis current is equal to the magnitude of the second auxiliary driving current, and the magnitude of the falling edge pre-emphasis current is equal to the magnitude of the first auxiliary driving current minus the magnitude of the second auxiliary driving current.
Based on this and the conduction mode of the NMOS transistor Q3 and the NMOS transistor Q5 (conducting when the auxiliary driving signal Delay is low), adjusting the ratio of the current conduction capability of the NMOS transistor Q3 and the NMOS transistor Q5 and the magnitude of the driving current IDELAY generated by the current source IDELAY can adjust the magnitudes of the falling edge pre-emphasis current and the rising edge de-emphasis current, so as to adjust the magnitudes of the falling edge pre-emphasis current and the rising edge de-emphasis current of the output signal. For example, when the current conduction capacities of the NMOS transistor Q3 and the NMOS transistor Q5 are the same, the magnitude of the first auxiliary driving current Iv is equal to the magnitude of the driving current Idelay, and the magnitude of the second auxiliary driving current Iz is 1/2 of the driving current Idelay. The mode reduces the consumption of NMOS tubes, thereby simplifying the structure of the driving device and reducing the cost. Further, the current conducting capacity of the NMOS tube can be adjusted by adjusting the width-length ratio of the NMOS tube.
In order to simplify the structure of the driving apparatus and thus reduce the cost, the first bypass output terminal c and the second bypass output terminal may be provided as one end as shown in fig. 5. In order to match the bypass output terminal with the output terminal b of the drive device, a resistor may be connected to the bypass output terminal, and the main drive line 301 and the second sub drive line 303 may be connected to each other via the resistor.
As can be seen from the foregoing description of the embodiments, the present disclosure can facilitate the control by setting the connection relationship and the control relationship of the above-mentioned respective controllable switches. Taking the first controllable switch 3041, the second controllable switch, the fourth controllable switch, and the sixth controllable switch as an example, each of the four controllable switches may include a control terminal and a communication line.
For the first controllable switch 3041, its control terminal is connected to the input negative terminal of the main drive signal and is used to obtain the main drive signal. The communication circuit is respectively electrically connected with the control end, the main current source of the main driving circuit and the output end, and is used for switching on or off according to the main driving signal so as to control the main current source to output or not output the main driving current to the output end.
For the second controllable switch, its control terminal is connected to the positive input terminal of the auxiliary drive signal and is used to obtain the auxiliary drive signal. The connection lines are electrically connected to the control terminal, the first auxiliary current source of the first auxiliary driving line, and the connection line of the first controllable switch 3041, respectively, and are used for turning on or off according to the auxiliary driving signal, so as to control the first auxiliary current source to output or not output the first auxiliary driving current to the output terminal through the connection line of the second controllable switch and the connection line of the first controllable switch 3041.
The second auxiliary drive line may comprise a delayed current source, based on which a fourth controllable switch, the control terminal of which is connected to the input negative terminal of the auxiliary drive signal and is used to derive the auxiliary drive signal. And the communication line is respectively electrically connected with the control end, the delay current source and the output end and is used for switching on or off according to the auxiliary driving signal so as to control the delay current source to output or not output a second auxiliary driving current to the output end.
And for the sixth controllable switch, the control end of the sixth controllable switch is connected with the input negative end of the auxiliary driving signal and is used for acquiring the auxiliary driving signal. And the communication line is respectively electrically connected with the control end, the delay current source and the second bypass output end and is used for switching on or off according to the auxiliary driving signal so as to control the delay current source to output or not output a third auxiliary driving current to the second bypass output end.
To facilitate a fuller understanding of the drive arrangement of the present disclosure, further description will be continued with fig. 5. As shown in fig. 5, the driving device 500 includes a main current source iman, a delay current source IDELAY, a bias current source IBIAS, an NMOS transistor Q1, an NMOS transistor Q2, an NMOS transistor Q3, an NMOS transistor Q4, and an NMOS transistor Q5.
The gate of the NMOS transistor Q1 is connected to the negative input terminal of the main driving signal, the source of the NMOS transistor Q1 is connected to the main current source IMAIN, and the drain of the NMOS transistor Q1 is connected to the output terminal b of the driving device 500, so that the main driving circuit 301 is formed by the connection. The gate of the NMOS transistor Q2 is connected to the positive input terminal of the auxiliary driving signal, the drain of the NMOS transistor Q2 is connected to the source of the NMOS transistor Q1, and the source of the NMOS transistor Q2 is connected to the delay current source IDELAY, by which the first auxiliary driving line 302 is formed.
The gates of the NMOS transistor Q3 and the NMOS transistor Q5 are both connected to the negative input terminal of the auxiliary driving signal, the drain of the NMOS transistor Q3 is connected to the output terminal b of the driving device 500, the drain of the NMOS transistor Q5 is connected to the bypass output terminal c through a resistor, the sources of the NMOS transistor Q3 and the NMOS transistor Q5 are both connected to the delay current source IDELAY, and the second auxiliary driving line 303 and the connection line between the second auxiliary driving line 303 and the bypass output terminal (hereinafter referred to as the second bypass output line) are formed by the connection.
The gate of the NMOS transistor Q4 is connected to the positive input terminal of the auxiliary drive signal, the source of the NMOS transistor Q4 is connected to the main current source IMAIN, and the drain of the NMOS transistor Q4 is connected to the bypass output terminal c via the resistor, and this connection forms a connection line between the main drive line 301 and the bypass output terminal c (hereinafter referred to as a first bypass output line).
Based on the above circuit connection relationship, the operation principle of the driving device 500 is as follows:
when the Main driving signal Main is at a low level and the auxiliary driving signal Delay is at a high level, the NMOS transistor Q1 is turned on, the NMOS transistor Q4 is turned off, the Main driving circuit 301 is connected, and the Main current source IMAIN outputs a Main driving current IMAIN to the output end b. In addition, at this time, the NMOS transistor Q2 is turned on, the NMOS transistor Q3 and the NMOS transistor Q5 are turned off, the first auxiliary driving line 302 is connected, and the delay current source IDELAY outputs the driving current IDELAY to the output terminal b.
When the Main drive signal Main and the auxiliary drive signal Delay are both at a low level, the NMOS transistor Q1 is turned on, the NMOS transistor Q4 is turned off, the Main drive line 301 is connected, and the Main current source IMAIN outputs a Main drive current IMAIN to the output terminal b. In addition, at this time, the NMOS transistor Q2 is turned off, the NMOS transistor Q3 and the NMOS transistor Q5 are simultaneously turned on, the second auxiliary driving line 303 and the second bypass output line are connected, and the delay current source IDELAY outputs the second auxiliary driving current Iz to the output terminal b and outputs the third auxiliary driving current to the bypass output terminal c. At this time, if the current conducting capabilities of the NMOS transistor Q3 and the NMOS transistor Q5 are the same, the magnitudes of the second auxiliary driving current Iz and the third auxiliary driving current are 1/2 of Idelay.
When the Main driving signal Main is at a high level and the auxiliary driving signal Delay is at a low level, the NMOS transistor Q1 is turned off, the NMOS transistor Q4 is turned on, the first bypass output line is connected, and the Main current source IMAIN outputs a Main driving current IMAIN to the bypass output terminal c. In addition, at this time, the NMOS transistor Q2 is turned on, the NMOS transistor Q3 and the NMOS transistor Q5 are turned off, only the first auxiliary driving line 302 is connected at this time, and the delay current source IDELAY outputs the driving current IDELAY to the output terminal b.
When the Main drive signal Main and the auxiliary drive signal Delay are both at a high level, the NMOS transistor Q1 is turned off, the NMOS transistor Q4 is turned on, the first bypass output line is connected at this time, and the Main current source IMAIN outputs a Main drive current IMAIN to the bypass output terminal c. In addition, at this time, the NMOS transistor Q2 is turned on, the NMOS transistor Q3 and the NMOS transistor Q5 are turned off, the second bypass output line is connected, and the delay current source IDELAY outputs the second auxiliary drive current Iz to the output terminal b and outputs the third auxiliary drive current to the bypass output terminal c. At this time, if the current conduction capacities of the NMOS transistor Q3 and the NMOS transistor Q5 are the same, the magnitudes of the second auxiliary driving current Iz and the third auxiliary driving current are 1/2 which is the magnitude of the driving current Idelay.
After the target current is obtained, subtracting the target current from the bias current generated by the bias current source IBIAS to obtain an output current Iout.
As can be seen from the above description, the main driving line 301 and the first auxiliary driving line 302 in the driving apparatus 500 may share the NMOS transistor Q1, so that the on and off of the first auxiliary driving line 302 may be commonly controlled by the combination of the NMOS transistor Q1 and the NMOS transistor Q2, and further, the first auxiliary driving line 302 may output the driving current Idelay to the output terminal b only when the NMOS transistor Q1 and the NMOS transistor Q2 are simultaneously turned on. When either one of the NMOS transistor Q2 or the NMOS transistor Q1 is turned off, the first auxiliary drive line 302 cannot output the drive current Idelay to the output terminal b. It can be seen that this arrangement facilitates reliable control of the first auxiliary drive line 302 and has a simple circuit structure.
In addition, since the NMOS transistor Q3 and the NMOS transistor Q5 are turned on and off at the same time, they provide two current paths for the delay current source IDELAY. The two current channels can realize the shunting of the driving current Idelay, the magnitude of the driving current Idelay can be changed through the shunting without changing, and the magnitude of the second auxiliary driving current Iz output to the output end b can be changed by only adjusting the current conduction capacities of the NMOS tube Q3 and the NMOS tube Q5, so that the second auxiliary driving current Iz can be conveniently adjusted. In addition, this arrangement allows the first auxiliary current source and the second auxiliary current source to share one current source, thereby simplifying the structure of the driving device 500 and reducing the cost.
Fig. 7 is a flowchart illustrating a method 700 for processing a driving current according to an embodiment of the disclosure.
In one embodiment, the method 700 may be applied to a drive device that processes a drive current, and the drive device may include a main drive line, a first auxiliary drive line, and a second auxiliary drive line.
Based on this, as shown in fig. 7, the method 700 may include acquiring a main drive signal and an auxiliary drive signal at step S701. In one implementation scenario, the primary drive signal may be a primary signal that drives a device to be driven (e.g., a VCSEL), and the secondary drive signal may be a drive signal of the primary drive signal. The delay time of the delay signal may be specifically set as needed, and may be any time within one signal period of the main drive signal, for example, 1/2 or 3/4 periods.
After the main driving signal and the auxiliary driving signal are obtained, the method may proceed to step S702, and control the main driving circuit to output the main driving current to the output end of the driving device according to the main driving signal and the corresponding rule. The rule here may be, for example, a correspondence between the high and low levels of the main drive signal and whether or not the main drive current is output to the output terminal. For example, the main drive current is output to the output terminal when the main drive signal is at a low level, and the main drive current is not output to the output terminal when the main drive signal is at a high level.
After outputting the main driving current to the output terminal, the method may enter step S703, and control the first auxiliary driving circuit to output the first auxiliary driving current to the output terminal according to the main driving signal and the auxiliary driving signal and the corresponding rule, so as to form a superimposed current by superimposing the first auxiliary driving current with the main driving current. The rules herein may be similar to the rules described above. For example, the corresponding relationship between the high and low levels of the main drive signal and the auxiliary drive signal and whether to output the first auxiliary drive current to the output terminal may be used. Specifically, the first auxiliary drive current may be output to the output terminal when the main drive signal is at a low level and the auxiliary drive signal is at a high level, and the first auxiliary drive current may not be output to the output terminal when the main drive signal is at a high level and the auxiliary drive signal is at a low level, for example.
Next, the method 700 may proceed to step S704, and control the second auxiliary driving line to output the second auxiliary driving current to the output terminal according to the corresponding rule according to the auxiliary driving signal, so as to form the target current by being superimposed with the superimposed current. Similarly to the above rule, the rule for outputting the second auxiliary driving current may be a corresponding relationship between the high and low levels of the auxiliary driving signal and whether to output the second auxiliary driving current to the output terminal. Specifically, the second auxiliary drive signal may be output to the output terminal when the auxiliary drive signal is at a low level, and the second auxiliary drive signal may not be output to the output terminal when the auxiliary drive signal is at a high level.
The output rules of the main driving current, the first auxiliary driving current and the second auxiliary driving current are set so that the main driving current, the first auxiliary driving current and the second auxiliary driving current are superposed to form a rising edge de-emphasis current and a falling edge pre-emphasis current, so that the rising edge of an output signal can be de-emphasized and the falling edge of the output signal can be pre-emphasized at the same time. Therefore, the output signal can meet the requirement that the rising edge and the falling edge of the device to be driven have different rates, and the attenuation of the optical signal of the VCSEL waiting driving device can be compensated better.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.
It should be understood that the terms "first," "second," "third," and "fourth," etc. in the claims, description, and drawings of the present disclosure are used to distinguish between different objects and are not used to describe a particular order. The terms "comprises" and "comprising," when used in the specification and claims of this disclosure, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only, and is not intended to be limiting of the disclosure. As used in the specification and claims of this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should be further understood that the term "and/or" as used in the specification and claims of this disclosure refers to any and all possible combinations of one or more of the associated listed items and includes such combinations.
As used in this specification and claims, the term "if" may be interpreted contextually as "when", "upon" or "in response to a determination" or "in response to a detection". Similarly, the phrase "if it is determined" or "if a [ described condition or event ] is detected" may be interpreted contextually to mean "upon determining" or "in response to determining" or "upon detecting [ described condition or event ]" or "in response to detecting [ described condition or event ]".
The above embodiments are only used for illustrating the technical solutions of the embodiments of the present disclosure, and not for limiting the same; although embodiments of the present disclosure have been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the respective embodiments of the present disclosure.
Claims (9)
1. A drive device for processing a drive current, comprising:
a main drive line for outputting a main drive current to an output terminal of the drive device;
the first auxiliary driving circuit is used for outputting a first auxiliary driving current to the output end so that the main driving current and the first auxiliary driving current are superposed at the output end to form a superposed current;
a second auxiliary driving circuit for outputting a second auxiliary driving current to the output terminal, so that the superimposed current and the second auxiliary driving current are superimposed at the output terminal to form a target current for de-emphasizing a rising edge and pre-emphasizing a falling edge of an output signal of the driving device; and
a control circuit, comprising:
a first controllable switch connected in the main drive line and configured to:
acquiring a main driving signal; and
the main driving circuit is switched on or switched off according to the main driving signal so as to control the main driving circuit to output or not output the main driving current to the output end;
a second controllable switch assembly, comprising:
a second controllable switch for:
acquiring an auxiliary driving signal; and
the first auxiliary driving circuit is switched on or switched off according to the auxiliary driving signal so as to control the first auxiliary driving circuit to output or not output the first auxiliary driving current to the output end; and
a third controllable switch electrically connected to the second controllable switch and configured to:
acquiring the main driving signal; and
according to the main driving signal, the first auxiliary driving circuit is switched on or switched off to control the first auxiliary driving circuit to output or not output the first auxiliary driving current to the output end together with the second controllable switch, wherein the third controllable switch and the first controllable switch share one switching element; and
a third controllable switch assembly connected in the second auxiliary drive line and configured to:
acquiring the auxiliary driving signal; and
and the second auxiliary driving circuit is switched on or switched off according to the auxiliary driving signal so as to control the second auxiliary driving circuit to output or not output the second auxiliary driving current to the output end.
2. The drive arrangement of claim 1, wherein the first controllable switch comprises:
the control end is connected with the input negative end of a main driving signal and is used for acquiring the main driving signal; and
a communication line electrically connected to the control terminal, a main current source of the main driving line, and the output terminal, respectively, and configured to be turned on or off according to the main driving signal to control the main current source to output or not output the main driving current to the output terminal; and
wherein the second controllable switch comprises:
a control terminal connected to an input positive terminal of the auxiliary drive signal and used for acquiring the auxiliary drive signal; and
and the communication line is respectively and electrically connected with the control end, the first auxiliary current source of the first auxiliary driving line and the communication line of the first controllable switch, and is used for switching on or off according to the auxiliary driving signal so as to control the first auxiliary current source to output or not output the first auxiliary driving current to the output end through the communication line of the second controllable switch and the communication line of the first controllable switch.
3. The drive of claim 1, wherein the third controllable switch assembly comprises:
a fourth controllable switch for:
acquiring the auxiliary driving signal; and
and the second auxiliary driving circuit is switched on or switched off according to the auxiliary driving signal so as to control the second auxiliary driving circuit to output or not output the second auxiliary driving current to the output end.
4. A drive arrangement according to claim 1 wherein the main drive line is further for outputting a main drive current to a first bypass output of the drive arrangement, and the control circuit is further for controlling the main drive line to output a main drive current to the first bypass output in dependence on the main drive signal.
5. The driving device according to claim 4, wherein the control circuit further comprises:
a fifth controllable switch connected in a connection line of the main drive line and the first bypass output and configured to:
acquiring the main driving signal; and
and the main driving circuit is switched on or switched off according to the main driving signal so as to control the main driving circuit to output or not output the main driving current to the first bypass output end.
6. A drive arrangement according to claim 3 wherein the second auxiliary drive line is further for outputting a third auxiliary drive current to a second bypass output of the drive arrangement, and the control circuit is further for controlling the second auxiliary drive line to output the third auxiliary drive current to the second bypass output in dependence on the auxiliary drive signal.
7. The driving device according to claim 6, wherein the control circuit further comprises:
a sixth controllable switch connected in the connection line of the second auxiliary drive line and the second bypass output and configured to:
acquiring the auxiliary driving signal; and
and the second auxiliary driving circuit is switched on or switched off according to the auxiliary driving signal so as to control the second auxiliary driving circuit to output or not output the third auxiliary driving current to the second bypass output end.
8. The drive arrangement of claim 7, wherein the second auxiliary drive line comprises a delayed current source and the fourth controllable switch comprises:
the control end is connected with the input negative end of the auxiliary driving signal and is used for acquiring the auxiliary driving signal; and
a communication line electrically connected to the control terminal, the delay current source and the output terminal, respectively, and configured to be turned on or off according to the auxiliary driving signal to control the delay current source to output or not output the second auxiliary driving current to the output terminal; and
wherein the sixth controllable switch comprises:
the control end is connected with the input negative end of the auxiliary driving signal and is used for acquiring the auxiliary driving signal; and
and a communication line electrically connected to the control terminal, the delay current source and the second bypass output terminal, respectively, and configured to be turned on or off according to the auxiliary driving signal to control the delay current source to output or not output the third auxiliary driving current to the second bypass output terminal.
9. A method for processing a drive current, which is applied to the drive device for processing a drive current according to any one of claims 1 to 8, and which comprises:
acquiring a main driving signal through the first controllable switch, and switching on or off according to the main driving signal to control the main driving line to output or not output the main driving current to the output end;
acquiring an auxiliary driving signal through the second controllable switch, and switching on or off according to the auxiliary driving signal to control the first auxiliary driving line to output or not output the first auxiliary driving current to the output end;
the third controllable switch is used for acquiring the main driving signal, and the main driving signal is switched on or switched off according to the main driving signal so as to control the first auxiliary driving line to output or not output the first auxiliary driving current to the output end together with the second controllable switch; and
and acquiring the auxiliary driving signal through the third controllable switch component, and switching on or off according to the auxiliary driving signal to control the second auxiliary driving circuit to output or not output the second auxiliary driving current to the output end, so that the output main driving current, the first auxiliary driving current and the second auxiliary driving current are superposed to form the target current.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01309582A (en) * | 1988-06-08 | 1989-12-13 | Sony Corp | Video signal processing circuit |
| JP2010010471A (en) * | 2008-06-27 | 2010-01-14 | Rohm Co Ltd | Drive circuit of laser diode |
| WO2010067860A1 (en) * | 2008-12-11 | 2010-06-17 | 国立大学法人 鹿児島大学 | Laser diode drive device |
| WO2013132691A1 (en) * | 2012-03-05 | 2013-09-12 | 株式会社日立製作所 | Laser diode drive device and drive method, and optical transmission system using same |
| CN103427331A (en) * | 2013-08-23 | 2013-12-04 | 西安电子科技大学 | Driver of vertical cavity surface emitting laser |
| CN103457154A (en) * | 2013-08-29 | 2013-12-18 | 烽火通信科技股份有限公司 | Integrated optical communication laser driver with pre-emphasis |
| CN204633746U (en) * | 2015-06-26 | 2015-09-09 | 灿芯半导体(上海)有限公司 | Output circuit in interface circuit |
| CN110896304A (en) * | 2019-09-27 | 2020-03-20 | 厦门优迅高速芯片有限公司 | High-speed amplitude and phase programmable rising edge/falling edge adjustable circuit |
| CN110896327A (en) * | 2019-10-10 | 2020-03-20 | 厦门优迅高速芯片有限公司 | Multi-dimensional signal eye diagram compensation circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7477850B2 (en) * | 2005-10-31 | 2009-01-13 | Agere Systems Inc. | Optical signal jitter reduction via electrical equalization in optical transmission systems |
-
2022
- 2022-01-19 CN CN202210061220.XA patent/CN114094436B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01309582A (en) * | 1988-06-08 | 1989-12-13 | Sony Corp | Video signal processing circuit |
| JP2010010471A (en) * | 2008-06-27 | 2010-01-14 | Rohm Co Ltd | Drive circuit of laser diode |
| WO2010067860A1 (en) * | 2008-12-11 | 2010-06-17 | 国立大学法人 鹿児島大学 | Laser diode drive device |
| WO2013132691A1 (en) * | 2012-03-05 | 2013-09-12 | 株式会社日立製作所 | Laser diode drive device and drive method, and optical transmission system using same |
| CN103427331A (en) * | 2013-08-23 | 2013-12-04 | 西安电子科技大学 | Driver of vertical cavity surface emitting laser |
| CN103457154A (en) * | 2013-08-29 | 2013-12-18 | 烽火通信科技股份有限公司 | Integrated optical communication laser driver with pre-emphasis |
| CN204633746U (en) * | 2015-06-26 | 2015-09-09 | 灿芯半导体(上海)有限公司 | Output circuit in interface circuit |
| CN110896304A (en) * | 2019-09-27 | 2020-03-20 | 厦门优迅高速芯片有限公司 | High-speed amplitude and phase programmable rising edge/falling edge adjustable circuit |
| CN110896327A (en) * | 2019-10-10 | 2020-03-20 | 厦门优迅高速芯片有限公司 | Multi-dimensional signal eye diagram compensation circuit |
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