CN114093311B

CN114093311B - Display device

Info

Publication number: CN114093311B
Application number: CN202111367484.XA
Authority: CN
Inventors: 奚鹏博
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2021-07-12
Filing date: 2021-11-18
Publication date: 2023-10-27
Anticipated expiration: 2041-11-18
Also published as: TW202303559A; CN114093311A; TWI785674B

Abstract

The invention discloses a display, which comprises a plurality of groups of pixel circuits, a plurality of groups of scanning circuits and a plurality of light-emitting control circuits. The first set of pixel circuits includes K pixel circuits. K is an integer greater than one. The first group of scanning circuits generates a first group of scanning signals and transmits each scanning signal of the first group of scanning signals to a corresponding pixel circuit in the first group of pixel circuits. The first light emitting control circuit generates a first light emitting control signal and transmits the first light emitting control signal to each pixel circuit of the first group of pixel circuits. The first group of pixel circuits respectively and sequentially write a data signal into the K pixel circuits according to the K scanning signals of the first group of scanning signals. After the data signal is written into the first group of pixel circuits, K pixel circuits in the first group of pixel circuits emit light simultaneously according to the first light-emitting control signal and the data signal.

Description

Display device

Technical Field

The present invention relates to a display technology, and more particularly, to a display.

Background

When driving the LED panel, the display device is operated according to a Pulse-width modulation (PWM) signal. Operation by PWM signals may cause a large amount of current to accumulate in the display device, the circuit of the driving device requires a complicated design, and a risk of screen flicker (flicker) or the like is easily caused. Therefore, it is an important task in the art to develop a related art capable of overcoming the above-mentioned problems.

Disclosure of Invention

The embodiment of the invention comprises a display. The display comprises a plurality of groups of pixel circuits, a plurality of groups of scanning circuits and a plurality of light-emitting control circuits. The plurality of sets of pixel circuits includes a first set of pixel circuits including K pixel circuits, where K is an integer greater than one. The plurality of sets of scanning circuits comprise a first set of scanning circuits, wherein the first set of scanning circuits are used for generating a first set of scanning signals and transmitting each scanning signal of the first set of scanning signals to a corresponding pixel circuit in the first set of pixel circuits. The plurality of light-emitting control circuits comprise a first light-emitting control circuit, and the first light-emitting control circuit is used for generating a first light-emitting control signal and transmitting the first light-emitting control signal to each pixel circuit in the first group of pixel circuits. The first group of pixel circuits are used for writing a data signal into the K pixel circuits in the first group of pixel circuits according to the K scanning signals in the first group of scanning signals in sequence respectively. After the data signal is written into the first group of pixel circuits, K pixel circuits in the first group of pixel circuits are used for emitting light simultaneously according to the first light emitting control signal and the data signal.

Drawings

Fig. 1 is a schematic diagram of a display according to an embodiment of the present disclosure.

FIG. 2 is a block diagram of a display according to an embodiment of the present disclosure.

FIG. 3 is a timing diagram of a pixel circuit according to an embodiment of the invention for performing data writing and light emitting operations.

FIG. 4 is a block diagram of a display according to an embodiment of the present disclosure.

Fig. 5 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

FIG. 6A is a timing diagram of a pixel circuit according to an embodiment of the invention for performing a data writing operation and a light emitting operation.

FIG. 6B is a timing diagram of a group of pixel circuits performing data writing and light emitting operations according to an embodiment of the present invention.

Fig. 7 is a circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

FIG. 8A is a timing diagram of a pixel circuit according to an embodiment of the invention for performing a data writing operation and a light emitting operation.

FIG. 8B is a timing diagram of a group of pixel circuits performing data writing and light emitting operations according to an embodiment of the present invention.

Wherein, the reference numerals:

100. 200, 400 display

110. 210, 410 display device

120. 220, 420 scanner

130 data input device

140. 240, 440 lighting control device

Scan lines SL (0) -SL (n)

SS (1) to SS (52), G1 (n) to G4 (n), G1 (n+1) to G4 (n+1), G1 (n+2) to G4 (n+2), G1 (n+3) to G4 (n+3) scan signals

DL (1) -DL (m) data line

DTW (m), DTA (m) data signal

EL (1) -EL (Q) luminous line

SCLK1, SCLK2, SCLK3, scanning clock signal

SSTV scanning start signal

ECLK1, ECLK2, light-emitting clock signal

INA1, INA2, INB1, INB2: select signal

ESTV light-emitting Start Signal

ES (1) -ES (13), GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) light emission control signals

DV 1-DV 12 drive signals

PPO, clamping signal

SG (1) -SG (52) scanning circuit

PX (1) -PX (52), 500, 700 pixel circuit

EG (1) -EG (13) luminous control circuit

L5, L7 light-emitting element

VSS, VDD, RES, HDC, LDC Voltage signal

300. 601, 602, 801, 802 timing diagram

P31 to P316, P61 to P66, R61 to R66, P81 to P88, R81 to R88, period

T32 time interval

C51 to C53, C71 and C72, capacitance

T51-T517, T71-T714 switch

N51-N59, N71-N76: nodes

VEN, VDA voltage level

Detailed Description

The invention will now be described in more detail with reference to the drawings and specific examples, which are not intended to limit the invention thereto.

Herein, when an element is referred to as being "connected" or "coupled," it can be referred to as being "electrically connected" or "electrically coupled. "connected" or "coupled" may also mean that two or more elements co-operate or interact with each other. Furthermore, although the terms "first," "second," …, etc. may be used herein to describe various elements, this term is merely intended to distinguish between elements or operations that are described in the same technical term. Unless the context clearly indicates otherwise, the terms are not specifically intended or implied to be order or cis-ient nor intended to limit the invention.

Unless defined otherwise, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well as "at least one" unless the context clearly indicates otherwise. "or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.

Various embodiments of the present invention are disclosed in the following figures, and for the purposes of explanation, numerous practical details are set forth in the following description. However, it should be understood that these practical details are not to be construed as limiting the present disclosure. That is, in some embodiments of the present disclosure, these practical details are unnecessary. Moreover, for the purpose of simplifying the drawings, some conventional structures and elements are shown in the drawings in a simplified schematic manner.

Fig. 1 is a schematic diagram of a display 100 according to an embodiment of the disclosure. Referring to fig. 1, the display 100 includes a display device 110, a scanning device 120, a data input device 130 and a light emitting control device 140. In some embodiments, the display 100 may be made of a glass substrate or a plastic substrate, but is not limited thereto.

In some embodiments, the scanning device 120 provides scanning signals, such as the scanning signals G1 (n) to G4 (n) shown in fig. 6A and 8A, to the display device 110 via the scanning lines SL (0) to SL (n). The data input device 130 provides data signals, such as the data signals DTW (m) and DTA (m) shown in fig. 5 and 7, to the display device 110 via the data lines DL (1) to DL (m). Wherein n and m are positive integers. The light emission control device 140 provides light emission control signals, such as the light emission control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), and SW (Q) shown in fig. 6A and 8A, to the display device 110 via the light emission lines EL (1) to EL (Q). Wherein Q is a positive integer.

In some embodiments, the scanning device 120, the data input device 130 and the light-emitting control device 140 are further configured to provide other signals, such as the voltage signal RES and the pinch off (PPO) signal PPO, to the display device 110, but the embodiment of the invention is not limited thereto. In various embodiments, it is within the contemplation of the present invention to provide the voltage signal RES and the clamp signal PPO to the display device 110.

In some embodiments, the scan device 120 is implemented as a scan shift register and is used for signal reset, data writing, and threshold voltage compensation functions. In some embodiments, the light emission control device 140 is implemented as a pulse width modulation (Pulse Width Modulation, PWM) shift register and is used to generate ramp and square wave signals for PWM light emission operations, such as the light emission control signals EM1 (n) and SW (n) shown in fig. 6A and 8A.

Fig. 2 is a block diagram of a display 200 according to an embodiment of the present disclosure. Display 200 is one embodiment of display 100 shown in fig. 1.

As shown in fig. 2, the display 200 includes a display device 210, a scanning device 220, and a light emission control device 240. The display device 210, the scanning device 220, and the light emission control device 240 are one embodiment of the display device 110, the scanning device 120, and the light emission control device 140 shown in fig. 1, respectively.

As shown in fig. 2, the scanning device 220 is configured to generate scanning signals SS (1) to SS (8) according to the scanning clock signals SCLK1, SCLK2 and SCLK3 and the scanning start signal SSTV, and transmit the scanning signals SS (1) to SS (8) to the display device 210. The light-emitting control device 240 is used for generating light-emitting control signals ES (1) and ES (2) according to the light-emitting clock signals ECLK1, ECLK2, the selection signals INA1, INA2, INB1, INB2 and the light-emitting start signal ESTV, and transmitting the light-emitting control signals ES (1) and ES (2) to the display device 210. The display device 210 is used for performing data writing operation and light emitting operation according to the scan signals SS (1) to SS (8) and the light emitting control signals ES (1) and ES (2). In some embodiments, the selection signals INA1, INA2, INB1, INB2 are selection analog signals.

As shown in fig. 2, the display device 210 includes a plurality of stages of pixel circuits PX (1) to PX (8), the scanning device 220 includes a plurality of stages of scanning circuits SG (1) to SG (8), and the light emission control device 240 includes a plurality of stages of light emission control circuits EG (1) and EG (2).

In the embodiment shown in fig. 2, the scan start signal SSTV is sequentially transferred in the scan circuits SG (1) to SG (8), and the light emission start signal SSTV is sequentially transferred in the light emission control circuits EG (1) and EG (2). The scan circuits SG (1), SG (4) and SG (7) are used for receiving the scan clock signal SCLK1, the scan circuits SG (2), SG (5) and SG (8) are used for receiving the scan clock signal SCLK2, and the scan circuits SG (3) and SG (6) are used for receiving the scan clock signal SCLK3. The light-emitting control circuit EG (1) is used for receiving light-emitting clock signals ECLK1 and ECLK2 and selection signals INA1 and INB1. The light-emitting control circuit EG (2) is used for receiving light-emitting clock signals ECLK1 and ECLK2 and selection signals INA2 and INB2. In different embodiments, the scanning circuit and the light-emitting control circuit may have different signal configuration relationships.

As shown in fig. 2, the scan circuits SG (1) to SG (8) are respectively used for generating scan signals SS (1) to SS (8). The light emission control circuits EG (1) and EG (2) are respectively used for generating light emission control signals ES (1) and ES (2). The pixel circuits PX (1) to PX (8) are respectively configured to receive the scanning signals SS (1) to SS (8). The pixel circuits PX (1) to PX (4) are configured to receive the emission control signal ES (1), and the pixel circuits PX (5) to PX (8) are configured to receive the emission control signal ES (2).

In some embodiments, each of the pixel circuits PX (1) to PX (8) corresponds to a column of pixel circuits in the display device 210, and the operation of other pixel circuits on the column of pixel circuits is similar to the operation of the corresponding one of the pixel circuits PX (1) to PX (8), and thus will not be repeated herein.

In some embodiments, the pixel circuits PX (1) to PX (4) corresponding to the light emission control signal ES (1) are referred to as a first group of pixel circuits, the scanning circuits SG (1) to SG (4) corresponding to the first group of pixel circuits are referred to as a first group of scanning circuits, and the scanning signals SS (1) to SS (4) generated by the scanning circuits SG (1) to SG (4) are referred to as a first group of scanning signals. Similarly, the pixel circuits PX (5) to PX (8) corresponding to the light emission control signal ES (2) are referred to as a second group of pixel circuits, the scanning circuits SG (5) to SG (8) corresponding to the second group of pixel circuits are referred to as a second group of scanning circuits, and the scanning signals SS (5) to SS (8) generated by the scanning circuits SG (5) to SG (8) are referred to as a second group of scanning signals.

In the embodiment corresponding to fig. 2, the display 200 includes two sets of pixel circuits and two sets of scan circuits, each set of pixel circuits includes four pixel circuits and each set of scan circuits includes four scan circuits, but the embodiment of the invention is not limited thereto. In different embodiments, the display 200 may include different numbers of sets of pixel circuits and sets of scan circuits and corresponding light emission control circuits, one set of pixel circuits may include different numbers of pixel circuits, and one set of pixel circuits may include different numbers of scan circuits.

For example, the pixel circuit 200 includes L light emission control circuits, L sets of pixel circuits, and L sets of scan circuits, wherein each set of pixel circuits includes K pixel circuits, and each set of scan circuits includes K scan circuits. Each of the L light emission control circuits corresponds to K pixel circuits and K scanning circuits. Wherein L is a positive integer and K is an integer greater than one.

In some prior approaches, a row of pixel circuits in a display corresponds to a scanning circuit and a light emission control circuit. The pixel circuit performs data writing operation and light emitting operation according to the scanning signal generated by the scanning circuit and the light emitting control signal generated by the light emitting control circuit. In the above-mentioned method, the requirements of the scan signal and the light-emitting control signal may be in conflict in time sequence.

In comparison with the above, in the embodiment of the invention, the K pixel circuits PX (1) to PX (K) are configured to operate according to the scan signals SS (1) to SS (K) generated by the scan circuits SG (1) to SG (K) and the light emission control signal ES (1) generated by the light emission control circuit EG (1). The number ratio of the scanning circuit and the light-emitting control circuit can be adjusted to enable the scanning signal and the light-emitting control signal to meet the time sequence requirement. Further details are described below.

Fig. 3 is a timing diagram 300 illustrating a pixel circuit 200 performing a data writing operation and a light emitting operation according to an embodiment of the present invention. As shown in fig. 3, the horizontal axis of the timing diagram 300 corresponds to time. The timing chart 300 includes periods P31 to P316 that are sequentially and consecutively arranged. In some embodiments, the timing diagram 300 corresponds to the operation of the pixel circuits PX (1) -PX (12) during periods P31-P316. In some embodiments, the time lengths of periods P31-P315 are the same as each other.

Referring to fig. 3 and 2, in the embodiment shown in fig. 3, during a period P31, the pixel circuit PX (1) is configured to perform a reset operation corresponding to the PWM data writing according to the scan signal SS (1). In the period P32, the pixel circuit PX (1) is configured to perform PWM data writing operation according to the scan signal SS (1). In the period P34, the pixel circuit PX (1) performs a reset operation corresponding to the pulse amplitude modulation (Pulse Amplitude Modulation, PAM) data writing according to the scan signal SS (1). In the period P34, the pixel circuit PX (1) is configured to perform PAM data writing operation according to the scan signal SS (1). As described above, when the period P34 ends, the pixel circuit PX (1) is ready to start light emission after the PWM data signal and the PAM data signal are written.

Similarly, in the period P32, the pixel circuit PX (2) is configured to perform a reset operation corresponding to the PWM data writing according to the scan signal SS (2). In the period P33, the pixel circuit PX (2) is configured to perform PWM data writing operation according to the scan signal SS (2). In the period P34, the pixel circuit PX (2) is configured to perform a reset operation corresponding to the PAM data writing according to the scan signal SS (2). In the period P35, the pixel circuit PX (2) is configured to perform PAM data writing operation according to the scan signal SS (2). As described above, when the period P35 ends, the pixel circuit PX (2) is ready to start light emission after the PWM data signal and the PAM data signal are written.

Similarly, for the positive integer i, during the period P3i, the pixel circuit PX (i) is configured to perform the reset operation corresponding to the PWM data writing according to the scan signal SS (i). In the period P3 (i+1), the pixel circuit PX (i) is configured to perform PWM data writing operation according to the scan signal SS (i). In the period P3 (i+2), the pixel circuit PX (i) is configured to perform a reset operation corresponding to the PAM data writing according to the scan signal SS (i). In the period P3 (i+3), the pixel circuit PX (i) is configured to perform PAM data writing operation according to the scan signal SS (i). At the end of the period P3 (i+3), the pixel circuit PX (i) is ready to start light emission after the PWM data signal and the PAM data signal are written.

In other words, as shown in fig. 3, in the periods P31 to P315, the pixel circuits PX (1) to PX (12) sequentially perform the data writing operation, wherein the i-th pixel circuit PX (i) starts the data writing operation according to the i-th scanning signal SS (i) and the i+1th pixel circuit PX (i+1) starts the data writing operation according to the i+1th scanning signal SS (i+1) with a time interval T31 therebetween. In some embodiments, the length of the time interval T31 is the time length of the period P1.

Referring to fig. 3 and 2, in the embodiment shown in fig. 3, during the period P38, the pixel circuits PX (1) to PX (4) are simultaneously used for performing the light emitting operation according to the light emitting control signal ES (1) generated by the light emitting control circuit EG (1). In other words, the pixel circuits PX (1) to PX (4) sequentially write the data signals in the periods P31 to P37, and then simultaneously perform the light emission operation in the period P38.

In some embodiments, the light emitting time length of the pixel circuits PX (1) to PX (4) is determined by the corresponding PWM data signals, and the pixel circuits PX (1) to PX (4) may have different light emitting time lengths. For example, in the embodiment shown in fig. 3, the pixel circuit PX (1) emits light in the periods P38 to P313, the pixel circuit PX (2) emits light in the periods P38 to P311, the pixel circuit PX (3) emits light in the periods P38 to P314, and the pixel circuit PX (4) emits light in the periods P38 to P39.

Similarly, in the embodiment shown in fig. 3, during the period P312, the pixel circuits PX (5) to PX (8) are simultaneously configured to perform the light emitting operation according to the light emission control signal ES (2) generated by the light emission control circuit EG (2). In other words, the pixel circuits PX (5) to PX (8) sequentially write the data signals in the periods P35 to P311, and then simultaneously perform the light emission operation in the period P312.

Similarly, in the embodiment shown in fig. 3, during the period P316, the pixel circuits PX (9) to PX (12) are simultaneously configured to perform the light emitting operation according to the light emission control signal ES (3) generated by the light emission control circuit EG (3). In other words, the pixel circuits PX (9) to PX (12) sequentially write the data signals in the periods P39 to P315, and then simultaneously perform the light emission operation in the period P316.

In the embodiment shown in fig. 3, a first group of pixel circuits including the pixel circuits PX (1) to PX (4), a second group of pixel circuits including the pixel circuits PX (5) to PX (8), and a third group of pixel circuits including the pixel circuits PX (9) to PX (12) sequentially emit light.

In the embodiment shown in fig. 3, each group of pixel circuits contains four pixel circuits. Correspondingly, the time interval 4×t31 is provided between the time when the i-th group pixel circuit starts to emit light and the time when the i+1th group pixel circuit starts to emit light. For example, the first set of pixel circuits emits light from the period P38, and the second set of pixel circuits emits light from the period P312, wherein the period P38 and the period P312 have a time interval of 4×t31 therebetween.

In some other embodiments, each set of pixel circuits includes K pixel circuits. Correspondingly, a time interval k×t31 is provided between the time at which the i-th group pixel circuit starts to emit light and the time at which the i+1th group pixel circuit starts to emit light.

As shown in fig. 3, the maximum possible light emission time of each light emitting circuit in the first group of pixel circuits is denoted by a time interval T32. The time interval T32 is not drawn to scale. Various lengths of the time interval T32 are within the scope of the present disclosure.

Fig. 4 is a block diagram of a display 400 according to an embodiment of the present disclosure. Display 400 is one embodiment of display 100 shown in fig. 1. Display 400 is a variation of display 200 shown in fig. 2.

As shown in fig. 4, the display 400 includes a display device 410, a scanning device 420, and a light emission control device 440. The display device 410, the scanning device 420 and the light emission control device 440 are one embodiment of the display device 110, the scanning device 120 and the light emission control device 140 shown in fig. 1, respectively.

As shown in fig. 4, the display device 410 includes a plurality of stages of pixel circuits PX (1) to PX (52), the scanning device 420 includes a plurality of stages of scanning circuits SG (1) to SG (52), and the light emission control device 440 includes a plurality of stages of light emission control circuits EG (1) to EG (13). The operation and configuration of the display device 410, the scanning device 420, and the light emission control device 440 are similar to those of the display device 210, the scanning device 220, and the light emission control device 240 shown in fig. 2, and thus, a detailed description thereof will not be repeated. For example, the operations of the pixel circuits PX (49) to PX (52) and the scan circuits SG (49) to SG (52) corresponding to the light emission control circuit EG (13) are similar to the operations of the pixel circuits PX (1) to PX (4) and the scan circuits SG (1) to SG (4) corresponding to the light emission control circuit EG (1) shown in fig. 2.

As shown in fig. 4, the light emission control circuits EG (1) to EG (12) are respectively configured to receive the driving signals DV1 to DV12. In some embodiments, the light-emitting control circuits EG (1) -EG (12) are used for generating corresponding light-emitting control signals ES (1) -ES (12) according to the driving signals DV 1-DV 12.

As shown in fig. 4, the light emission control circuit EG (13) is configured to receive the driving signal DV1 to generate the light emission control signal ES (13). In some embodiments, the light emission control circuits EG (14) -EG (24) are respectively used for receiving the driving signals DV 2-DV 12 to generate corresponding light emission control signals.

In the embodiment corresponding to fig. 4, the light-emitting control device 440 is configured to receive twelve driving signals DV 1-DV 12, but the embodiment of the invention is not limited thereto. In various embodiments, the lighting control device 440 is configured to receive various numbers of driving signals.

In some embodiments, the multi-stage light-emitting control circuit in the light-emitting control device 440 is configured to receive P driving signals, and the kth×p+j light-emitting control circuit is configured to receive the jth driving signal of the P driving signals to generate a corresponding light-emitting control signal, where k is a non-negative integer, and j is an integer greater than zero and less than or equal to P.

Referring to fig. 4 and 3, in some embodiments, the display 400 operates with the timing shown in fig. 3. For example, the pixel circuits PX (1) to PX (52) sequentially perform data writing operations, and the first group of pixel circuits to thirteenth group of pixel circuits corresponding to the light emission control circuits EG (1) to EG (13) sequentially perform light emission operations. In the above-described embodiment, the maximum possible light emission time of the first group of pixel circuits has the time interval t32=12×k×t31. In the embodiment having P driving signals, the maximum possible light emission time has a time interval t32=p×k×t31.

Fig. 5 is a circuit diagram of a pixel circuit 500 according to an embodiment of the disclosure. The pixel circuit 500 is an embodiment of the pixel circuit PX (n) shown in fig. 2, where n is a positive integer. In some embodiments, the pixel circuit 500 is a progressive PWM drive circuit.

As shown in fig. 5, the pixel circuit 500 includes switches T51 to T517, capacitors C51 to C53, and a light emitting element L5. In some embodiments, the pixel circuit 500 is configured to receive the scan signals G1 (n) and G2 (n), the data signals DTW (m), DTA (m), and the light emission control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) for performing the light emission operation, wherein m and Q are positive integers. Referring to fig. 2, the scan signals G1 (n) and G2 (n) are embodiments of the scan signal SS (n), and the emission control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) are embodiments of the emission control signal ES (Q). In some embodiments, the emission control signal EM1 (Q) corresponds to a square wave signal of the PWM emission operation, and the emission control signal SW (Q) corresponds to a ramp wave signal of the PWM emission operation.

In some embodiments, the pixel circuit 500 corresponds to the nth pixel circuit PX (n), and is configured to perform data writing and light emitting operations according to the scan signals G1 (n), G2 (n) generated by the nth scan circuit SG (n) and the light emitting control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) generated by the qth light emitting control circuit EG (Q). The Q-th light emission control circuit EG (Q) corresponds to the Q-th group of pixel circuits including the pixel circuit 500.

As shown in fig. 5, one end of the switch T51 is coupled to the node N51, the other end of the switch T51 is configured to receive the voltage signal HDC, and the control end of the switch T51 is configured to receive the emission control signal EM2 (Q). One end of the switch T52 is coupled to the node N51, the other end of the switch T52 is configured to receive the data signal DTW (m), and the control end of the switch T52 is configured to receive the scan signal G2 (N). One end of the switch T53 is coupled to the node N51, the other end of the switch T53 is coupled to the node N52, and the control end of the switch T53 is coupled to the node N53. One end of the switch T54 is coupled to the node N53, the other end of the switch T54 is coupled to the node N52, and the control end of the switch T54 is configured to receive the scan signal G2 (N). One end of the switch T55 is coupled to the node N53, and the other end and the control end of the switch T55 are configured to receive the scan signal G1 (N). One end of the switch T56 is coupled to the node N54, and the other end and the control end of the switch T56 are configured to receive the scan signal G1 (N). One end of the switch T57 is coupled to the node N55, the other end of the switch T57 is configured to receive the voltage signal VDD, and the control end of the switch T57 is configured to receive the emission control signal EM2 (Q). One end of the switch T58 is coupled to the node N55, the other end of the switch T58 is configured to receive the data signal DTA (m), and the control end of the switch T58 is configured to receive the scan signal G2 (N). One end of the switch T59 is coupled to the node N55, the other end of the switch T59 is coupled to the node N56, and the control end of the switch T59 is coupled to the node N54. One end of the switch T510 is coupled to the node N54, the other end of the switch T510 is coupled to the node N56, and the control end of the switch T510 is configured to receive the scan signal G2 (N). One end of the switch T511 is coupled to the node N57, the other end of the switch T511 is coupled to the node N56, and the control end of the switch T511 is coupled to the node N58. One end of the switch T512 is coupled to the node N57, the other end of the switch T512 is coupled to the light emitting element L5, and the control end of the switch T512 is configured to receive the light emitting control signal EM1 (Q). One end of the switch T513 is coupled to the node N52, the other end of the switch T513 is coupled to the node N58, and the control end of the switch T513 is configured to receive the light emission control signal EM2 (Q). One end of the switch T514 is coupled to the node N52, the other end of the switch T514 is configured to receive the voltage signal LDC, and the control end of the switch T514 is configured to receive the light emission control signal GST (Q). One end of the switch T515 is configured to receive the voltage signal HDC, the other end of the switch T515 is configured to receive the light emission control signal SW (Q), and the control end of the switch T515 is configured to receive the light emission control signal VST (Q). One end of the switch T516 is coupled to the node N59, the other end of the switch T516 is configured to receive the voltage signal HDC, and the control end of the switch T515 is configured to receive the light-emitting control signal VST (Q). One end of the switch T517 is coupled to the node N59, the other end of the switch T517 is configured to receive the voltage signal VDD, and the control end of the switch T517 is configured to receive the emission control signal EM2 (Q). One end of the capacitor C51 is configured to receive the light emission control signal SW (Q), and the other end of the capacitor C51 is coupled to the node N53. One end of the capacitor C52 is coupled to the node N59, and the other end of the capacitor C52 is coupled to the node N54. One end of the capacitor C53 is configured to receive the voltage signal LDC, and the other end of the capacitor C53 is coupled to the node N58. One end of the light emitting element L5 is coupled to the switch T512, and the other end of the light emitting element L5 is configured to receive the voltage signal VSS.

Fig. 6A is a timing diagram 601 of a pixel circuit 500 according to an embodiment of the invention for performing a data writing operation and a light emitting operation. As shown in fig. 6A, the horizontal axis of the timing chart 601 corresponds to time. The timing chart 601 includes periods P61 to P66 arranged in order.

As shown in the timing chart 601, in the period P61, the scan signal G1 (n) and the light-emitting control signal VST (Q) have the enable voltage level VEN, so that the switches T55, T56, T515 and T516 are turned on. At this time, the switches T55 and T56 reset the voltages of the nodes N53 and N54 by the scan signal G1 (N), respectively, and the switch T516 resets the voltage of the node N59 by the voltage signal HDC. Switches T53 and T59 are turned on according to the voltages of nodes N53 and N54, respectively. In some embodiments, the pixel circuit 500 resets the node voltage during the period P61 corresponding to a subsequent data write operation, and thus the period P61 is referred to as a data reset period.

As shown in the timing chart 601, in the period P62, the scan signal G2 (n) and the light-emitting control signal VST (Q) have the enable voltage level VEN, so that the switches T52, T54, T58, T510, T515 and T516 are turned on. At this time, the data signal DTW (m) is sequentially written into the node N53 via the switches T52, T53 and T54, and the data signal DTA (m) is sequentially written into the node N54 via the switches T58, T59 and T510. The capacitors C51 and C52 are used for storing the data signals DTW (m) and DTA (m), respectively. In some embodiments, the pixel circuit 500 writes the data signals DTW (m) and DTA (m) in the period P62, so the period P62 is referred to as a data writing period.

As shown in the timing diagram 601, in the period P63, the light-emitting control signals GST (Q) and VST (Q) have the enable voltage level VEN, so that the switches T514, T515 and T516 are turned on. At this time, the voltage signal LDC is written into the node N52 via the switch T514, so that the voltage of the node N52 is reset according to the voltage signal LDC. In some embodiments, the pixel circuit 500 resets the node voltage at the period P63 corresponding to the subsequent light emitting operation, and thus the period P63 is referred to as a light emitting reset period.

As shown in the timing diagram 601, during the period P64, the light emission control signals EM1 (Q) and EM2 (Q) have the enable voltage level VEN, so that the switches T51, T57, T517, T513 and T512 are turned on. At this time, the voltage signal VDD is written into the nodes N59 and N55 through the switches T517 and T57, respectively, and the voltage signal HDC is written into the node N51 through the switch T51.

In the period P64, the light emission control signal SW (Q) is a ramp signal gradually decreasing from the voltage level VDA to the voltage level VEN. The light emitting control signal SW (Q) is used to adjust the voltage of the node N53 via the capacitor C51 to further adjust the voltage of the node N52. The voltage of the node N58 is regulated by the switch T513 through the voltage of the node N52, so that the switch T511 is turned on according to the voltage of the node N58. The light-emitting element L5 emits light according to the current passing through the switch T511. In some embodiments, the pixel circuit 500 performs a light emitting operation in the period P64, and thus the period P64 is referred to as a light emitting period.

As shown in the timing diagram 601, in the period P65, the light-emitting control signals GST (Q) and VST (Q) have the enable voltage level VEN, so that the switches T514, T515 and T516 are turned on. In the period P66, the light emission control signals EM1 (Q) and EM2 (Q) have the enable voltage level VEN, so that the switches T51, T57, T517, T513 and T512 are turned on.

In the period P65, the pixel circuit 500 performs the light emission reset operation again. In the period P66, the pixel circuit 500 performs the light emitting operation again. In some embodiments, the operation of periods P65 and P66 is similar to the operation of periods P63 and P64, so some details are not repeated. In some embodiments, the pixel circuit 500 may repeat the light-emitting reset operation and the light-emitting operation a plurality of times in a Frame time (Frame time). In some other embodiments, the pixel circuit 500 may perform a light-emitting reset operation and a plurality of light-emitting operations in a Frame time (Frame time).

FIG. 6B is a timing diagram 602 of a group of pixel circuits performing data writing and light emitting operations according to an embodiment of the present invention. As shown in fig. 6B, the horizontal axis of the timing diagram 602 corresponds to time. The timing chart 602 includes periods R61 to R66 arranged in order.

Referring to fig. 2, 5, 6A and 6B, in some embodiments, the configuration of each of the pixel circuits PX (1) -PX (8) is similar to the configuration of the pixel circuit 500. The pixel circuit PX (n) is configured to receive the scan signals G1 (n) and G2 (n). Correspondingly, the pixel circuit PX (n+1) is configured to receive the scan signals G1 (n+1) and G2 (n+1) in a similar configuration, the pixel circuit PX (n+2) is configured to receive the scan signals G1 (n+2) and G2 (n+2) in a similar configuration, and the pixel circuit PX (n+3) is configured to receive the scan signals G1 (n+3) and G2 (n+3) in a similar configuration.

Referring to fig. 2, 6A and 6B, the operation of the pixel circuit PX (n) in the periods R61 and R62 is similar to the operation of the pixel circuit PX (n) in the periods P61 and P62, respectively, and the operation of the pixel circuit PX (n) in the period R66 is similar to the operation of the pixel circuits in the periods P63 to P64. Therefore, some details will not be repeated.

In some embodiments, the pixel circuit PX (n) is configured to perform a data writing operation according to the scan signals G1 (n) and G2 (n) in the periods R61 and R62, and perform a light emitting operation according to the light emitting control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) in the period R66.

In some embodiments, the pixel circuit PX (n+1) is configured to perform a data writing operation according to the scan signals G1 (n+1) and G2 (n+1) during the periods R62 and R63, and perform a light emitting operation according to the light emitting control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) during the period R66.

In some embodiments, the pixel circuit PX (n+2) is configured to perform a data writing operation according to the scan signals G1 (n+2) and G2 (n+2) during the periods R63 and R64, and perform a light emitting operation according to the light emitting control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) during the period R66.

In some embodiments, the pixel circuit PX (n+3) is configured to perform a data writing operation according to the scan signals G1 (n+3) and G2 (n+3) during the periods R64 and R65, and perform a light emitting operation according to the light emitting control signals GST (Q), EM1 (Q), EM2 (Q), VST (Q), SW (Q) during the period R66.

As described above, the pixel circuits PX (n) to PX (n+3) sequentially perform data writing operations in the periods R61 to R65, and simultaneously perform light emitting operations in the period R66. Referring to fig. 3 and 6B, in some embodiments, the periods R61 to R65 correspond to the periods P31 to P37, and the period R66 corresponds to the periods P38 to P315.

Fig. 7 is a circuit diagram of a pixel circuit 700 according to an embodiment of the disclosure. The pixel circuit 700 is an embodiment of the pixel circuit PX (n) shown in fig. 2. In some embodiments, the pixel circuit 700 is a progressive PWM drive circuit.

As shown in fig. 7, the pixel circuit 700 includes switches T71 to T714, capacitors C71, C72, and a light emitting element L7. In some embodiments, the pixel circuit 700 is configured to receive the scan signals G1 (n) -G4 (n), the data signals DTW (m), DTA (m), and the light emission control signals EM1 (Q), EM2 (Q), VST (Q), SW (Q) for performing the light emission operation, wherein m and Q are positive integers. Referring to fig. 2, the scan signals G1 (n) to G4 (n) are embodiments of the scan signal SS (n), and the emission control signals EM1 (Q), EM2 (Q), VST (Q), SW (Q) are embodiments of the emission control signal ES (Q). In some embodiments, the emission control signal EM1 (Q) corresponds to a square wave signal of the PWM emission operation, and the emission control signal SW (Q) corresponds to a ramp wave signal of the PWM emission operation.

In some embodiments, the pixel circuit 700 corresponds to the nth pixel circuit PX (n), and is configured to perform data writing and light emitting operations according to the scan signals G1 (n) -G4 (n) generated by the nth scan circuit SG (n) and the light emitting control signals EM1 (Q), EM2 (Q), VST (Q), SW (Q) generated by the qth light emitting control circuit EG (Q). The Q-th light emission control circuit EG (Q) corresponds to the Q-th group of pixel circuits including the pixel circuit 700.

As shown in fig. 7, one end of the switch T71 is coupled to the node N71, the other end of the switch T71 is configured to receive the voltage signal RES, and the control end of the switch T71 is configured to receive the scan signal G1 (N). One end of the switch T72 is coupled to the node N71, the other end of the switch T72 is coupled to the node N72, and the control end of the switch T72 is configured to receive the scan signal G2 (N). One end of the switch T73 is coupled to the node N73, the other end of the switch T73 is coupled to the node N72, and the control end of the switch T73 is coupled to the node N71. One end of the switch T74 is coupled to the node N74, the other end of the switch T74 is configured to receive the data signal DTA (m), and the control end of the switch T74 is configured to receive the scan signal G4 (N). One end of the switch T75 is coupled to the node N72, the other end of the switch T75 is coupled to the node N75, and the control end of the switch T75 is configured to receive the scan signal G4 (N). One end of the switch T76 is coupled to the node N74, the other end of the switch T76 is configured to receive the voltage signal VDD, and the control end of the switch T76 is configured to receive the emission control signal EM1 (Q). One end of the switch T77 is coupled to the node N74, the other end of the switch T77 is coupled to the node N75, and the control end of the switch T77 is coupled to the node N72. One end of the switch T78 is coupled to the node N75, the other end of the switch T78 is coupled to the light emitting element L7, and the control end of the switch T78 is configured to receive the light emitting control signal EM2 (Q). One end of the switch T79 is coupled to the node N73, the other end of the switch T79 is configured to receive the clamping signal PPO, and the control end of the switch T79 is configured to receive the light emitting control signal EM2 (Q). One end of the switch T710 is coupled to the node N73, the other end of the switch T710 is configured to receive the data signal DTW (m), and the control end of the switch T710 is configured to receive the scan signal G2 (N). One end of the switch T711 is configured to receive the blocking signal PPO, the other end of the switch T711 is configured to receive the light emission control signal SW (Q), and the control end of the switch T711 is configured to receive the light emission control signal VST (Q). One end of the switch T712 is coupled to the node N72, the other end of the switch T712 is configured to receive the voltage signal RES, and the control end of the switch T712 is configured to receive the scan signal G3 (N). One end of the switch T713 is coupled to the node N76, the other end of the switch T713 is configured to receive the clamping signal PPO, and the control end of the switch T713 is configured to receive the light-emitting control signal VST (Q). One end of the switch T714 is coupled to the node N76, the other end of the switch T714 is configured to receive the voltage signal VDD, and the control end of the switch T714 is configured to receive the emission control signal EM2 (Q). One end of the capacitor C71 is configured to receive the light emission control signal SW (Q), and the other end of the capacitor C71 is coupled to the node N71. One end of the capacitor C72 is coupled to the node N72, and the other end of the capacitor C72 is coupled to the node N76. One end of the light emitting element L7 is coupled to the switch T78, and the other end of the light emitting element L7 is configured to receive the voltage signal VSS.

Fig. 8A is a timing diagram 801 illustrating a data writing operation and a light emitting operation of the pixel circuit 700 according to an embodiment of the invention. As shown in fig. 8A, the horizontal axis of the timing chart 801 corresponds to time. The timing chart 801 includes periods P81 to P88 arranged in order.

As shown in the timing chart 801, in the period P81, the scan signal G1 (n) and the light emission control signal VST (Q) have the enable voltage level VEN, so that the switches T71, T711 and T713 are turned on. At this time, the switch T71 resets the voltage of the node N71 by the voltage signal RES, and the clamp signal PPO is written into the nodes N77 and N76 through the switches T711 and T713, respectively. In some embodiments, the pixel circuit 700 resets the node voltage during the period P81 corresponding to a subsequent PWM data write operation, so the period P81 is referred to as a PWM data reset period.

As shown in the timing chart 801, in the period P82, the scan signal G2 (n) and the light-emitting control signal VST (Q) have the enable voltage level VEN, so that the switches T72, T710, T711 and T713 are turned on. At this time, the data signal DTW (m) is written into the node N71 via the switches T710, T73 and T72 in sequence. The capacitor C71 is used for storing the data signal DTW (m). In some embodiments, the data signal DTW (m) is a PWM data signal. In some embodiments, the pixel circuit 700 writes the data signal DTW (m) during the period P82, and thus the period P82 is referred to as a PWM data writing period.

As shown in the timing chart 801, the scan signal G3 (n) and the light emission control signal VST (Q) have the enable voltage level VEN during the period P83, so that the switches T712, T711 and T713 are turned on. At this time, the switch T712 resets the voltage of the node N72 by the voltage signal RES, and the clamp signal PPO is written into the nodes N77 and N76 through the switches T711 and T713, respectively. In some embodiments, the pixel circuit 700 resets the node voltage during the period P83 corresponding to a subsequent PAM data write operation, and thus the period P83 is referred to as a PAM data reset period.

As shown in the timing chart 801, during the period P84, the scan signal G4 (n) and the light-emitting control signal VST (Q) have the enable voltage level VEN, so that the switches T74, T75, T711 and T713 are turned on. At this time, the data signal DTA (m) is written into the node N72 via the switches T74, T77 and T75 in sequence. The capacitor C72 is used for storing the data signal DTA (m). In some embodiments, the data signal DTA (m) is a PAM data signal. In some embodiments, the pixel circuit 700 is in the write data signal DTA (m) of the period P84, and thus the period P84 is referred to as PAM data write period.

As shown in the timing chart 801, in the period P85, the light emitting control signals EM1 (Q) and EM2 (Q) have the enable voltage level VEN, so that the switches T79, T78, T76 and T714 are turned on. At this time, the voltage signal VDD is written into the nodes N74 and N76 via the switches T76 and T714, respectively, and the clamp signal PPO is written into the node N73 via the switch T79.

In the period P85, the light emission control signal SW (Q) is a ramp signal gradually decreasing from the voltage level VDA to the voltage level VEN. The light emitting control signal SW (Q) is used to adjust the voltage of the node N71 via the capacitor C71 to further adjust the voltage of the node N72. The switch T73 adjusts the voltage of the node N72 according to the voltage of the node N71, so that the switch T77 is turned on according to the voltage of the node N72. The light-emitting element L7 emits light according to the current passing through the switch T77. In some embodiments, the pixel circuit 700 performs a light emitting operation in the period P85, and thus the period P85 is referred to as a light emitting period.

As shown in the timing chart 801, in the period P86, the scan signal G3 (n) and the light-emitting control signal VST (Q) have the enable voltage level VEN, so that the switches T712, T711 and T713 are turned on. In the period P87, the scan signal G4 (n) and the light-emitting control signal VST (Q) have the enable voltage level VEN, so that the switches T74, T75, T711 and T713 are turned on. In the period P85, the light emission control signals EM1 (Q) and EM2 (Q) have the enable voltage level VEN, so that the switches T79, T78, T76 and T714 are turned on.

In the periods P86 to P87, the pixel circuit 700 again writes the PAM data signal. In the period P88, the pixel circuit 700 performs the light emitting operation again. In some embodiments, the operation of periods P86, P87, and P88 is similar to the operation of periods P83, P84, and P85, so some details are not repeated. In some embodiments, the pixel circuit 700 may repeat PAM data writing operation and light emitting operation a plurality of times in a Frame time (Frame time). In some other embodiments, the pixel circuit 700 may perform one PAM data write operation and multiple light emitting operations in a Frame time (Frame time).

FIG. 8B is a timing diagram 802 illustrating a data write operation and a light emitting operation of a group of pixel circuits according to an embodiment of the invention. As shown in fig. 8B, the horizontal axis of the timing diagram 802 corresponds to time. The timing chart 802 includes periods R81 to R88 arranged in order.

Referring to fig. 2, 7, 8A and 8B, in some embodiments, the configuration of each of the pixel circuits PX (1) -PX (8) is similar to the configuration of the pixel circuit 700. The pixel circuit PX (n) is configured to receive the scan signals G1 (n) to G4 (n). Correspondingly, the pixel circuit PX (n+1) is configured to receive the scan signals G1 (n+1) to G4 (n+1) in a similar configuration, the pixel circuit PX (n+2) is configured to receive the scan signals G1 (n+2) to G4 (n+2) in a similar configuration, and the pixel circuit PX (n+3) is configured to receive the scan signals G1 (n+3) to G4 (n+3) in a similar configuration.

Referring to fig. 2, 8A and 8B, the operation of the pixel circuit PX (n) in the period R81 to R84 is similar to the operation of the pixel circuit PX (n) in the period P81 to P84, respectively, and the operation of the pixel circuit PX (n) in the period R88 is similar to the operation of the pixel circuit PX (n) in the period P85. Therefore, some details will not be repeated.

In some embodiments, the pixel circuit PX (n) is configured to perform data writing operation according to the scan signals G1 (n) to G4 (n) in the period R81 to R84, and perform light emitting operation according to the light emitting control signals EM1 (Q), EM2 (Q), VST (Q), SW (Q) in the period R88.

In some embodiments, the pixel circuit PX (n+1) is configured to perform a data writing operation according to the scan signals G1 (n+1) to G4 (n+1) in the period R82 to R85, and perform a light emitting operation according to the light emitting control signals EM1 (Q), EM2 (Q), VST (Q), SW (Q) in the period R88.

In some embodiments, the pixel circuit PX (n+2) is used for performing data writing operation according to the scan signals G1 (n+2) to G4 (n+2) in the period R83 to R86, and performing light emitting operation according to the light emitting control signals EM1 (Q), EM2 (Q), VST (Q), SW (Q) in the period R88.

In some embodiments, the pixel circuit PX (n+3) is used for performing data writing operation according to the scan signals G1 (n+3) to G4 (n+3) in the period R84 to R87, and performing light emitting operation according to the light emitting control signals EM1 (Q), EM2 (Q), VST (Q), SW (Q) in the period R88.

As described above, the pixel circuits PX (n) to PX (n+3) sequentially perform data writing operations in the periods R81 to R87, and simultaneously perform light emitting operations in the period R88. Referring to fig. 3 and 8B, in some embodiments, periods R81 to R87 correspond to periods P31 to P37, and period R88 corresponds to periods P38 to P315.

The various data writing methods and the light emitting operation methods described above are described for illustration, and other various data writing methods and light emitting operation methods are within the scope of the present invention.

In summary, in the embodiment of the invention, the display 200 controls a group of pixel circuits including the pixel circuits PX (1) to PX (K) by one light-emitting control circuit EG (1) and a group of scanning circuits including the scanning circuits SG (1) to SG (K), so that the pixel circuits PX (1) to PX (K) sequentially write data signals according to the scanning signals SS (1) to SS (K) and emit light simultaneously according to the light-emitting control signal ES (1). In this way, the display 200 can meet the timing requirements of various signals.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather is capable of modification and variation without departing from the spirit and scope of the present invention.

Claims

1. A display, comprising:

a plurality of sets of pixel circuits including a first set of pixel circuits including K pixel circuits, where K is an integer greater than one;

the multi-group scanning circuit comprises a first group of scanning circuits, wherein the first group of scanning circuits are used for generating a first group of scanning signals and transmitting each scanning signal of the first group of scanning signals to a corresponding pixel circuit in the first group of pixel circuits;

The plurality of light-emitting control circuits comprise a first light-emitting control circuit which is used for generating a first light-emitting control signal and transmitting the first light-emitting control signal to each pixel circuit in the first group of pixel circuits,

wherein the first group of pixel circuits is used for writing a data signal into the K pixel circuits in the first group of pixel circuits according to the K scanning signals in the first group of scanning signals respectively in sequence, and

after the data signal is written into the first group of pixel circuits, the K pixel circuits in the first group of pixel circuits are used for emitting light simultaneously according to the first light emitting control signal and the data signal;

after the data signal is written into the first group of pixel circuits, the first group of pixel circuits alternately perform at least one reset operation and at least one light emitting operation for resetting at least one node voltage of the first group of pixel circuits according to the first light emitting control signal.

2. The display of claim 1, wherein the display comprises,

the plurality of sets of pixel circuits further includes a second set of pixel circuits, the second set of pixel circuits including K pixel circuits,

a second group of scanning circuits of the plurality of groups of scanning circuits is used for generating a second group of scanning signals and transmitting each scanning signal of the second group of scanning signals to a corresponding pixel circuit of the second group of pixel circuits,

A second light emission control circuit of the light emission control circuits is used for generating a second light emission control signal and transmitting the second light emission control signal to each pixel circuit in the second group of pixel circuits,

the second group of pixel circuits is used for writing the data signals into the K pixel circuits in the second group of pixel circuits according to the K scanning signals in the second group of scanning signals after the data signals are written into the first group of pixel circuits, respectively

After the data signal is written into the second group of pixel circuits, the K pixel circuits in the second group of pixel circuits are used for emitting light according to the second light-emitting control signal and the data signal.

3. The display of claim 2, wherein the display comprises,

a first time interval is provided between the time when a first pixel circuit in the first group of pixel circuits starts to write the data signal and the time when a second pixel circuit in the first group of pixel circuits starts to write the data signal,

the first group of pixel circuits have a second time interval between a time when the first light-emitting control signal starts to emit light and a time when the second group of pixel circuits start to emit light according to the second light-emitting control signal, and

A length of the second time interval is K times a length of the first time interval.

4. The display of claim 3, wherein the display comprises,

the light-emitting control circuits comprise a first light-emitting control circuit, a P-th light-emitting control circuit and a P+1th light-emitting control circuit which sequentially emit light,

the first to the P-th light emission control circuits are respectively used for receiving a first to a P-th driving signals, and the P+1-th light emission control circuit is used for receiving the first driving signals, wherein P is a positive integer, and

the first light emitting control circuit is used for generating the first light emitting control signal according to the first driving signal.

5. The display of claim 4 wherein a maximum possible light emission time of the first set of pixel circuits is P times the second time interval.

6. The display of claim 2, wherein the first set of pixel circuits is configured to emit light according to the first light-emitting control signal and the data signal when the second set of pixel circuits writes the data signal into the second set of pixel circuits according to the second set of scanning signals.

7. The display of claim 1, wherein the first light emission control signal comprises a square wave signal and a ramp wave signal for pwm light emission operation.

8. The display of claim 1, wherein the display comprises,

each group of the plurality of groups of pixel circuits comprises K pixel circuits,

the K pixel circuits of each group of pixel circuits sequentially perform data writing operations, each writing operation having a first time interval therebetween,

the pixel circuits sequentially perform light-emitting operation, each group of pixel circuits has a second time interval between light-emitting operations, and

9. The display of claim 8, wherein the display comprises,

the light-emitting control circuits are divided into P groups of light-emitting control circuits for generating corresponding light-emitting control signals according to the P driving signals, respectively, and

the maximum possible light emitting time of each group of pixel circuits is P times of the second time interval.