CN114091399B - Integrated circuit layout display method, integrated circuit layout display device, electronic equipment, medium and product - Google Patents
Integrated circuit layout display method, integrated circuit layout display device, electronic equipment, medium and product Download PDFInfo
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- CN114091399B CN114091399B CN202210051897.5A CN202210051897A CN114091399B CN 114091399 B CN114091399 B CN 114091399B CN 202210051897 A CN202210051897 A CN 202210051897A CN 114091399 B CN114091399 B CN 114091399B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
Abstract
The application discloses a method and a device for displaying integrated circuit layout, electronic equipment, a medium and a product. The method comprises the following steps: displaying an integrated circuit layout, wherein the integrated circuit layout is provided with a plurality of layer layouts, and the plurality of layer layouts comprise a first layer layout and a second layer layout; the projection of a first element in the first layer layout and a second element in the second layer layout in the direction vertical to the integrated circuit layout are overlapped; and responding to a first operation of a user, displaying a first element and a second element in the integrated circuit layout in a simplified layout display mode, so that the projection of the first element and the projection of the second element in the direction vertical to the integrated circuit layout are not overlapped, and the connection relation of each element in each layer of layer layout displayed in the simplified layout display mode is unchanged. The effect of clearly displaying the elements of different layers with overlapped projections in the direction perpendicular to the integrated circuit layout and the connection relation of the elements in the layer layout of each layer is achieved.
Description
Technical Field
The present application relates to the field of integrated circuits, and in particular, to a method, an apparatus, an electronic device, a medium, and a product for displaying an integrated circuit layout.
Background
When drawing an integrated circuit layout using Electronic Design Automation (EDA) software (e.g., Computer Aided Design (CAD), Computer Aided Manufacturing (CAM), Computer Aided Testing (CAT), and Computer Aided Engineering (CAE)), dimensions of elements in the integrated circuit layout (e.g., line widths of metal lines and sizes of metal holes), etc. are designed according to requirements of processes, physical conditions, etc., so that elements in layers of different layers in the integrated circuit layout may have the same dimensions and the same positions.
In an integrated circuit layout, the same or different types of elements at the same position in each layer layout may overlap in projection in a direction perpendicular to the integrated circuit layout, and the elements in each layer layout are densely distributed, the connection relationship is complicated, and it is difficult to find the real connection relationship.
Disclosure of Invention
An object of the embodiments of the present application is to provide a method, an apparatus, an electronic device, a medium, and a product for displaying an integrated circuit layout, so as to achieve the effects of displaying elements of different layers with overlapping projections in a direction perpendicular to the integrated circuit layout in a non-overlapping manner, and clearly displaying a connection relationship between the elements in the layer layout of each layer.
The technical scheme of the application is as follows:
in a first aspect, a method for displaying an integrated circuit layout is provided, the method comprising:
displaying an integrated circuit layout, wherein the integrated circuit layout is provided with a plurality of layer layouts, and the plurality of layer layouts comprise a first layer layout and a second layer layout; the first element in the first layer layout and the second element in the second layer layout are overlapped in projection in the direction perpendicular to the integrated circuit layout;
and responding to a first operation of a user, displaying the first element and the second element in the integrated circuit layout in a simplified layout display mode so as to enable projections of the first element and the second element in a direction perpendicular to the integrated circuit layout not to be overlapped, wherein the connection relation of each element in each layer of the layout displayed in the simplified layout display mode is the same as that of each element in the integrated circuit layout.
In a second aspect, there is provided an integrated circuit layout display apparatus, the apparatus comprising:
the display module is used for displaying an integrated circuit layout, wherein the integrated circuit layout is provided with a plurality of layer layouts, and the plurality of layer layouts comprise a first layer layout and a second layer layout; the first element in the first layer layout and the second element in the second layer layout are overlapped in projection in the direction perpendicular to the integrated circuit layout;
the display module is further configured to display the first element and the second element in the integrated circuit layout in a simplified layout display manner in response to a first operation of a user, so that projections of the first element and the second element in a direction perpendicular to the integrated circuit layout are not overlapped, and a connection relationship of each element in each layer of layer layout displayed in the simplified layout display manner is the same as a connection relationship of each element in the integrated circuit layout.
In a third aspect, an embodiment of the present application provides an electronic device, which includes a processor, a memory, and a program or an instruction stored in the memory and executable on the processor, where the program or the instruction, when executed by the processor, implements the steps of the integrated circuit layout display method according to any one of the embodiments of the present application.
In a fourth aspect, an embodiment of the present application provides a readable storage medium, where a program or an instruction is stored on the readable storage medium, and the program or the instruction, when executed by a processor, implements the steps of the integrated circuit layout display method according to any of the embodiments of the present application.
In a fifth aspect, an embodiment of the present application provides a computer program product, where instructions in the computer program product, when executed by a processor of an electronic device, enable the electronic device to perform the steps of the integrated circuit layout display method according to any one of the embodiments of the present application.
The technical scheme provided by the embodiment of the application at least has the following beneficial effects:
the integrated circuit layout display method, the integrated circuit layout display device, the electronic equipment, the medium and the product provided by the embodiment of the application have a plurality of layers of layouts, the plurality of layers of layouts comprise a first layer of layouts and a second layer of layouts, through responding to the first operation of a user, a first element in the first layer of layouts and a second element in the second layer of layouts can be displayed in the integrated circuit layout in a simplified layout display mode, so that the first element and the second element which are originally overlapped in a projection direction perpendicular to the integrated circuit layout are not overlapped, the connection relation of each element in each layer of layouts displayed in the simplified layout display mode is the same as that of each element in the integrated circuit layout, and thus the first element and the second element which are originally overlapped and the connection relation of each element in each layer of layers of layouts can be clearly displayed, avoid the element in different layer territories to overlap, cause the confusion.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application and are not to be construed as limiting the application.
Fig. 1 is a flowchart illustrating a method for displaying an integrated circuit layout according to an embodiment of a first aspect of the present application;
FIG. 2 is a schematic diagram of an integrated circuit layout according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a simplified layout display manner according to an embodiment of the present application;
FIG. 4 is a schematic diagram illustrating a process from an integrated circuit layout display mode to a simplified layout display mode according to an embodiment of the present application;
FIG. 5 is a schematic diagram illustrating a process from an integrated circuit layout display mode to a simplified layout display mode according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an integrated circuit layout display device according to an embodiment of a second aspect of the present application;
fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of a third aspect of the present application.
Detailed Description
In order to make the technical solutions of the present application better understood by those of ordinary skill in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are intended to be illustrative only and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.
It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples consistent with certain aspects of the present application, as detailed in the appended claims.
As described in the background section, in an integrated circuit layout, the prior art has a problem that the projections of the same type of elements at the same positions in each layer layout may overlap in a direction perpendicular to the integrated circuit layout, and the elements in each layer layout are densely distributed and have complicated connection relationships, so that it is difficult to see the real connection relationships, and to solve the above problem, embodiments of the present application provide an integrated circuit layout display method, apparatus, electronic device, medium, and product, in which a plurality of layer layouts including a first layer layout and a second layer layout are provided in an integrated circuit layout, and by responding to a first operation by a user, a first element in the first layer layout and a second element in the second layer layout can be displayed in a simplified layout display manner in the integrated circuit layout, so that the first element originally overlapped by projection in the direction perpendicular to the integrated circuit layout does not overlap with the second element, and the connection relation of each element in each layer layout displayed in a simplified layout display mode is the same as that of each element in the integrated circuit layout, so that the originally overlapped first element and second element and the connection relation of each element in each layer layout can be clearly displayed, and the overlapping of elements in different layer layouts and the confusion caused by the overlapping of the elements in different layer layouts are avoided.
The integrated circuit layout display method provided by the embodiment of the present application is described in detail below with reference to the accompanying drawings through specific embodiments and application scenarios thereof.
Fig. 1 is a schematic flow chart of an integrated circuit layout display method provided in an embodiment of the present application, where an execution subject of the integrated circuit layout display method may be EDA software or a server. In the embodiment of the present application, the execution body is not limited.
As shown in fig. 1, the integrated circuit layout display method provided in the embodiment of the present application may include steps 110 to 120.
Step 110, displaying an integrated circuit layout; the integrated circuit layout comprises a plurality of layers of layouts, wherein the plurality of layers of layouts comprise a first layer of layout and a second layer of layout; and the projection of the first element in the first layer layout and the projection of the second element in the second layer layout in the direction vertical to the integrated circuit layout are overlapped.
And 120, responding to a first operation of a user, displaying a first element and a second element in the integrated circuit layout in a simplified layout display mode so as to enable projections of the first element and the second element in a direction perpendicular to the integrated circuit layout not to be overlapped, wherein the connection relation of each element in each layer of layer layout displayed in the simplified layout display mode is the same as that of each element in the integrated circuit layout.
In an embodiment of the application, there is a multilayer layer layout in the integrated circuit layout, the multilayer layer layout comprising a first layer layout and a second layer layout, by responding to a first operation by a user, a first element in the first layer layout and a second element in the second layer layout may be displayed in the integrated circuit layout in a simplified layout display, such that the first element and the second element which were overlapped by the projection in the direction perpendicular to the integrated circuit layout do not overlap, and the connection relationship of each element in the layer layout of each layer displayed in a simplified layout display mode is the same as the connection relationship of each element in the integrated circuit layout, so that the originally overlapped first element and second element can be clearly displayed, and the connection relation of each element of each layer layout avoids the elements in different layer layouts from overlapping to cause disorder.
The integrated circuit layout display method provided by the embodiment of the application is described in detail below.
Firstly, introducing step 110, displaying an integrated circuit layout; the integrated circuit layout comprises a plurality of layers of layouts, wherein the plurality of layers of layouts comprise a first layer of layout and a second layer of layout; and the projection of the first element in the first layer layout and the projection of the second element in the second layer layout in the direction vertical to the integrated circuit layout are overlapped.
Wherein the layer layout may be a hierarchical layout that makes up an integrated circuit layout. That is, the integrated circuit layout is composed of a plurality of layer layouts.
The first layer layout can be any layer layout or several layers of layer layouts in the multilayer layer layout.
The second layer layout can be any layer layout or layers of layer layouts except the first layer layout in the multilayer layer layout.
The first element may be an element in the first layer layout.
The second element may be an element in the second layer layout.
In some embodiments of the present application, the first element and the second element may include at least one of: signal lines, vias, and an element of an integrated circuit device.
In some embodiments of the present application, the signal line may be a line for signal transmission, and may be a metal line in the layer layout, for example.
In some embodiments of the present application, the first element and the second element may be the same type of element or may be different types of elements. For example, the first element and the second element may be both signal lines, or the first element may be a signal line and the second element may be a via.
In some embodiments of the present application, the through hole may be a via hole in the layer layout, for example, may be a metal hole in the layer layout.
In some embodiments of the present application, the integrated circuit components may be components in an integrated circuit, such as but not limited to resistive elements, capacitive elements, and the like.
In some embodiments of the present application, in the integrated circuit layer layout, the element patterns of the first element and the second element may be any one of a rectangle and an equal-width line.
In some embodiments of the present application, in the layer layout of the integrated circuit, the signal lines may be represented by equal-width lines, and the vias and the integrated circuit components may be represented by rectangles or other polygons, for example, the implanted regions, the poly regions, and the well regions of the device.
In some embodiments of the present application, the projection overlap of the first element in the first layer layout and the second element in the second layer layout in the direction perpendicular to the integrated circuit layout may have the following two-layer meaning: 1. and the projection of the first element in the first layer layout and the projection of the second element in the second layer layout in the direction vertical to the integrated circuit layout are completely overlapped. 2. The projection of the first element in the first layer layout and the projection of the second element in the second layer layout in the direction perpendicular to the integrated circuit layout are not completely overlapped. In one example, referring to fig. 2, the line widths of the signal lines in the M4 layer and the M5 layer in the region a in fig. 2 are the same, the signal lines in the M4 layer and the M5 layer are completely overlapped, and the signal lines in the M4 layer and the M5 layer are overlapped with the signal lines in the M3 layer due to dense distribution (i.e., not completely overlapped, as the signal lines in the region B in fig. 2 are overlapped).
Then, step 120 is introduced, in response to a first operation of a user, displaying a first element and a second element in the integrated circuit layout in a simplified layout display manner, so that projections of the first element and the second element in a direction perpendicular to the integrated circuit layout do not overlap, and a connection relationship of each element in each layer of layer layout displayed in the simplified layout display manner is the same as a connection relationship of each element in the integrated circuit layout.
The first operation may be to display the first element and the second element in the integrated circuit layout in a simplified layout display manner, and the first operation may include, but is not limited to, a click operation, a filling operation, a sliding operation, a gesture operation, a voice operation, and the like. A combination of at least two of the above operations is also possible.
In some embodiments of the application, the first operation may be a control button for clicking a "simplified layout display mode" in the integrated circuit layout, or may also be a shortcut key, and the specific first operation may be set according to a user requirement, which is not limited herein.
In one example, continuing with the example in fig. 2, a user may respond to the user's operation by clicking a shortcut key to display signal lines in the layer layouts of the M3 layer, the M4 layer, and the M5 layer in a simplified layout display manner in which projections of the signal lines in the layer layouts of the M3 layer, the M4 layer, and the M5 layer in a direction perpendicular to the integrated circuit layout do not overlap (as shown in fig. 3).
In another example, referring to fig. 4, VIA2 (the first element) in the M2 layer and VIA3 (the second element) in the M3 layer are located at the same position and have the same size (e.g., VIA2 and VIA3 overlap in the left half of fig. 4), and it is easy to determine as a VIA, and after a user clicks a shortcut, the first element and the second element can be displayed in the integrated circuit layout in a simplified layout display manner in which projections of the first element and the second element in a direction perpendicular to the integrated circuit layout do not overlap (e.g., right half of fig. 4) in response to the user's operation.
It should be noted that, in some embodiments of the present application, the term "making the projections of the first element and the second element in the direction perpendicular to the integrated circuit layout non-overlap" refers to reducing the overlapping proportion of the projections of the first element and the second element in the direction perpendicular to the integrated circuit layout, even if the projections of the boundary of the first element and the boundary of the second element in the direction perpendicular to the integrated circuit layout do not completely overlap, so that the projections of the boundary of the first element and the boundary of the second element in the direction perpendicular to the integrated circuit layout are clearer (as shown in fig. 3 and the right half of fig. 4).
In some embodiments of the present application, in order to improve the display efficiency on the integrated circuit layout, before step 120, the integrated circuit layout display method related to above may further include:
receiving setting operation of display modes of a first element and a second element;
and determining the simplified layout display mode of the first element and the second element in response to the setting operation.
The operation of setting the display modes of the first element and the second element may be an operation of setting the display modes of the first element and the second element.
In the embodiment of the application, the setting operation of the display modes of the first element and the second element is received, the simplified layout display modes of the first element and the second element are determined in response to the setting operation, and the simplified layout display modes of the first element and the second element are set in advance, so that after a user carries out the first operation, the first element and the second element can be directly displayed according to the previously set simplified layout display modes of the first element and the second element, and the display efficiency of the integrated circuit layout is improved.
In some embodiments of the present application, the receiving a setting operation of a display manner of the first element and the second element may include at least one of:
receiving a setting operation of a display scale between a first size of a first element and a second size of a second element;
a set operation for a first size of a first element and a set operation for a second size of a second element are received.
Wherein the first size may be a size of the first element when displayed in the simplified layout display manner.
The second size may be a size of the second element when displayed in the simplified layout display manner.
In some embodiments of the present application, the first element and the second element may be displayed in the integrated circuit layout at a previously set display scale in response to a first operation by a user by setting the display scale between a first size of the first element and a second size of the second element.
In an example, with continued reference to fig. 2 and fig. 3, the integrated circuit layout has two layer layouts of M4 and M5, and the signal lines in the two layer layouts of M4 and M5 (i.e. equal-width lines, because the signal lines may be represented by equal-width lines in the integrated circuit layout) have the same positions and the same sizes, so that a user may preset the display ratio of the signal lines in the two layer layouts of M4 and M5 when displaying in the simplified layout display manner, for example, the display ratio of the signal lines in the two layer layouts of M4 and M5 is set to 0.8:1, and when displaying in the subsequent simplified layout display manner, if the side length of the signal line in the layer layout of M4 is 0.8um, the side length of the signal line in the layer layout of M5 is 1 um. That is, the signal lines overlapped in fig. 2 can be displayed in a simplified manner in the form shown in fig. 3 by the display scale of the first size and the second size which are set in advance when the simplified layout display mode is used for displaying.
In some embodiments of the present application, the size of the first element when displayed in the simplified layout display manner may be specifically set, and the size of the second element when displayed in the simplified layout display manner may be specifically set.
In one example, with continued reference to fig. 2 and 3, the integrated circuit layout has two layer layouts of M4 and M5, and the signal lines in the two layer layouts of M4 and M5 have the same position and the same size, so that the user can preset the specific size of the first element when the first element is displayed in the simplified layout display manner, and the specific size of the second element when displayed in the simplified layout display manner, for example, the signal lines in the layer layout of the M4 layer are set to be displayed with a width of 1um when displayed in the simplified layout display manner, the signal lines in the layer layout of the M5 layer are set to be displayed with a width of 1.2um when displayed in the simplified layout display manner, then the size of the first element (i.e. the width of the first element) is 1um and the size of the second element (i.e. the width of the second element) is 1.2um when displaying in the simplified layout display manner.
In an embodiment of the present application, the display scale is set by receiving a setting operation for a display scale between a first size of a first element and a second size of a second element; or receiving the setting operation of the first size of the first element and the setting operation of the second size of the second element to set the sizes of the first element and the second element, so that the sizes of the first element and the second element can be set according to the requirements of a user, and the user can clearly distinguish the first element and the second element in the layer layout of each layer when displaying in a simplified layout display mode subsequently.
In some embodiments of the application, after the setting operation of the display modes of the first element and the second element is preset, if the first element and the second element are displayed in the simplified layout display mode in the integrated circuit layout after responding to the first operation, a user is unsatisfied, that is, the user feels unclear or not clear enough, at this time, the user can return to the setting interface (specifically, return to the setting interface through a return shortcut key and the like), and the display modes of the first element and the second element are set again, so that the sizes of the first element and the second element when the first element and the second element are displayed in the simplified display mode can be continuously adjusted according to the user requirements, and thus the user requirements are met to the maximum extent.
In some embodiments of the application, when the first element and the second element are displayed in the simplified layout display manner, non-overlapping display may be performed with reference to a center of a corresponding element graphic.
For the first element or the second element, the element pattern corresponding to the element may be a pattern formed by projection of the element in a direction perpendicular to the integrated circuit layout direction. For example, taking an element as a through hole, if the projection of the element in the direction perpendicular to the integrated circuit layout direction is a rectangle, the element pattern corresponding to the element is a rectangle. For another example, taking an element as a signal line, if the projection of the element in the direction perpendicular to the integrated circuit layout direction is a rectangle, the element pattern corresponding to the element is a rectangle.
In an example, referring to fig. 2 and 3, elements of signal lines in layer layouts of the M3 layer, the M4 layer, and the M5 layer are signal lines, and corresponding element patterns are rectangles, after sizes of the first element and the second element when the first element and the second element are displayed in a simplified layout display manner are preset, a user can display the first element and the second element in the simplified layout display manner in the integrated circuit layout by using a shortcut key, and specifically, when the first element and the second element are displayed, projection of the first element and the projection of the second element in a direction perpendicular to the integrated circuit layout may be displayed in a non-overlapping manner with reference to a center of the rectangle.
In another example, referring to fig. 5, fig. 5 is a portion of real integrated circuit layout data intercepted, such as the upper half of fig. 5, in the integrated circuit layout, signal lines in layer layouts of M3 layers and M4 layers overlap, signal lines in layer layouts of M2 layers and M4 layers overlap, signal lines in layer layouts of M5 layers and M7 layers overlap, and vias in layers of M2 layers and M3 layers overlap. By receiving a setting operation on the display modes of the first element and the second element, in response to the setting operation, the simplified layout display modes of the first element and the second element can be determined, and after the first operation of a user is responded, the overlapped elements in the layer layouts of the layers can be displayed in a non-overlapping manner (as shown in the lower half part of fig. 5).
It should be noted that, in the integrated circuit layout display method provided in the embodiment of the present application, the execution main body may be an integrated circuit layout display device, or a control module used for executing the integrated circuit layout display method in the integrated circuit layout display device.
Based on the same inventive concept as the risk determination method, the application also provides an integrated circuit layout display device. The integrated circuit layout display device provided by the embodiment of the present application is described in detail below with reference to fig. 6.
Fig. 6 is a schematic diagram illustrating a structure of an integrated circuit layout display apparatus according to an exemplary embodiment.
As shown in fig. 6, the integrated circuit layout display apparatus 600 may include:
the display module 610 is configured to display an integrated circuit layout, where the integrated circuit layout has a multilayer layer layout, and the multilayer layer layout includes a first layer layout and a second layer layout; the first element in the first layer layout and the second element in the second layer layout are overlapped in projection in the direction perpendicular to the integrated circuit layout;
the display module 610 may be further configured to respond to a first operation of a user, display the first element and the second element in the integrated circuit layout in a simplified layout display manner, so that projections of the first element and the second element in a direction perpendicular to the integrated circuit layout do not overlap, and a connection relationship of each element in each layer of layer layout displayed in the simplified layout display manner is the same as a connection relationship of each element in the integrated circuit layout.
In the embodiment of the application, the integrated circuit layout is provided with a plurality of layer layouts, the plurality of layer layouts comprise a first layer layout and a second layer layout, a first element in the first layer layout and a second element in the second layer layout can be displayed in a simplified layout display mode in the integrated circuit layout in response to a first operation of a user through a display module, so that the first element and the second element which are originally overlapped in projection in a direction perpendicular to the integrated circuit layout are not overlapped, the connection relation of each element in each layer layout displayed in the simplified layout display mode is the same as that of each element in the integrated circuit, the first element and the second element which are originally overlapped and the connection relation of each element in each layer layout can be clearly displayed, and the element overlapping in different layer layouts can be avoided, causing confusion.
In some embodiments of the present application, in order to improve the display efficiency on the integrated circuit layout, the integrated circuit layout display apparatus may further include:
the receiving module is used for receiving setting operation of display modes of the first element and the second element;
and the first determining module is used for responding to the setting operation and determining the simplified layout display mode of the first element and the second element.
In some embodiments of the present application, the receiving module may specifically include at least one of:
a first receiving unit configured to receive a setting operation of a display scale between a first size of the first element and a second size of the second element;
a second receiving unit configured to receive a setting operation on a first size of the first element and a setting operation on a second size of the second element.
In some embodiments of the present application, the simplified layout display manner is: the first element and the second element are displayed in a non-overlapping manner with reference to the center of the corresponding element graph.
In some embodiments of the present application, the element graphics of the first element and the second element are rectangles.
In some embodiments of the present application, the first element and the second element comprise at least one of: signal lines and vias.
The integrated circuit layout display device provided in the embodiment of the present application may be used to implement the integrated circuit layout display method provided in the above method embodiments, and the implementation principle and technical effect are similar, and for the sake of brevity, no further description is given here.
Based on the same inventive concept, the embodiment of the application also provides the electronic equipment.
Fig. 7 is a schematic structural diagram of an electronic device according to an embodiment of the present application. As shown in fig. 7, the electronic device may include a processor 701 and a memory 702 storing computer programs or instructions.
Specifically, the processor 701 may include a Central Processing Unit (CPU), or an Application Specific Integrated Circuit (ASIC), or may be configured as one or more Integrated circuits implementing an embodiment of the present invention.
The processor 701 may read and execute the computer program instructions stored in the memory 702 to implement any one of the integrated circuit layout display methods in the above embodiments.
In one example, the electronic device may also include a communication interface 703 and a bus 710. As shown in fig. 7, the processor 701, the memory 702, and the communication interface 703 are connected by a bus 710 to complete mutual communication.
The communication interface 703 is mainly used for implementing communication between modules, devices, units, and/or devices in the embodiment of the present invention.
The electronic device may perform the integrated circuit layout display method in the embodiment of the present invention, thereby implementing the integrated circuit layout display method described in fig. 1.
In addition, in combination with the integrated circuit layout display method in the above embodiment, the embodiment of the present invention may provide a readable storage medium to implement. The readable storage medium having stored thereon program instructions; the program instructions, when executed by a processor, implement any of the integrated circuit layout display methods of the embodiments described above.
It is to be understood that the invention is not limited to the specific arrangements and instrumentality described above and shown in the drawings. A detailed description of known methods is omitted herein for the sake of brevity. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present invention are not limited to the specific steps described and illustrated, and those skilled in the art can make various changes, modifications and additions or change the order between the steps after comprehending the spirit of the present invention.
The functional blocks shown in the above-described structural block diagrams may be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, it may be, for example, an electronic circuit, an Application Specific Integrated Circuit (ASIC), suitable firmware, plug-in, function card, or the like. When implemented in software, the elements of the invention are the programs or code segments used to perform the required tasks. The program or code segments may be stored in a machine-readable medium or transmitted by a data signal carried in a carrier wave over a transmission medium or a communication link. A "machine-readable medium" may include any medium that can store or transfer information. Examples of a machine-readable medium include electronic circuits, semiconductor memory devices, ROM, flash memory, Erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, Radio Frequency (RF) links, and so forth. The code segments may be downloaded via computer networks such as the internet, intranet, etc.
It should also be noted that the exemplary embodiments mentioned in this patent describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above-described steps, that is, the steps may be performed in the order mentioned in the embodiments, may be performed in an order different from the order in the embodiments, or may be performed simultaneously.
Aspects of the present application are described above with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, enable the implementation of the functions/acts specified in the flowchart and/or block diagram block or blocks. Such a processor may be, but is not limited to, a general purpose processor, a special purpose processor, an application specific processor, or a field programmable logic circuit. It will also be understood that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware for performing the specified functions or acts, or combinations of special purpose hardware and computer instructions.
As described above, only the specific embodiments of the present invention are provided, and it can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the system, the module and the unit described above may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again. It should be understood that the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present invention, and these modifications or substitutions should be covered within the scope of the present invention.
Claims (10)
1. A method for displaying an integrated circuit layout, the method comprising:
displaying an integrated circuit layout, wherein the integrated circuit layout is provided with a plurality of layer layouts, and the plurality of layer layouts comprise a first layer layout and a second layer layout; the first element in the first layer layout and the second element in the second layer layout are overlapped in projection in the direction perpendicular to the integrated circuit layout;
and responding to a first operation of a user, displaying the first element and the second element in the integrated circuit layout in a simplified layout display mode so as to enable projections of the first element and the second element in a direction perpendicular to the integrated circuit layout not to be overlapped, wherein the connection relation of each element in each layer of the layout displayed in the simplified layout display mode is the same as that of each element in the integrated circuit layout.
2. The method according to claim 1, wherein prior to said displaying said first element and said second element in said integrated circuit layout in a simplified layout display in response to a first operation by a user, said method further comprises:
receiving a setting operation of display modes of the first element and the second element;
and determining the simplified layout display mode of the first element and the second element in response to the setting operation.
3. The method according to claim 2, wherein the receiving of the setting operation of the display mode of the first element and the second element comprises at least one of the following:
receiving a setting operation of a display scale between a first size of the first element and a second size of the second element;
a set operation for a first size of the first element and a set operation for a second size of the second element are received.
4. The method according to claim 1, wherein the simplified layout display mode is: the first element and the second element are displayed in a non-overlapping manner with reference to the center of the corresponding element graph.
5. The method of any of claims 1-4, wherein the element pattern of the first element and the second element is a rectangle.
6. The method of claim 1, wherein the first element and the second element comprise at least one of: signal lines and vias.
7. An integrated circuit layout display apparatus, characterized in that the apparatus comprises:
the display module is used for displaying an integrated circuit layout, wherein the integrated circuit layout is provided with a plurality of layer layouts, and the plurality of layer layouts comprise a first layer layout and a second layer layout; the first element in the first layer layout and the second element in the second layer layout are overlapped in projection in the direction perpendicular to the integrated circuit layout;
the display module is further configured to display the first element and the second element in the integrated circuit layout in a simplified layout display manner in response to a first operation of a user, so that projections of the first element and the second element in a direction perpendicular to the integrated circuit layout are not overlapped, and a connection relationship of each element in each layer of layer layout displayed in the simplified layout display manner is the same as a connection relationship of each element in the integrated circuit layout.
8. The apparatus of claim 7, further comprising:
the receiving module is used for receiving setting operation of display modes of the first element and the second element;
and the determining module is used for responding to the setting operation and determining the simplified layout display mode of the first element and the second element.
9. The apparatus of claim 8, wherein the receiving module is specifically configured to at least one of:
receiving a setting operation of a display scale between a first size of the first element and a second size of the second element;
a set operation for a first size of the first element and a set operation for a second size of the second element are received.
10. The apparatus according to claim 7, wherein the simplified layout display mode is: the first element and the second element are displayed in a non-overlapping manner with reference to the center of the corresponding element graph.
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| US11887559B1 (en) | 2022-08-11 | 2024-01-30 | Beijing Eswin Computing Technology Co., Ltd. | Driving instruction modification method and receiver applied to display driver integrated circuit |
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