CN114091387A

CN114091387A - Circuit inspection method, circuit inspection device, electronic apparatus, and storage medium

Info

Publication number: CN114091387A
Application number: CN202111387925.2A
Authority: CN
Inventors: 郭翠娜; 陈权; 冯东东
Original assignee: Haiguang Information Technology Co Ltd
Current assignee: Haiguang Information Technology Co Ltd
Priority date: 2021-11-22
Filing date: 2021-11-22
Publication date: 2022-02-25

Abstract

A circuit inspection method, a circuit inspection apparatus, an electronic device, and a storage medium. The circuit inspection method includes: determining a plurality of circuit nodes; determining a plurality of input scenes corresponding to the circuit; determining element states respectively corresponding to the circuit elements in each selected input scene in the input scenes; determining an equivalent model corresponding to the circuit under the selected input scene according to element states respectively corresponding to the circuit elements and the circuit nodes under the selected input scene; and performing circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under a plurality of input scenes. The circuit checking method can avoid errors caused by manual checking, reduce the workload of circuit checking, improve the reliability and accuracy of circuit design, improve the research and development efficiency, and help circuit designers to efficiently and quickly identify circuit problems in the circuit design process.

Description

Circuit inspection method, circuit inspection device, electronic apparatus, and storage medium

Technical Field

Embodiments of the present disclosure relate to a circuit inspection method, a circuit inspection apparatus, an electronic device, and a non-transitory computer-readable storage medium.

Background

Complex circuits, such as large scale digital integrated circuits, typically include a plurality of circuit blocks. For example, the plurality of circuit blocks may include a plurality of unit circuits as a standard cell library, the unit circuits including combinational logic, sequential logic, and special type cells, etc. During the circuit design process, a designer must ensure the logical correctness of each circuit block (e.g., cell circuit). In the design process, a designer will generally confirm whether each circuit module meets the design target through a simulation tool. If the number of circuit modules is large, and factors such as design optimization and version iteration are considered, a circuit designer needs to modify and check a plurality of circuit modules for many times in the design process.

Disclosure of Invention

At least one embodiment of the present disclosure provides an inspection method of a circuit including a plurality of circuit elements and a plurality of input terminals, the inspection method including: determining a plurality of circuit nodes, wherein each circuit node represents a point of connection with at least one circuit element; determining a plurality of input scenes corresponding to the circuit, wherein each input scene comprises signal states corresponding to the plurality of input ends respectively; determining element states corresponding to the plurality of circuit elements in each of the plurality of input scenarios that is selected; determining an equivalent model corresponding to the circuit in the selected input scene according to the element states respectively corresponding to the circuit elements in the selected input scene and the circuit nodes; and performing circuit check on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenes.

For example, in an inspection method for a circuit provided in at least one embodiment of the present disclosure, each equivalent model includes a plurality of equivalent nodes and a plurality of equivalent edges, the circuit further includes a ground terminal and at least one power terminal, an element state of each circuit element includes a conducting state or a non-conducting state, and determining, according to the element states and the circuit nodes corresponding to the circuit elements respectively in the selected input scenario, the equivalent model corresponding to the circuit in the selected input scenario includes: taking the plurality of circuit nodes, the ground terminal and the at least one power terminal as a plurality of equivalent nodes of an equivalent model corresponding to the circuit in the selected input scenario; the multiple circuit elements are used as multiple equivalent edges in an equivalent model corresponding to the circuit under the selected input scene, wherein each equivalent edge is used for connecting two equivalent nodes in the equivalent model corresponding to the circuit under the selected input scene; and determining equivalent path values corresponding to the equivalent edges respectively based on element states corresponding to the circuit elements respectively, wherein in response to the element state of the circuit element being a conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a first value, in response to the element state of the circuit element being a non-conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a second value, and the first value and the second value are different.

For example, in an inspection method for a circuit provided in at least one embodiment of the present disclosure, performing a circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenarios includes: determining at least one check group based on the ground terminal and the at least one power terminal, wherein each check group includes one of the ground terminal and the at least one power terminal; and traversing the equivalent models for each selected checking group, determining whether a short-circuit path exists between the power supply end and the ground end in the selected checking group in each selected equivalent model, and determining that the circuit has a short-circuit problem in the input scene corresponding to the selected equivalent model in response to the existence of the short-circuit path between the power supply end and the ground end in the selected checking group.

For example, in an inspection method of a circuit provided in at least one embodiment of the present disclosure, determining whether a short-circuit path exists between a power supply terminal and a ground terminal in the selected inspection group in each selected equivalent model includes: determining whether a shortest circuit path exists between a power supply end and a ground end in the selected check group, and in response to the shortest circuit path existing between the power supply end and the ground end in the selected check group, calculating an equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value corresponding to at least one equivalent edge included in the shortest circuit path; judging whether the shortest circuit path is a short-circuit path or not according to the equivalent path sum; determining that a short circuit path does not exist between the power supply terminals in the selected check group and the ground terminal in response to the shortest circuit path not existing between the power supply terminals in the selected check group and the ground terminal.

For example, in an inspection method of a circuit provided in at least one embodiment of the present disclosure, the equivalent path sum is a sum of the at least one equivalent path value or a weighted sum of the at least one equivalent path value.

For example, in an inspection method of a circuit provided in at least one embodiment of the present disclosure, the determining whether the shortest circuit path is a short-circuit path according to the equivalent path sum includes: determining that the shortest circuit path is a short circuit path in response to the equivalent path sum being equal to the first value; in response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a shorted path.

For example, the method for checking a circuit provided in at least one embodiment of the present disclosure further includes: and in response to the shortest circuit path being a short-circuit path, recording the shortest circuit path, the input scene corresponding to the selected equivalent model, and the power supply end and the ground end included in the selected check group.

For example, in an inspection method for a circuit provided in at least one embodiment of the present disclosure, the circuit further includes at least one power supply terminal, and the performing a circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit in the plurality of input scenarios includes: for each selected circuit node of the plurality of circuit nodes: determining whether a conductive path exists between the at least one power terminal and the selected circuit node under the plurality of input scenarios based on the plurality of equivalent models; in response to a conductive path existing between either power supply terminal and the selected circuit node in either input scenario, determining that a high-impedance state does not exist between the selected circuit node and the at least one power supply terminal; determining that a high state exists between the selected circuit node and the at least one power source terminal in response to no conductive path existing between the at least one power source terminal and the selected circuit node in the plurality of input scenarios.

For example, in an inspection method of a circuit provided in at least one embodiment of the present disclosure, determining whether a conduction path exists between the at least one power source terminal and the selected circuit node in the plurality of input scenarios based on the plurality of equivalent models includes: for each selected one of the at least one power terminals, traversing the plurality of equivalent models, performing a conduction path detection on each selected equivalent model; wherein the conduction path detection comprises: in the selected equivalent model, in response to a shortest circuit path existing between the selected power source terminal and the selected circuit node, determining whether the shortest circuit path is a conducting path, in response to the shortest circuit path being a conducting path, determining that a conducting path exists between the selected power source terminal and the selected circuit node in an input scenario corresponding to the selected equivalent model, in response to the shortest circuit path not being a conducting path or in response to no shortest circuit path existing between the selected power source terminal and the selected circuit node, determining that a conducting path does not exist between the selected power source terminal and the selected circuit node in an input scenario corresponding to the selected equivalent model, and continuing to perform the conducting path detection on a next equivalent model.

For example, in an inspection method of a circuit provided in at least one embodiment of the present disclosure, the determining whether the shortest circuit path is a conducting path or not, where the first value is 0, includes: calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value corresponding to at least one equivalent edge included in the shortest circuit path; determining that the shortest circuit path is a conductive path in response to the equivalent path sum being equal to the first value; in response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a conductive path.

For example, in an inspection method for a circuit provided in at least one embodiment of the present disclosure, the circuit further includes a ground terminal, and the performing a circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit in the plurality of input scenarios includes: for each selected circuit node of the plurality of circuit nodes: determining whether a conduction path exists between the ground terminal and the selected circuit node under the plurality of input scenes based on the plurality of equivalent circuits; in response to a conducting path existing between the ground terminal and the selected circuit node in any input scenario, determining that a high-impedance state does not exist between the selected circuit node and the ground terminal; and determining that a high-impedance state exists between the selected circuit node and the ground terminal in response to no conducting path existing between the ground terminal and the selected circuit node under the plurality of input scenes.

For example, in an inspection method of a circuit provided in at least one embodiment of the present disclosure, each input terminal has a first signal state and a second signal state, where the first signal state and the second signal state are different, and determining a plurality of input scenarios corresponding to the circuit includes: combining the signal states of the plurality of input ends to determine the plurality of input scenes, wherein the number of the plurality of input ends is N, and the number of the plurality of input scenes is 2^NAnd N is a positive integer.

For example, in an inspection method for a circuit provided in at least one embodiment of the present disclosure, the plurality of circuit elements includes a plurality of first circuit elements, the plurality of first circuit elements are connected to the plurality of input terminals, and determining element states respectively corresponding to the plurality of circuit elements in each of the plurality of input scenarios that is selected includes: determining the signal states corresponding to the plurality of input ends respectively under the selected input scene; and determining element states corresponding to the plurality of first circuit elements under the selected input scene according to the signal states corresponding to the plurality of input ends respectively.

For example, in an inspection method for a circuit provided in at least one embodiment of the present disclosure, the circuit is a digital circuit, and determining the plurality of circuit nodes includes: obtaining a netlist corresponding to the circuit; and determining the plurality of circuit nodes according to the netlist.

For example, in the method for checking a circuit provided in at least one embodiment of the present disclosure, the circuit is a cell circuit of a standard cell library.

For example, in the inspection method of a circuit provided in at least one embodiment of the present disclosure, each circuit element is a transistor or a resistor.

At least one embodiment of the present disclosure provides an inspection apparatus of a circuit including a plurality of circuit elements and a plurality of input terminals, the inspection apparatus including: a node determination unit configured to determine a plurality of circuit nodes, wherein each circuit node represents a point to which at least one circuit element is connected; an input scene determining unit configured to determine a plurality of input scenes corresponding to the circuit, wherein the plurality of input scenes comprise signal states corresponding to the plurality of input ends respectively; an element state determination unit configured to determine element states to which the plurality of circuit elements respectively correspond in each of the plurality of input scenarios selected; an equivalent model determination unit configured to determine an equivalent model corresponding to the circuit in the selected input scenario according to element states respectively corresponding to the plurality of circuit elements in the selected input scenario and the plurality of circuit nodes; a checking unit configured to perform a circuit check on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenarios.

At least one embodiment of the present disclosure provides an electronic device, including: a memory non-transiently storing computer executable instructions; a processor configured to execute the computer-executable instructions, wherein the computer-executable instructions, when executed by the processor, implement a method of inspection of a circuit according to any embodiment of the present disclosure.

At least one embodiment of the present disclosure provides a non-transitory computer-readable storage medium having stored thereon computer-executable instructions that, when executed by a processor, implement a method of checking a circuit according to any one of the embodiments of the present disclosure.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description relate only to some embodiments of the present disclosure and are not limiting to the present disclosure.

FIG. 1A is a schematic circuit diagram according to an embodiment of the present disclosure;

FIG. 1B is a schematic circuit diagram according to another embodiment of the present disclosure;

fig. 2 is a schematic flow chart of a method for inspecting a circuit according to at least one embodiment of the present disclosure;

FIG. 3A is a schematic diagram of an equivalent model according to an embodiment of the disclosure;

FIG. 3B is a schematic diagram of an equivalent model according to another embodiment of the disclosure;

fig. 4 is a flowchart of a circuit inspection method according to at least one embodiment of the disclosure;

fig. 5 is a schematic block diagram of an inspection apparatus for an electrical circuit according to at least one embodiment of the present disclosure;

fig. 6 is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure;

fig. 7 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings of the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.

To maintain the following description of the embodiments of the present disclosure clear and concise, a detailed description of some known functions and components may be omitted from the present disclosure.

In a circuit design process, especially for a complex circuit, the circuit may generate errors due to subjective or objective factors, for example, the circuit includes a plurality of circuit elements, the plurality of circuit elements have different types, and the connection relationship of the plurality of circuit elements is complex, so that the circuit may generate a short circuit problem, a high impedance problem, and the like due to various factors.

For example, in the embodiments of the present disclosure, the short-circuit problem refers to that the circuit has a path that is directly conducted from the power source terminal to the ground terminal under the control of the input control signal, and the path that is directly conducted from the power source terminal to the ground terminal is a short-circuit path, where direct conduction refers to that current directly flows from the power source terminal to the ground terminal without passing through any circuit element or only passing through a circuit element in a conducting state (e.g., a transistor, a diode, etc.) and without passing through any circuit element.

Fig. 1A is a schematic diagram of a circuit according to an embodiment of the disclosure.

In fig. 1A, VDD denotes a power supply terminal, VSS denotes a ground terminal, T1 to T5 denote 5 transistors, where T1 to T4 denote 4P-type transistors, T5 denotes an N-type transistor, net _ x0, net _ x1, and net _ x2 denote 3 circuit nodes, and A, B, C denotes three input terminals for inputting a control signal to the gate of each transistor to control the turning on and off of the transistor. For example, each input terminal includes two signal states, respectively indicated as 0 and 1, when the control signal is low, the N-type transistor is turned off and the P-type transistor is turned on, and when the control signal is high, the N-type transistor is turned on and the P-type transistor is turned off, and when the input terminal is turned on, the signal state is indicated as 1.

It should be noted that 0 and 1 in the present disclosure indicate two signal states, for example, 0 indicates a low state, and 1 indicates a high state, and according to the actual situation of different circuits, the voltage range corresponding to the low state and the voltage range corresponding to the high state may be different, as long as the low state can turn off the N-type transistor and turn on the P-type transistor, and the high state can turn on the N-type transistor and turn off the P-type transistor.

For example, the input terminal B inputs the control signal B to the gate of the transistor T1, the input terminal a inputs the control signal a to the gates of the transistors T2 and T4, the input terminal C inputs the control signal C to the gate of the transistor T3, and the control signal a obtained by negating the control signal a of the input terminal a is used as the control signal

The gate of the input transistor T5,

when the result of the non-operation of a, that is, when a is 1,

when A is equal to 0, the compound is,

in the circuit shown in fig. 1A, the transistor T5 is also controlled by the control signal output from the input terminal a.

For example, when a is 0, B is 0, and C is 1, the transistor T2, the transistor T4, and the transistor T5 are turned on, and the transistor T1 and the transistor T3 are turned off, so that the circuit generates a short-circuit path: the power supply end VDD- > the transistor T2- > the transistor T4- > the transistor T5- > the ground end VSS, and the short-circuit path directly connects the power supply end VDD and the ground end VSS together, so that the circuit has a short-circuit problem.

For example, in embodiments of the present disclosure, the high impedance problem refers to: a circuit node (net) in the circuit is in a high impedance state, i.e. a floating state.

Fig. 1B is a schematic diagram of a circuit according to another embodiment of the disclosure.

In fig. 1B, VDD1 and VDD2 denote two power source terminals having different potentials, VSS denotes a ground terminal, T1, T2, T3, T4, T5, A, B, C, and,

The meaning of (A) is the same as that of FIG. 1A, and repeated description is omitted. In addition, the circuit shown in fig. 1B further includes an input terminal D, an input terminal E, and two transistors T6 and T7, the transistors T6 and T7 are both N-type transistors, the input terminal D inputs the control signal D to the gate of the transistor T6, and the input terminal E inputs the control signal E to the gate of the transistor T7. The definition of the input terminal D and the input terminal E is the same as that of the input terminal a, the input terminal B and the input terminal C, and the description thereof is omitted.

The circuit includes 6 circuit nodes net _ y0, net _ y1, net _ y2, net _ y3, net _ y4, and net _ y5, respectively. As can be seen from fig. 1B, there is no conductive path between the circuit node net _ y2 and the ground terminal VSS, and there is no conductive path between the circuit node net _ y4 and the power source terminal VDD1 and the power source terminal VDD2, so that the circuit node net _ y2 and the circuit node net _ y4 are in a high impedance state, which causes a problem of high impedance.

In the design process of a complex circuit, such as a large-scale integrated circuit, if the short-circuit problem and the high-impedance problem are not found in time in the design stage of a unit circuit, the short-circuit problem and the high-impedance problem are more difficult to find in the subsequent layout design stage, so that the research and development progress of the circuit is influenced, and the hidden trouble of circuit design is possibly generated.

For example, for a circuit with a complex structure, a circuit designer usually checks the correctness of the circuit by a simulation tool, for example, inputting a stimulus signal to an input terminal of the circuit and judging by the result of the simulation tool.

However, when a circuit designer checks a circuit by looking up a waveform diagram of a simulation result through a simulation tool, a subtle waveform abnormality is difficult to find, and a circuit problem (such as a short circuit problem or a high impedance state problem) hidden in the circuit is difficult to be checked. In addition, considering factors such as inspection cost and inspection workload, and the circuit designer may not inspect all states of the circuit, for example, the circuit designer focuses on verifying the normal operating state of the circuit, and may not completely inspect the abnormal operating state of the circuit.

At least one embodiment of the present disclosure provides a circuit inspection method, a circuit inspection apparatus, an electronic device, and a non-transitory computer-readable storage medium. The circuit inspection method includes: determining a plurality of circuit nodes; determining a plurality of input scenes corresponding to the circuit; determining element states corresponding to the circuit elements under each selected input scene in the input scenes; determining an equivalent model corresponding to the circuit under the selected input scene according to element states respectively corresponding to the circuit elements and the circuit nodes under the selected input scene; and performing circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under a plurality of input scenes.

According to the circuit inspection method provided by at least one embodiment of the disclosure, according to circuit nodes and element states of circuit elements in different input scenes, a circuit is converted into different equivalent models, circuit inspection is performed on the equivalent models in various input scenes, errors caused by artificial inspection are avoided, circuit inspection workload is reduced, reliability and accuracy of circuit design are improved, research and development efficiency is improved, and circuit problems existing in the circuit, such as a short circuit problem or a high impedance problem, are efficiently and quickly identified by circuit designers in a circuit design process.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings, but the present disclosure is not limited to these specific embodiments.

Fig. 2 is a schematic flow chart of an inspection method of a circuit according to at least one embodiment of the present disclosure.

For example, the circuitry may include digital circuitry or analog circuitry. For example, a circuit in the present disclosure may refer to a partial design or a partial module in a large circuit design, that is, the circuit in the present disclosure may be a complete circuit itself, or may be a partial circuit in a complete circuit, and the present disclosure is not limited thereto.

For example, the circuit may be a cell circuit of a standard cell library in a digital circuit.

For example, a circuit includes a plurality of circuit elements and a plurality of inputs. For example, the circuit element includes a transistor, a resistor, and the like, and the input terminal includes a gate signal input terminal of the transistor, and the like. Taking fig. 1A as an example, the plurality of circuit elements include a transistor T1 through a transistor T5, and the plurality of inputs include an input a, an input B, and an input C.

For example, as shown in fig. 2, the inspection method of the circuit provided by the embodiment of the present disclosure includes steps S10 to S50.

In step S10, a plurality of circuit nodes are determined.

For example, each circuit node represents a point connected to at least one circuit element, that is, a plurality of circuit nodes includes a point connected to at least two circuit elements and a point connected to one circuit element.

For example, taking fig. 1A as an example, the plurality of circuit nodes in the circuit shown in fig. 1A include a circuit node net _ x0, a circuit node net _ x1, and a circuit node net _ x2, for example, the circuit node net _ x0 is a point at which the transistor T1 and the transistor T3 are connected, and the circuit node net _ x2 is a point at which the transistor T3, the transistor T4, and the transistor T5 are connected. For example, taking fig. 1B as an example, the plurality of circuit nodes in the circuit shown in fig. 1B include a circuit node net _ y0, a circuit node net _ y1, a circuit node net _ y2, a circuit node net _ y3, a circuit node net _ y4, and a circuit node net _ y5, where the circuit node net _ y2 is a point connected to the transistor T3, the circuit node net _4 is a point connected to the transistor T4, that is, the circuit node net _ y2 is connected to only one circuit element, and the circuit node net _ y4 is also connected to only one circuit element.

For example, the voltage state of a point at which a circuit element is connected to a ground terminal or a power terminal is fixed, and thus, a circuit inspection may not be performed as a circuit node. That is, in the embodiment of the present disclosure, the points directly connected to the power and ground terminals do not serve as circuit nodes.

For example, when the circuit is an analog circuit, step S10 may include: electrical characteristics of a plurality of circuit elements in the circuit are analyzed to obtain a plurality of circuit nodes.

For example, when the circuit is a digital circuit, step S10 may include: obtaining a netlist corresponding to the circuit; a plurality of circuit nodes are determined from the netlist.

For example, the netlist is a gate-level netlist corresponding to the digital circuit, the gate-level netlist describes the connection relationship of circuit elements in the circuit in a text language, and the connection relationship between logic gates (and, or, not), flip-flops and the like is recorded. Therefore, the information of the circuit nodes is recorded in the netlist, and a plurality of circuit nodes can be obtained by reading the netlist corresponding to the circuit.

In step S20, a plurality of input scenes corresponding to the circuit are determined.

For example, each input scenario includes a plurality of signal states respectively corresponding to the input terminals.

For example, each input terminal has a first signal state and a second signal state, the first signal state and the second signal state being different. For example, the first signal state indicates that the control signal input from the input terminal belongs to a first voltage range, for example, the first signal state is a low level state as described above, and the second signal state indicates that the control signal input from the input terminal belongs to a second voltage range, for example, the second signal state is a high level state as described above. The first voltage range and the second voltage range are set according to actual conditions.

For example, step S20 may include: for signals of multiple inputsAnd combining the number states to determine a plurality of input scenes, wherein the number of the plurality of input ends is N, and the number of the plurality of input scenes is 2^NAnd N is a positive integer.

For example, for any two input scenarios in the plurality of input scenarios, the signal states of the plurality of input terminals in one of the any two input scenarios are not identical to the signal states of the plurality of input terminals in another of the any two input scenarios.

For example, taking the circuit shown in FIG. 1A as an example, the circuit at least includes 3 input terminals, namely input terminal A, input terminal B and input terminal C, the 3 input terminals are used for inputting the control signal A, the control signal B, the control signal C and the control signal C to the gates of the transistors T1-T5

For example, the input terminal is represented by 0 when in the first signal state, for example, the first signal state is a low level state; the input terminal is denoted by 1 when in the second signal state, for example when the second signal state is a high state. For this circuit, the signal states of 3 inputs are combined, and 2 can be determined in total³In any two of the 8 input scenarios, the signal states of the 3 inputs in one of the two input scenarios are not exactly the same as the signal states of the 3 inputs in the other of the two input scenarios. For example, 8 input scenarios include:

input scenario 1: a is 0, B is 0, C is 0; input scenario 2: a is 1, B is 0, C is 0; input scenario 3: a is 0, B is 1, C is 0; input scenario 4: a ═ 0, B ═ 0, C ═ 1; input scenario 5: a is 1, B is 1, C is 0; input scenario 6: a is 0, B is 1, C is 1; input scenario 7: a is 1, B is 0, C is 1; input scenario 8: a is 1, B is 1 and C is 1.

Here, a ═ 0 indicates that the input terminal a has the first signal state, a ═ 1 indicates that the input terminal a has the second signal state, and B and C are the same.

For example, when the number of the plurality of input scenes is2^NIn the process, all possible input scenes can be subjected to traversal inspection during circuit inspection, so that circuit errors possibly existing in all input scenes are determined, the circuit inspection cost and the time overhead are greatly reduced, the accuracy and the reliability of the circuit inspection are improved, and circuit designers can be timely and quickly helped to find leaks which are not easy to find in the circuit.

It should be noted that the multiple input scenarios may be part or all of all possible input scenarios corresponding to the circuit, and in practice, the multiple input scenarios may be selected according to needs, which is not limited by the present disclosure.

In step S30, element states corresponding to the plurality of circuit elements in each of the plurality of input scenarios are determined.

For example, the plurality of circuit elements includes a plurality of first circuit elements connected to the plurality of input terminals, and the first circuit elements may be transistors, for example.

For example, step S30 may include: determining signal states respectively corresponding to the plurality of input ends under the selected input scene; and determining element states corresponding to the first circuit elements under the selected input scene according to the signal states corresponding to the input ends respectively.

For example, when the first circuit element is a transistor, if the input terminal is in a first signal state, such as a low level state, the N-type transistor whose gate is connected to the input terminal is in an off state, that is, a non-conducting state, and the P-type transistor whose gate is connected to the input terminal is in a conducting state; if the input terminal is in a second signal state, for example, a high level state, the N-type transistor having the gate connected to the input terminal is in a conducting state, and the P-type transistor having the gate connected to the input terminal is in a closed state, that is, a non-conducting state. Thus, the element state of the first circuit element may be determined based on the signal state corresponding to the input terminal to which the first circuit element is connected, for example, the element state includes a conductive state and a non-conductive state.

For example, the plurality of circuit elements may further include at least one second circuit element, which may be a resistor, for example.

For example, when the circuit further includes a second circuit element, step S30 may further include: an element state corresponding to the at least one second circuit element is determined. For example, when the second circuit element is a resistor, the element state of the second circuit element can be directly determined to be an on state. The element state of the second circuit element is independent of the signal state of the input terminal.

For example, the circuit elements may also include capacitors, diodes, and the like, which the present disclosure is not particularly limited. One skilled in the art can determine the element state of each circuit element according to the specific conductive state of the circuit element in the circuit, for example, if the circuit element is conductive, the element state is conductive, and vice versa.

In step S40, an equivalent model corresponding to the circuit in the selected input scenario is determined according to the element states corresponding to the circuit elements in the selected input scenario and the circuit nodes.

For example, each equivalence model includes a plurality of equivalence nodes and a plurality of equivalence edges. For example, referring to the graph theory principle, a circuit node is equivalent to an equivalent node, a circuit element is equivalent to an equivalent edge, and an equivalent path value of the equivalent edge, that is, a weight of the equivalent edge, is determined according to an element state of the circuit element, so that the circuit is converted into an equivalent model composed of the equivalent node and the equivalent edge.

For example, the circuit further comprises a ground terminal and at least one power terminal, different power terminals may have different potentials. For example, as shown in fig. 1B, the circuit includes 2 power terminals, i.e., power terminal VDD1 and power terminal VDD2, respectively, the power terminal VDD1 may have a potential of 5V (volts), and the power terminal VDD2 may have a potential of 10V. Of course, the potential of the power supply terminal may be a positive potential or a negative potential as needed, which is not limited by the present disclosure.

For example, the element state of each circuit element includes a conducting state or a non-conducting state, and reference may be made to the related description of step S30 for the conducting state and the non-conducting state, which is not described herein again.

For example, step S40 may include: taking the multiple circuit nodes, the grounding terminal and the at least one power supply terminal as multiple equivalent nodes of an equivalent model corresponding to the circuit under the selected input scene; taking a plurality of circuit elements as a plurality of equivalent edges in an equivalent model corresponding to the circuit under the selected input scene, wherein each equivalent edge is used for connecting two equivalent nodes in the equivalent model corresponding to the circuit under the selected input scene; and determining equivalent path values corresponding to the equivalent edges respectively based on element states corresponding to the circuit elements, wherein in response to the element state of the circuit element being a conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a first value, in response to the element state of the circuit element being a non-conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a second value, and the first value and the second value are different.

For example, the first value may be 0, the second value may be 1, or other non-0 values, such as 9999. The first value and the second value are different from each other, thereby distinguishing between a conductive state and a non-conductive state.

Specifically, the plurality of circuit nodes, the ground terminal, and the power source terminal are all equivalent to equivalent nodes, the circuit elements are all equivalent to equivalent edges, the equivalent edges are used for connecting the two equivalent nodes, and the equivalent edges correspond to different equivalent path values according to different element states corresponding to the circuit elements. Each equivalent node is connected with at least one equivalent edge. For example, in the circuit, the circuit element a is electrically connected to the ground terminal and the circuit node a, and the circuit element a is used for connecting the ground terminal and the circuit node a, then in the equivalent model, the ground terminal and the circuit node a are equivalent to two equivalent nodes, and the two equivalent nodes are connected by an equivalent edge a of the circuit element a. If the circuit element a is in the on state according to the signal states corresponding to the plurality of input ends in the input scenario a, the equivalent path value corresponding to the equivalent edge a in the equivalent model corresponding to the input scenario a is a first value, for example, 0. If the circuit element a is in a non-conducting state according to the signal states corresponding to the plurality of input ends in the input scenario b, the equivalent path value corresponding to the equivalent edge a in the equivalent model corresponding to the input scenario b is a second value, for example, 1.

For example, the positions and connection relationships of the equivalent nodes and the equivalent edges in the equivalent model are determined based on the positions and connection relationships between the plurality of circuit elements, the power source terminal, the ground terminal, and the plurality of circuit nodes in the circuit.

Fig. 3A is a schematic diagram of an equivalent model according to an embodiment of the disclosure. For example, fig. 3A is a corresponding equivalent model of the circuit shown in fig. 1A under a selected input scenario. For example, the selected input scene may be input scene 6.

As shown in fig. 3A, the power source terminal VDD, the ground terminal VSS, the circuit nodes net _ x0, net _ x1 and net _ x2 in fig. 1A are all equivalent to equivalent nodes, as shown by the 5 circles labeled VDD, VSS, net _ x0, net _ x1 and net _ x2 in fig. 3A.

As shown in fig. 3A, the transistors T1 to T5 are all equivalent as equivalent sides, as shown by the equivalent sides 1 to 5 connecting the respective equivalent nodes in fig. 3A. For example, in the equivalent model shown in fig. 3A, the transistor T1 is equivalent to the equivalent edge 1 connecting the equivalent node VDD and the equivalent node net _ x0, the transistor T3 is equivalent to the equivalent edge 2 connecting the equivalent node net _ x0 and the equivalent node net _ x2, the transistor T5 is equivalent to the equivalent edge 3 connecting the equivalent node net _ x2 and the ground, the transistor T4 is equivalent to the equivalent edge 4 connecting the equivalent node net _ x1 and the equivalent node net _ x2, and the transistor T2 is equivalent to the equivalent edge 5 connecting the equivalent node VDD and the equivalent node net _ x 1.

For example, in the selected input scenario, the input terminal a has a first signal state, e.g., a low state, the input terminal B and the input terminal C have a second signal state, e.g., a high state, i.e., the transistor T2, the transistor T4, and the transistor T5 are in a conductive state in the selected input scenario, and the transistor T1, the transistor T3 are in a non-conductive state in the selected input scenario. Therefore, in the equivalent model corresponding to the selected input scene, the equivalent path value corresponding to the equivalent edge corresponding to each of the transistor T2, the transistor T4, and the transistor T5 is a first value, for example, 0, and the equivalent path value corresponding to the equivalent edge corresponding to each of the transistor T1 and the transistor T3 is a second value, for example, 9999. As shown in fig. 3A, the number (0 or 9999) beside each equivalent edge represents the equivalent path value corresponding to the equivalent edge.

For example, fig. 3B is a schematic diagram of an equivalent model according to an embodiment of the disclosure. For example, fig. 3B is a corresponding equivalent model of the circuit shown in fig. 1B under the selected input scenario.

As shown in fig. 3B, power source terminal VDD1, power source terminal VDD2, ground terminal VSS, circuit nodes net _ y0, net _ y1, net _ y2, net _ y3, net _ y4 and net _ y5 in fig. 1B are all equivalent to equivalent nodes, as shown by the 9 circles labeled VDD1, VDD2, VSS, net _ y0, net _ y1, net _ y2, net _ y3, net _ y4 and net _ y5 in fig. 3B.

As shown in fig. 3B, the transistors T1 through T7 are all equivalent sides, as indicated by the black straight lines connecting the respective equivalent nodes in fig. 3B. For example, in the equivalent model shown in fig. 3B, the transistor T6 is equivalent to an equivalent edge connecting the equivalent node net _ y4 and the equivalent node net _ y5, and the correspondence between other transistors and the equivalent edge is similar thereto, and is not described again here.

For example, the circuit shown in fig. 1B includes an input terminal D and an input terminal E, which input a control signal D and a control signal E to the gates of the transistor T6 and the transistor T7, respectively, in addition to the input terminal a, the input terminal B, and the input terminal C.

For example, in the selected input scenario, the input terminals a to E all have the second signal state, for example, a high level state, that is, the transistors T6 and T7 are in a conductive state in the selected input scenario, and the transistors T1 to T5 are in a non-conductive state in the selected input scenario. Therefore, in the equivalent model corresponding to the selected input scene, the equivalent path value corresponding to the equivalent edge corresponding to each of the transistors T1 to T5 is a second value, for example 9999, and the equivalent path value corresponding to the equivalent edge corresponding to each of the transistors T6 and T7 is a first value, for example 0. As shown in fig. 3B, the number (0 or 9999) beside each equivalent edge represents the equivalent path value corresponding to the equivalent edge.

It should be noted that, in a plurality of equivalent models corresponding to the circuit in a plurality of input scenarios, the positions and connection relationships of the equivalent nodes and the equivalent edges are the same, and the difference between the plurality of equivalent models is as follows: the equivalent paths corresponding to the equivalent edges have different values.

In step S50, a circuit check is performed on the circuit based on a plurality of equivalent models respectively corresponding to the circuit in a plurality of input scenarios.

After obtaining the plurality of equivalent models, the equivalent models of the circuit under different input scenes can be analyzed by combining a shortest path algorithm (such as dijkstra algorithm) and the like, so as to determine whether a short circuit problem and a high impedance problem exist in the circuit.

For example, when the short circuit check is performed on the circuit, step S50 may include: determining at least one check group based on the ground terminal and the at least one power terminal, wherein each check group includes one of the ground terminal and the at least one power terminal; and traversing a plurality of equivalent models for each selected checking group, determining whether a short-circuit path exists between the power supply end and the ground end in the selected checking group in each selected equivalent model, and responding to the short-circuit path existing between the power supply end and the ground end in the selected checking group, wherein the determining circuit has the short-circuit problem in the input scene corresponding to the selected equivalent model.

For example, if the power supply includes two power supply terminals, e.g., power supply terminal VDD1 and power supply terminal VDD2, two check sets are determined, check set 1 includes power supply terminal VDD1 and ground terminal VSS, check set 2 includes power supply terminal VDD2 and ground terminal VSS, and then, short-circuit checks are respectively performed on the two check sets to determine whether a short-circuit path exists between power supply terminal VDD1 and ground terminal VSS and to determine whether a short-circuit path exists between power supply terminal VDD2 and ground terminal VSS.

For example, in step S50, determining whether a short circuit path exists between the power terminal and the ground terminal in the selected check group in each selected equivalent model may include: determining whether a shortest circuit path exists between a power supply end and a ground end in the selected check group, and calculating an equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value corresponding to at least one equivalent edge included in the shortest circuit path in response to the shortest circuit path existing between the power supply end and the ground end in the selected check group; judging whether the shortest circuit path is a short-circuit path or not according to the equivalent path sum; in response to the absence of the shortest circuit path between the power supply terminal and the ground terminal in the selected check group, it is determined that a short circuit path does not exist between the power supply terminal and the ground terminal in the selected check group.

For example, the shortest circuit path includes a plurality of equivalent nodes and at least one equivalent edge.

For example, any feasible path algorithm (e.g., dijkstra algorithm, etc.) may be used to determine whether the shortest circuit path exists between the power terminals and the ground terminals in the selected check set, which is not limited by this disclosure. For example, at least one shortest circuit path from a start point to an end point is determined based on an equivalent model, with the equivalent node corresponding to the power source terminal as the start point and the equivalent node corresponding to the ground terminal as the end point. It should be noted that the determination of the shortest circuit path is required to satisfy the conventional characteristics of the circuit, for example, the current generally flows from a high potential to a low potential, and the like.

For example, if the shortest circuit path does not exist between the start point and the end point, it is determined that a short-circuit path does not exist between the power source terminal and the ground terminal in the selected inspection set.

For example, if a shortest circuit path exists between the starting point and the end point, an equivalent path sum corresponding to the shortest circuit path is calculated according to at least one equivalent path value corresponding to at least one equivalent edge included in the shortest circuit path, for example, the equivalent path sum is a sum of the at least one equivalent path value or a weighted sum of the at least one equivalent path value.

And then, judging whether the shortest circuit path is a short-circuit path or not according to the equivalent path sum. For example, if the first value is 0, determining whether the shortest circuit path is a short circuit path according to the equivalent path sum includes: determining that the shortest circuit path is a short circuit path in response to the equivalent path sum being equal to a first value; in response to the equivalent path sum not being equal to the first value, it is determined that the shortest circuit path is not a shorted path. When the first value is set to 0, the judgment of the short-circuit path can be achieved simply and efficiently.

Of course, if the first value is not 0 and the equivalent path sum is the sum of at least one equivalent path value, determining whether the shortest circuit path is a short-circuit path according to the equivalent path sum includes: and calculating the total number M of equivalent edges included by the shortest circuit path, determining that the shortest circuit path is a short-circuit path in response to the sum of the equivalent paths being equal to the product of M and the first value, and determining that the shortest circuit path is not the short-circuit path in response to the sum of the equivalent paths not being equal to the product of M and the first value. If the first value is not 0 and the equivalent path sum is a weighted sum of at least one equivalent path value, determining whether the shortest circuit path is a short-circuit path according to the equivalent path sum, including: summing weights respectively corresponding to all equivalent edges included in the shortest circuit path to obtain a weight sum; the shortest circuit path is determined to be a short circuit path in response to the equivalent path sum being equal to the product of the weight sum and the first value, and is determined not to be a short circuit path in response to the equivalent path sum not being equal to the product of the weight sum and the first value.

After the short circuit inspection is carried out on a plurality of equivalent models, the short circuit problem between the power supply end and the grounding end in the selected inspection group under a plurality of input scenes can be obtained, if the plurality of input scenes are all possible input scenes corresponding to the circuit, the circuit can be subjected to omnibearing short circuit inspection, not only all the power supply ends are covered, but also all the possible input conditions are covered, the correctness and the reliability of circuit design are greatly guaranteed, the product design iteration time caused by circuit leaks is reduced, and the research and development speed is improved.

For example, the method for checking a circuit provided in at least one embodiment of the present disclosure may further include: and if the shortest circuit path is the short-circuit path, determining that the circuit has a short-circuit problem, and recording short-circuit information, wherein the short-circuit information can comprise the shortest circuit path, an input scene corresponding to the selected equivalent model with the shortest circuit path, a power supply end and a ground end included in the selected checking group with the shortest circuit path, and the like. And then, after the inspection of all input scenes and all inspection groups of the circuit is finished, providing the short circuit information in all inspection groups and all input scenes for a circuit designer, wherein the circuit designer can accurately position related circuit elements according to the short circuit information to inspect and modify, so that the inspection and modification efficiency of the circuit is improved.

The following describes a process of performing a short circuit check on a circuit according to at least one embodiment of the present disclosure with reference to fig. 1A and fig. 3A.

For example, the input scenario corresponding to the equivalent model shown in fig. 3A is input scenario 6, that is, input terminal a has a first signal state, and input terminals B and C have a second signal state. When the inspection set (i.e. the selected inspection set) includes the power source terminal VDD and the ground terminal VSS, and the short circuit inspection is performed based on the equivalent model shown in fig. 3A, the shortest circuit path from the start point to the end point in the equivalent model is determined by using any feasible path algorithm, with the equivalent node corresponding to the power source terminal VDD as the start point and the equivalent node corresponding to the ground terminal VSS as the end point. For example, the shortest circuit path is the equivalent node VDD- > the equivalent node net _ x0- > the equivalent node net _ x2- > the equivalent node VSS, the shortest circuit path includes 3 equivalent edges, which are the equivalent edge 1, the equivalent edge 2 and the equivalent edge 3, respectively, and the equivalent path values corresponding to the 3 equivalent edges are all 0 (i.e., the first value), so that the equivalent path sum corresponding to the shortest circuit path is 0, which is equal to the first value, thereby determining that the shortest circuit path is a short circuit path.

Then, the short circuit inspection is continuously performed on the next equivalent model until 8 equivalent models are traversed, and at the same time, information of all the short circuit paths, input scenarios corresponding to the equivalent models with short circuit paths (for example, the input terminal a shown in fig. 3A has a first signal state, and the input terminal B and the input terminal C have a second signal state), and the power supply terminal VDD and the ground terminal VSS included in the inspection group with short circuit paths are recorded and provided to the circuit designer, so that the circuit designer inspects corresponding circuit elements by combining the information of the short circuit paths, the input scenarios, and the like, and modifies the circuit.

For example, when the circuit is checked to be in the high-impedance state, whether a conducting path exists between each circuit node and the power supply terminal in all input scenes can be checked, and if no conducting path exists between a certain circuit node and all the power supply terminals in all input scenes, the circuit node is in the high-impedance state, and the circuit has the problem of the high-impedance state.

For example, step S50 may further include: for each selected circuit node of the plurality of circuit nodes: determining whether a conduction path exists between at least one power supply end and the selected circuit node under a plurality of input scenes on the basis of a plurality of equivalent models; in response to a conductive path existing between either power supply terminal and the selected circuit node in either of the input scenarios, determining that a high-impedance state does not exist between the selected circuit node and at least one power supply terminal; in response to no conductive path existing between at least one power supply terminal and the selected circuit node under the multiple input scenarios, it is determined that a high-impedance state exists between the selected circuit node and the at least one power supply terminal.

For example, in step S50, determining whether a conductive path exists between at least one power source terminal and the selected circuit node under a plurality of input scenarios based on the plurality of equivalent models may include: traversing the plurality of equivalent models for each selected power supply terminal of the at least one power supply terminal, and performing conduction path detection on each selected equivalent model; wherein, the conduction path detection includes: in the selected equivalent model, in response to the existence of the shortest circuit path between the selected power supply end and the selected circuit node, judging whether the shortest circuit path is a conduction path or not, in response to the fact that the shortest circuit path is the conduction path, determining that the conduction path exists between the selected power supply end and the selected circuit node under the input scene corresponding to the selected equivalent model, in response to the fact that the shortest circuit path is not the conduction path or in response to the fact that the shortest circuit path does not exist between the selected power supply end and the selected circuit node, determining that the conduction path does not exist between the selected power supply end and the selected circuit node under the input scene corresponding to the selected equivalent model, and continuing to detect the conduction path of the next equivalent model.

For example, determining whether the shortest circuit path is a conductive path may include: calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value corresponding to at least one equivalent edge included in the shortest circuit path; determining that the shortest circuit path is a conduction path in response to the equivalent path sum being equal to a first value; and determining that the shortest circuit path is not a conduction path in response to the equivalent path sum not being equal to the first value.

As for the method for determining the conduction path, reference may be made to the method for determining the short-circuit path as described above, and details thereof are not repeated here.

For example, as shown in fig. 1B, the circuit includes a power source terminal VDD1 and a power source terminal VDD2, p input scenarios corresponding to the circuit shown in fig. 1B and p equivalent models corresponding to the p input scenarios, respectively, are determined according to steps S10 to S40, for example, the p input scenarios are input scenarios 1 'to p', the p equivalent models are equivalent models 1 'to p', respectively, and p is a positive integer.

In performing the high-resistance state check between the power source terminal VDD1 and the selected circuit node, the plurality of equivalent models are traversed, and the conduction path detection is performed for each equivalent model.

First, conduction path detection is performed on the equivalent model 1'. Specifically, if the power supply terminal VDD1 is the selected power supply terminal, using the power supply terminal VDD1 as the starting point and the selected circuit node as the end point, any feasible path algorithm is used to determine whether the shortest circuit path exists from the starting point to the end point in the equivalent model 1'; if the shortest circuit path exists, judging whether the shortest circuit path is a conducting path, specifically, if the shortest circuit path is a conducting path, determining that a conducting path exists between the power supply terminal VDD1 and the selected circuit node under the input scene 1', the selected circuit node does not have a high-resistance state, and ending the high-resistance state check between the power supply terminal VDD1 and the selected circuit node; if the shortest circuit path does not exist or the shortest circuit path is not a conduction path, it is determined that a conduction path does not exist between the power supply terminal VDD1 and the selected circuit node in the input scenario 1 ', and the detection and judgment of the conduction path are continuously performed on the next equivalent model, for example, the equivalent model 2', until p equivalent models are traversed.

If no conducting path exists between the power supply terminal VDD1 and the selected circuit node in the p equivalent models, the power supply terminal VDD2 is used as the selected power supply terminal to continue to perform the high-impedance state check between the power supply terminal VDD2 and the selected circuit node, and the detailed process is not repeated. If there is also no conductive path between the power supply terminal VDD2 and the selected circuit node, it is determined that a high-impedance state exists between the selected circuit node and the power supply terminal.

For example, after determining that the selected circuit node has a high impedance state, the selected circuit node may be recorded and provided to a circuit designer, and the circuit designer may accurately position the relevant circuit element according to the information to perform inspection and modification, thereby improving the efficiency of the inspection and modification of the circuit.

For example, when the circuit is checked to be in the high-impedance state, whether a conducting path exists between each circuit node and the ground terminal in all input scenes can be checked, and if no conducting path exists between a certain circuit node and the ground terminal in all input scenes, the circuit node is in the high-impedance state, and the circuit has the problem of the high-impedance state.

For example, step S50 may further include: for each selected circuit node of the plurality of circuit nodes: determining whether a conduction path exists between the grounding end and the selected circuit node under a plurality of input scenes based on a plurality of equivalent circuits; in response to the fact that a conducting path exists between the grounding end and the selected circuit node under any input scene, determining that a high-resistance state does not exist between the selected circuit node and the grounding end; and determining that a high-impedance state exists between the selected circuit node and the ground terminal in response to the fact that no conducting path exists between the ground terminal and the selected circuit node under the plurality of input scenes.

The inspection of the high impedance state between the circuit node and the ground terminal is similar to the inspection of the high impedance state between the circuit node and the power source terminal, and is not described herein again.

The following describes a process of performing a high resistance state check on a circuit according to at least one embodiment of the present disclosure with reference to fig. 1B and fig. 3B.

For example, as shown in fig. 3B, taking the circuit node net _ y4 as an example, at this time, the circuit node net _ y4 is a selected circuit node, and it is checked whether a high impedance state exists between the circuit node net _ y4 and the power source terminal.

For example, with respect to the equivalent model shown in fig. 3B, the power source terminal VDD1 is the selected power source terminal, and at this time, the shortest circuit path from the start point to the end point in the equivalent model is determined by using any feasible path algorithm with the equivalent node VDD1 corresponding to the power source terminal VDD1 as the start point and the equivalent node net _ y4 corresponding to the circuit node net _ y4 as the end point. As shown in fig. 3B, if there is no shortest circuit path between the equivalent node net _ y4 and the equivalent node VDD1, it is determined that there is no conducting path between the circuit node net _ y4 and the power source terminal VDD1 in the input scenario corresponding to the equivalent model shown in fig. 3B. After traversing all equivalent models, there is no conductive path between the equivalent node net _ y4 and the equivalent node VDD 1. Taking the power supply terminal VDD2 as the selected power supply terminal, then, a high impedance state check is performed on the power supply terminal VDD2 and the circuit node net _ y4, which is not described in detail again. Finally, after traversing all the equivalent models, no conducting path exists between the equivalent node net _ y4 and the equivalent node VDD2, and it is determined that a high-impedance state exists between the circuit node net _ y4 and the power supply end.

Then, the high impedance state between the circuit node net _ y4 and the power supply terminal is recorded, and the existence of the high impedance state between the circuit node net _ y4 and the power supply terminal is marked and provided to a circuit designer, so that the circuit designer can check the corresponding circuit elements in combination with the information to modify the circuit.

For example, as shown in fig. 3B, taking the circuit node net _ y2 as an example, the circuit node net _ y2 is the selected circuit node, and it is checked whether a high impedance state exists between the circuit node net _ y2 and the ground.

For example, with respect to the equivalent model shown in fig. 3B, the shortest circuit path from the start point to the end point in the equivalent model is determined by using any feasible path algorithm, with the equivalent node net _ y2 corresponding to the circuit node net _ y2 as the start point and the equivalent node VSS corresponding to the ground terminal VSS as the end point. As shown in fig. 3B, if the shortest circuit path does not exist between the equivalent node net _ y2 and the terminal of the equivalent node VSS, it is determined that a conductive path does not exist between the circuit node net _ y2 and the ground terminal in the input scenario corresponding to the equivalent model shown in fig. 3B. After traversing all the equivalent models, no conducting path exists between the equivalent node net _ y2 and the equivalent node VSS terminal, and a high-impedance state exists between the circuit node net _ y2 and the ground terminal.

And then, recording the circuit node net _ y2, marking the high-impedance state between the circuit node net _ y2 and the grounding terminal, and providing the high-impedance state to a circuit designer, so that the circuit designer can check the corresponding circuit element by combining the information to modify the circuit.

The circuit inspection method provided by at least one embodiment of the present disclosure provides a new idea to perform circuit inspection, that is, the circuit is simplified into an equivalent model, and then the circuit is inspected based on the equivalent model, so that the correctness and reliability of the circuit design are greatly ensured, the product design iteration time caused by circuit leaks is reduced, and a third-party tool is not needed, so that the quick and effective circuit inspection can be realized, and circuit designers can be helped to find circuit problems, such as short-circuit problems and high-impedance problems, in time.

Fig. 4 is a flowchart of a circuit inspection method according to at least one embodiment of the present disclosure.

As shown in fig. 4, the circuit check includes two parts, a short circuit check and a high resistance state check. For example, the short circuit inspection is performed on the circuit first, then the high impedance state inspection is performed on the circuit, and the recorded inspection result is provided to the circuit designer in a file, a popup window or the like, so that the circuit designer can modify the circuit.

A specific implementation process of the circuit inspection method according to at least one embodiment of the present disclosure is specifically described below with reference to fig. 4.

As shown in fig. 4, first, a plurality of circuit nodes are determined. The specific process may refer to the relevant content of step S10, and repeated details are not repeated.

Then, a plurality of input scenes corresponding to the circuit are determined. The specific process may refer to the relevant content of step S20, and repeated details are not repeated.

And then, determining element states corresponding to the circuit elements in each input scene. The specific process may refer to the relevant content of step S30, and repeated details are not repeated.

Then, an equivalent model corresponding to the circuit under each input scene is determined. The specific process may refer to the relevant content of step S40, and repeated details are not repeated.

Thereafter, all the power source terminals and the ground terminals are subjected to short circuit inspection. For example, for a selected power source terminal in at least one power source terminal included in the circuit, all input scenes are traversed, for each input scene, whether a short-circuit path exists between the selected power source terminal and a ground terminal in an equivalent model corresponding to the input scene is determined, if so, short-circuit information of the input scene, the short-circuit path and the like is recorded, and if not, the judgment is continuously performed on the equivalent model corresponding to the next input scene until all the input scenes are traversed. The details of the short circuit check refer to the related description of step S50, and are not described herein again.

If the circuit includes a power supply terminal, it is determined that the short circuit inspection is completed.

If the circuit includes a plurality of power source terminals, the above-mentioned short-circuit check is performed for any one of the plurality of power source terminals included in the circuit other than the above-mentioned selected power source terminal until the above-mentioned short-circuit check is performed for all the power source terminals. Thereafter, a high impedance state check is performed on all circuit nodes.

For example, a high-resistance state check between the selected circuit node and the ground terminal and a high-resistance state check between the selected circuit node and the power source terminal are performed in parallel for the selected circuit node.

For example, for the high-resistance state check between the selected circuit node and the ground terminal, it is determined whether a conduction path exists between the selected circuit node and the ground terminal in any input scenario, if no conduction path exists in all input scenarios, the selected circuit node is recorded, and the high-resistance state check between the selected circuit node and the ground terminal is performed on the next circuit node; if a conduction path exists in any input scene, determining that the selected circuit node and the grounding terminal do not have a high-resistance state, and continuously executing the high-resistance state check between the next circuit node and the grounding terminal until all the circuit nodes are traversed.

For example, for the high-resistance state check between the selected circuit node and the power supply end, whether a conducting path exists between the selected circuit node and all the power supply ends in any input scene is judged, if the conducting path does not exist in all the input scenes, the selected circuit node is recorded, the high-resistance state check between the selected circuit node and the power supply end is carried out on the next circuit node, if the conducting path exists in any input scene, the selected circuit node and the power supply end do not exist in a high-resistance state, and the high-resistance state check between the selected circuit node and the power supply end is continuously carried out on the next circuit node until all the circuit nodes are traversed and completed. The details of the high impedance state check refer to the related description of step S50, and are not described herein again.

It should be noted that fig. 4 is only a schematic description, and the present disclosure does not limit the inspection sequence of the circuit, for example, the inspection of the high resistance state may be performed first, and then the inspection of the short circuit is performed; for example, in the high-resistance state check, the high-resistance state check between the selected circuit node and the ground terminal and the high-resistance state check between the selected circuit node and the power terminal may be performed in series, for example, whether a high-resistance state exists between the circuit node and the power terminal may be checked first, and then whether a high-resistance state exists between the circuit node and the ground terminal may be checked, or whether a high-resistance state exists between the circuit node and the ground terminal may be checked first, and then whether a high-resistance state exists between the circuit node and the power terminal may be checked.

Corresponding to the circuit inspection method described above, at least one embodiment of the present disclosure further provides an apparatus for inspecting a circuit, and fig. 5 is a schematic block diagram of an apparatus for inspecting a circuit provided by at least one embodiment of the present disclosure.

For example, as shown in fig. 5, the circuit inspection apparatus 500 includes: a node determination unit 501, an input scene determination unit 502, an element state determination unit 503, an equivalent model determination unit 504, and a check unit 505.

A node determination unit 501 is configured to determine a plurality of circuit nodes. For example, each circuit node represents a point to which at least one circuit element is connected.

An input scene determination unit 502 configured to determine a plurality of input scenes to which the circuit corresponds. For example, each input scenario includes a plurality of signal states respectively corresponding to the input terminals.

An element state determination unit 503 configured to determine element states corresponding to the plurality of circuit elements in each of the plurality of input scenarios.

The equivalent model determining unit 504 is configured to determine an equivalent model corresponding to the circuit in the selected input scenario according to the element states corresponding to the plurality of circuit elements in the selected input scenario and the plurality of circuit nodes.

The inspection unit 505 is configured to perform circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under a plurality of input scenarios.

For example, the equivalent model determining unit 504 performs the following operations when determining the equivalent model corresponding to the circuit in the selected input scenario according to the element states corresponding to the circuit elements in the selected input scenario and the circuit nodes: taking a plurality of circuit nodes, a grounding terminal and at least one power supply terminal as a plurality of equivalent nodes of an equivalent model corresponding to the circuit under the selected input scene; taking a plurality of circuit elements as a plurality of equivalent edges in an equivalent model corresponding to the circuit under the selected input scene, wherein each equivalent edge is used for connecting two equivalent nodes in the equivalent model corresponding to the circuit under the selected input scene; and determining equivalent path values corresponding to the equivalent edges respectively based on element states corresponding to the circuit elements, wherein in response to the element state of the circuit element being a conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a first value, in response to the element state of the circuit element being a non-conducting state, the equivalent path value corresponding to the equivalent edge corresponding to the circuit element is a second value, and the first value and the second value are different.

For example, the checking unit 505 performs the circuit checking on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under a plurality of input scenarios, and the following operations are performed: determining at least one check group based on the ground terminal and the at least one power terminal, wherein each check group includes one of the ground terminal and the at least one power terminal; and traversing a plurality of equivalent models for each selected checking group, determining whether a short-circuit path exists between the power supply end and the ground end in the selected checking group in each selected equivalent model, and responding to the short-circuit path existing between the power supply end and the ground end in the selected checking group, wherein the determining circuit has the short-circuit problem in the input scene corresponding to the selected equivalent model.

For example, the checking unit 505 performs the circuit checking based on a plurality of equivalent models respectively corresponding to the circuits under a plurality of input scenarios, and further performs the following operations when performing the circuit checking on the circuits: for each selected circuit node of the plurality of circuit nodes: determining whether a conductive path exists between at least one power supply terminal and the selected circuit node under a plurality of input scenarios based on a plurality of equivalent models; in response to a conductive path existing between either power supply terminal and the selected circuit node in either of the input scenarios, determining that a high-impedance state does not exist between the selected circuit node and at least one power supply terminal; in response to no conductive path existing between at least one power supply terminal and the selected circuit node under the multiple input scenarios, it is determined that a high-impedance state exists between the selected circuit node and the at least one power supply terminal.

For example, the checking unit 505 performs the circuit checking based on a plurality of equivalent models respectively corresponding to the circuits under a plurality of input scenarios, and further performs the following operations when performing the circuit checking on the circuits: for each selected circuit node of the plurality of circuit nodes: determining whether a conduction path exists between a grounding end and a selected circuit node under a plurality of input scenes based on a plurality of equivalent circuits; in response to the fact that a conducting path exists between the grounding end and the selected circuit node under any input scene, determining that a high-resistance state does not exist between the selected circuit node and the grounding end; and determining that a high-impedance state exists between the selected circuit node and the ground terminal in response to the fact that no conducting path exists between the ground terminal and the selected circuit node under the plurality of input scenes.

For example, the node determining unit 501, the input scene determining unit 502, the element state determining unit 503, the equivalent model determining unit 504, and the checking unit 505 include codes and programs stored in a memory; the processor may execute the code and the program to realize some or all of the functions of the node determining unit 501, the input scene determining unit 502, the element state determining unit 503, the equivalent model determining unit 504, and the checking unit 505 as described above. For example, the node determining unit 501, the input scenario determining unit 502, the element state determining unit 503, the equivalent model determining unit 504, and the checking unit 505 may be dedicated hardware devices for implementing some or all of the functions of the node determining unit 501, the input scenario determining unit 502, the element state determining unit 503, the equivalent model determining unit 504, and the checking unit 505 as described above. For example, the node determining unit 501, the input scenario determining unit 502, the element state determining unit 503, the equivalent model determining unit 504, and the checking unit 505 may be one circuit board or a combination of a plurality of circuit boards for realizing the functions as described above. In an embodiment of the present application, the one or a combination of the plurality of circuit boards may include: (1) one or more processors; (2) one or more non-transitory memories connected to the processor; and (3) firmware stored in the memory executable by the processor.

It should be noted that the node determining unit 501 is configured to implement step S10 shown in fig. 2, the input scenario determining unit 502 is configured to implement step S20 shown in fig. 2, the element state determining unit 503 is configured to implement step S30 shown in fig. 2, the equivalent model determining unit 504 is configured to implement step S40 shown in fig. 2, and the checking unit 505 is configured to implement step S50 shown in fig. 2. Thus, for the specific description of the node determining unit 501, the description related to step S10 shown in fig. 2 in the embodiment of the circuit inspection method, the description related to step S20 shown in fig. 2 in the embodiment of the circuit inspection method, the description related to step S30 shown in fig. 2 in the embodiment of the circuit inspection method, the description related to step S40 shown in fig. 2 in the embodiment of the circuit inspection method, the description related to step S50 shown in fig. 2 in the embodiment of the circuit inspection method, and the description related to step S50 shown in fig. 2 in the embodiment of the circuit inspection method may be referred to for the specific description of the element state determining unit 503.

At least one embodiment of the present disclosure provides an inspection apparatus for a circuit, which can achieve similar technical effects to the aforementioned inspection method for a circuit. The circuit is simplified into the equivalent model by the circuit checking device, then circuit checking is carried out on the circuit based on the equivalent model, the correctness and the reliability of circuit design are greatly guaranteed, the product design iteration time caused by circuit leaks is reduced, quick and effective circuit checking can be realized without the aid of a third-party tool, and circuit designers are helped to find circuit problems in time, such as short circuit problems and high impedance problems.

At least one embodiment of the present disclosure further provides an electronic device, and fig. 6 is a schematic block diagram of an electronic device provided in at least one embodiment of the present disclosure.

For example, as shown in fig. 6, the electronic apparatus includes a processor 1001, a communication interface 1002, a memory 1003, and a communication bus 1004. The processor 1001, the communication interface 1002, and the memory 1003 communicate with each other via the communication bus 1004, and components such as the processor 1001, the communication interface 1002, and the memory 1003 may communicate with each other via a network connection. The present disclosure is not limited herein as to the type and function of the network.

For example, memory 1003 is used to store computer-executable instructions non-transiently. When the processor 1001 is configured to execute the computer-executable instructions, the computer-executable instructions are executed by the processor 1001 to implement the circuit checking method according to any of the above embodiments. For specific implementation and related explanation of each step of the circuit inspection method, reference may be made to the above embodiments of the circuit inspection method, which are not described herein again.

For example, the implementation manner of the circuit inspection method implemented by the processor 1001 executing the program stored in the memory 1003 is the same as the implementation manner mentioned in the foregoing embodiment of the circuit inspection method, and is not described herein again.

For example, the communication bus 1004 may be a peripheral component interconnect standard (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.

For example, communication interface 1002 is used to enable communication between an electronic device and other devices.

For example, the processor 1001 and the memory 1003 may be provided on a server side (or a cloud side).

For example, the processor 1001 may control other components in the electronic device to perform desired functions. The processor 1001 may be a Central Processing Unit (CPU), a Network Processor (NP), etc., and may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. The Central Processing Unit (CPU) may be an X86 or ARM architecture, etc.

For example, memory 1003 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and/or non-volatile memory. Volatile memory can include, for example, Random Access Memory (RAM), cache memory (or the like). The non-volatile memory may include, for example, Read Only Memory (ROM), hard disk, Erasable Programmable Read Only Memory (EPROM), portable compact disk read only memory (CD-ROM), USB memory, flash memory, and the like. On which one or more computer-executable instructions may be stored and executed by the processor 1001 to implement various functions of the electronic device. Various application programs and various data and the like can also be stored in the storage medium.

For example, for detailed description of the process of the electronic device performing the inspection of the circuit, reference may be made to the related description in the embodiment of the inspection method of the circuit, and repeated descriptions are omitted.

Fig. 7 is a schematic diagram of a non-transitory computer-readable storage medium according to at least one embodiment of the disclosure. For example, as shown in fig. 7, one or more computer-executable instructions 1101 may be non-temporarily stored on a storage medium 1100. For example, the computer-executable instructions 1101, when executed by a processor, may perform one or more steps of an inspection method according to the circuitry described above.

For example, the storage medium 1100 may be applied to the inspection apparatus 1400 of the electronic device and/or circuit described above. For example, the storage medium 1100 may include the memory 1003 in the electronic device.

For example, the description of the storage medium 1100 may refer to the description of the memory in the embodiment of the electronic device, and repeated descriptions are omitted.

For the present disclosure, there are also the following points to be explained:

(1) the drawings of the embodiments of the disclosure only relate to the structures related to the embodiments of the disclosure, and other structures can refer to the common design.

(2) Thicknesses and dimensions of layers or structures may be exaggerated in the drawings used to describe embodiments of the present invention for clarity. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

(3) Without conflict, embodiments of the present disclosure and features of the embodiments may be combined with each other to arrive at new embodiments.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and the scope of the present disclosure should be subject to the scope of the claims.

Claims

1. An inspection method of a circuit, wherein the circuit comprises a plurality of circuit elements and a plurality of input terminals, the inspection method comprising:

determining a plurality of circuit nodes, wherein each circuit node represents a point of connection with at least one circuit element;

determining a plurality of input scenes corresponding to the circuit, wherein each input scene comprises signal states corresponding to the plurality of input ends respectively;

determining element states corresponding to the plurality of circuit elements in each of the plurality of input scenarios that is selected;

determining an equivalent model corresponding to the circuit in the selected input scene according to the element states respectively corresponding to the circuit elements in the selected input scene and the circuit nodes;

and performing circuit check on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenes.

2. The inspection method of claim 1, wherein each equivalent model comprises a plurality of equivalent nodes and a plurality of equivalent edges,

the circuit further comprises a ground terminal and at least one power terminal, the element state of each circuit element comprises a conducting state or a non-conducting state,

determining an equivalent model corresponding to the circuit in the selected input scenario according to the element states respectively corresponding to the plurality of circuit elements in the selected input scenario and the plurality of circuit nodes, including:

taking the plurality of circuit nodes, the ground terminal and the at least one power terminal as a plurality of equivalent nodes of an equivalent model corresponding to the circuit in the selected input scenario;

the multiple circuit elements are used as multiple equivalent edges in an equivalent model corresponding to the circuit under the selected input scene, wherein each equivalent edge is used for connecting two equivalent nodes in the equivalent model corresponding to the circuit under the selected input scene;

determining equivalent path values corresponding to the equivalent edges based on element states corresponding to the circuit elements,

the method comprises the steps of responding to the condition that the element state of a circuit element is a conduction state, setting an equivalent path value corresponding to an equivalent edge corresponding to the circuit element to be a first value, responding to the condition that the element state of the circuit element is a non-conduction state, setting the equivalent path value corresponding to the equivalent edge corresponding to the circuit element to be a second value, and setting the first value and the second value to be different.

3. The inspection method according to claim 2, wherein performing circuit inspection on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenarios comprises:

determining at least one check group based on the ground terminal and the at least one power terminal, wherein each check group includes one of the ground terminal and the at least one power terminal;

traversing the plurality of equivalent models for each selected check group, determining whether a short circuit path exists between a power terminal and the ground terminal in the selected check group in each selected equivalent model,

and determining that the circuit has a short-circuit problem in the input scene corresponding to the selected equivalent model in response to the fact that a short-circuit path exists between the power supply terminal and the ground terminal in the selected check group.

4. The inspection method of claim 3, wherein determining whether a short circuit path exists between the power terminals and the ground terminals in the selected inspection set in each selected equivalent model comprises:

determining whether a shortest circuit path exists between a power terminal and the ground terminal in the selected check group,

in response to a shortest circuit path existing between a power terminal and the ground terminal in the selected check group,

calculating the equivalent path sum corresponding to the shortest circuit path according to at least one equivalent path value corresponding to at least one equivalent edge included in the shortest circuit path;

judging whether the shortest circuit path is a short-circuit path or not according to the equivalent path sum;

determining that a short circuit path does not exist between the power supply terminals in the selected check group and the ground terminal in response to the shortest circuit path not existing between the power supply terminals in the selected check group and the ground terminal.

5. An inspection method according to claim 4, wherein the equivalent path sum is a sum of the at least one equivalent path value or a weighted sum of the at least one equivalent path value.

6. The inspection method according to claim 4, wherein the first value is 0,

judging whether the shortest circuit path is a short circuit path according to the equivalent path sum, comprising:

determining that the shortest circuit path is a short circuit path in response to the equivalent path sum being equal to the first value;

in response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a shorted path.

7. The inspection method according to claim 3, further comprising:

and in response to the shortest circuit path being a short-circuit path, recording the shortest circuit path, the input scene corresponding to the selected equivalent model, and the power supply end and the ground end included in the selected check group.

8. The inspection method according to claim 2, wherein the circuit further comprises at least one power supply terminal,

performing a circuit check on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenarios, including:

for each selected circuit node of the plurality of circuit nodes:

determining whether a conductive path exists between the at least one power terminal and the selected circuit node under the plurality of input scenarios based on the plurality of equivalent models;

in response to a conductive path existing between either power supply terminal and the selected circuit node in either input scenario, determining that a high-impedance state does not exist between the selected circuit node and the at least one power supply terminal;

determining that a high state exists between the selected circuit node and the at least one power source terminal in response to no conductive path existing between the at least one power source terminal and the selected circuit node in the plurality of input scenarios.

9. The inspection method according to claim 8, wherein determining whether a conductive path exists between the at least one power terminal and the selected circuit node under the plurality of input scenarios based on the plurality of equivalent models comprises:

for each selected one of the at least one power terminals, traversing the plurality of equivalent models, performing a conduction path detection on each selected equivalent model;

wherein the conduction path detection comprises:

in the selected equivalent model, the equivalent model is selected,

determining whether a shortest circuit path exists between the selected power terminal and the selected circuit node in response to the shortest circuit path being a conduction path,

determining that a conductive path exists between the selected power source terminal and the selected circuit node in an input scenario corresponding to the selected equivalent model in response to the shortest circuit path being a conductive path,

in response to the shortest circuit path not being a conducting path or in response to the shortest circuit path not existing between the selected power source terminal and the selected circuit node, determining that a conducting path does not exist between the selected power source terminal and the selected circuit node in an input scenario corresponding to the selected equivalent model, and continuing to perform the conducting path detection on a next equivalent model.

10. The inspection method according to claim 9, wherein the first value is 0,

judging whether the shortest circuit path is a conduction path or not, including:

determining that the shortest circuit path is a conductive path in response to the equivalent path sum being equal to the first value;

in response to the equivalent path sum not being equal to the first value, determining that the shortest circuit path is not a conductive path.

11. The inspection method according to claim 2, wherein the circuit further includes a ground terminal,

for each selected circuit node of the plurality of circuit nodes:

determining whether a conduction path exists between the ground terminal and the selected circuit node under the plurality of input scenes based on the plurality of equivalent circuits;

in response to a conducting path existing between the ground terminal and the selected circuit node in any input scenario, determining that a high-impedance state does not exist between the selected circuit node and the ground terminal;

and determining that a high-impedance state exists between the selected circuit node and the ground terminal in response to no conducting path existing between the ground terminal and the selected circuit node under the plurality of input scenes.

12. The inspection method of any one of claims 1-11, wherein each input has a first signal state and a second signal state, the first signal state and the second signal state being different,

determining a plurality of input scenarios corresponding to the circuit, including:

combining signal states of the plurality of inputs, determining the plurality of input scenarios,

wherein the number of the plurality of input ends is N, and the number of the plurality of input scenes is 2^N，

N is a positive integer.

13. The inspection method according to any one of claims 1 to 11, wherein the plurality of circuit elements includes a plurality of first circuit elements connected to the plurality of input terminals,

determining element states corresponding to the plurality of circuit elements in each selected input scenario of the plurality of input scenarios, including:

determining the signal states respectively corresponding to the plurality of input ends under the selected input scene;

and determining element states corresponding to the plurality of first circuit elements under the selected input scene according to the signal states corresponding to the plurality of input ends respectively.

14. The inspection method according to any one of claims 1 to 11, wherein the circuit is a digital circuit,

determining the plurality of circuit nodes, comprising:

obtaining a netlist corresponding to the circuit;

and determining the plurality of circuit nodes according to the netlist.

15. An inspection method according to any one of claims 1 to 11, wherein the circuit is a cell circuit of a standard cell library.

16. The inspection method according to any one of claims 1 to 11, wherein each circuit element is a transistor or a resistor.

17. An inspection apparatus for a circuit, the circuit comprising a plurality of circuit elements and a plurality of input terminals,

the inspection apparatus includes:

a node determination unit configured to determine a plurality of circuit nodes, wherein each circuit node represents a point to which at least one circuit element is connected;

an input scene determining unit configured to determine a plurality of input scenes corresponding to the circuit, wherein the plurality of input scenes comprise signal states corresponding to the plurality of input ends respectively;

an element state determination unit configured to determine element states to which the plurality of circuit elements respectively correspond in each of the plurality of input scenarios selected;

an equivalent model determination unit configured to determine an equivalent model corresponding to the circuit in the selected input scenario according to element states respectively corresponding to the plurality of circuit elements in the selected input scenario and the plurality of circuit nodes;

a checking unit configured to perform circuit checking on the circuit based on a plurality of equivalent models respectively corresponding to the circuit under the plurality of input scenarios.

18. An electronic device, comprising:

a memory non-transiently storing computer executable instructions;

a processor configured to execute the computer-executable instructions,

wherein the computer-executable instructions, when executed by the processor, implement a method of inspection of the circuit of any of claims 1-16.

19. A non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer-executable instructions,

the computer executable instructions when executed by a processor implement a method of inspection of a circuit according to any of claims 1 to 16.