CN114090482B - Delay counteracting method for transmission data - Google Patents

Delay counteracting method for transmission data Download PDF

Info

Publication number
CN114090482B
CN114090482B CN202111146452.7A CN202111146452A CN114090482B CN 114090482 B CN114090482 B CN 114090482B CN 202111146452 A CN202111146452 A CN 202111146452A CN 114090482 B CN114090482 B CN 114090482B
Authority
CN
China
Prior art keywords
data
clock signal
preset period
pulse
pulse waves
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111146452.7A
Other languages
Chinese (zh)
Other versions
CN114090482A (en
Inventor
葛锐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rongpai Semiconductor Shanghai Co ltd
Original Assignee
Rongpai Semiconductor Shanghai Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rongpai Semiconductor Shanghai Co ltd filed Critical Rongpai Semiconductor Shanghai Co ltd
Priority to CN202111146452.7A priority Critical patent/CN114090482B/en
Publication of CN114090482A publication Critical patent/CN114090482A/en
Application granted granted Critical
Publication of CN114090482B publication Critical patent/CN114090482B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14Handling requests for interconnection or transfer
    • G06F13/20Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)

Abstract

The invention discloses a delay counteracting method for transmitting data, which belongs to the technical field of data communication and comprises the following steps: step S1, outputting a clock signal according to a preset rule according to the rising edge and/or the falling edge of a data signal to be transmitted, wherein the clock signal comprises a plurality of pulse waves; step S2, decoding is carried out according to the interval between pulse waves of the clock signal, so as to obtain a data signal to be transmitted according to the clock signal. The invention has the beneficial effects that: the invention eliminates the improvement scheme of the prior art on the basis of data transmission, only one transmission path is needed, the transmission path transmits clock signals instead of data signals, clock pulses are transmitted according to the rising edge and/or the falling edge of the data signals, the data signals are decoded at the receiving end according to the pulse interval of the received clock signals, and the delay of the transmission path is fixed by adopting the same-edge transmission method, so that the delay is counteracted, and the phenomenon of pulse width distortion is avoided.

Description

Delay counteracting method for transmission data
Technical Field
The present invention relates to the field of data communication technologies, and in particular, to a delay cancellation method for transmission data.
Background
The pulse width distortion PWD refers to the maximum difference between the delay time Tr from low level to high level and the delay time Tf from high level to low level, and characterizes the accuracy of the signal remaining the same after the signal is output by the device. As shown in fig. 1, when two chips transmit data through a transmission path, the delay of the rising edge and the falling edge is not matched, so that a pulse width distortion phenomenon is generated, referring to fig. 2, the low-level to high-level delay Tr refers to the time difference between the rising edge of the signal input end and the rising edge of the signal output end, the high-level to low-level delay Tf refers to the time difference between the falling edge of the signal input end and the falling edge of the signal output end, and the pulse width distortion pwd= |tr-tf|.
In the scheme adopted in the prior art, for example, one scheme needs to add one transmission channel, as shown in fig. 3a, by adding one clock transmission path between two chips and simultaneously transmitting data and a clock, at a receiving end (rx end), data is grabbed again according to a clock signal CLK (retiming), and the scheme is transmitted by multiple clock paths, so that the cost is increased; in another scheme, as shown in fig. 3b, a Clock Data Recovery (CDR) circuit is disposed at a receiving end, the clock and the data are contained in a data stream, and the clock synchronization signal is transmitted to the other party while the code information is transmitted. In view of the above problems, it is highly desirable to design a delay cancellation method for transmitting data to meet the needs of practical use.
Disclosure of Invention
In order to solve the technical problems, the invention provides a delay counteracting method for transmitting data.
The technical problems solved by the invention can be realized by adopting the following technical scheme:
A delay cancellation method of transmission data, comprising:
Step S1, outputting a clock signal according to a preset rule according to the rising edge and/or the falling edge of a data signal to be transmitted, wherein the clock signal comprises a plurality of pulse waves;
and step S2, decoding according to the interval between pulse waves of the clock signal so as to obtain the data signal to be transmitted according to the clock signal.
Preferably, in the step S1, the preset rule includes:
transmitting first pulse waves of the clock signal from the rising edge of the data signal, wherein the time interval between two adjacent first pulse waves is a first preset period;
Transmitting second pulse waves of the clock signal from the falling edge of the data signal, wherein the time interval between two adjacent second pulse waves is a second preset period;
The pulse wave of the clock signal includes the first pulse wave and the second pulse wave.
Preferably, a time interval between a last first pulse wave of the plurality of first pulse waves having a time interval of a first preset period and an adjacent first one of the second pulse waves is greater than the first preset period or equal to the second preset period.
Preferably, in the step S2, the method specifically includes:
step S21A, comparing the time interval between two adjacent pulse waves in the clock signal with a preset period threshold;
Step S22A, decoding the first pulse wave received from the first time interval to first decoded data when the time interval is smaller than or equal to the first preset period; and
Decoding the first pulse wave received from the first pulse wave into second decoded data when the time interval is larger than the first preset period and smaller than or equal to the second preset period;
step S23A, obtaining the data signal according to the decoded data decoded by all adjacent two pulse waves in the clock signal.
Preferably, in the step S1, the preset rule includes:
Transmitting pulse waves of the clock signal from the rising edge of the data signal, wherein the time interval between two adjacent pulse waves is a first preset period;
and stopping transmitting the pulse wave of the clock signal from the falling edge of the data signal.
Preferably, a time interval between last two pulse waves of the plurality of pulse waves is less than or equal to the first preset period.
Preferably, in the step S2, the method specifically includes:
step S21B, determining whether the clock signal has a pulse wave in a second preset period:
If so, decoding the interval second preset period after the pulse wave is received into first decoded data;
If not, decoding an interval second preset period after the last pulse in a plurality of pulse waves with the time interval being the first preset period into second decoded data;
Step S22B, obtaining the data signal according to the decoded data decoded in all the second preset periods in the second clock signal.
Preferably, in the step S2, the method further includes:
and when the time interval between the two pulse waves is larger than a third preset period, setting the decoded data as default decoded data, wherein the default decoded data is identical to the second decoded data.
Preferably, the third preset period is greater than the second preset period;
the second preset period is greater than the first preset period.
The invention has the beneficial effects that:
The invention eliminates the improvement scheme of the prior art on the basis of data transmission, only one transmission path is needed, the transmission path transmits clock signals instead of data signals, clock pulses are transmitted according to the rising edge and/or the falling edge of the data signals, the data signals are decoded at the receiving end according to the pulse interval of the received clock signals, and the delay of the transmission path is fixed by adopting the same-edge transmission method, so that the delay is counteracted, and the phenomenon of pulse width distortion is avoided.
Drawings
Fig. 1 is a schematic diagram of a data transmission structure in the prior art;
FIG. 2 is a timing diagram of pulse width distortion generated during data transmission using the method of FIG. 1 in the prior art;
FIG. 3a is a schematic diagram of one solution to the impulse distortion in the prior art;
FIG. 3b is a schematic diagram of another prior art solution to impulse distortion;
FIG. 4 is a schematic diagram of a delay cancellation method for implementing a data transmission in accordance with the present invention;
FIG. 5 is a flow chart of a delay canceling method for transmitting data according to the present invention;
FIG. 6 is a flowchart of a first embodiment of the step S2;
FIGS. 7a-7c are timing diagrams illustrating a first embodiment of the present invention;
FIG. 8 is a flowchart of a second embodiment of the step S2;
Fig. 9a-9c are timing diagrams of a second embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that, without conflict, the embodiments of the present invention and features of the embodiments may be combined with each other.
The invention is further described below with reference to the drawings and specific examples, which are not intended to be limiting.
The invention provides a delay counteracting method for transmission data, which belongs to the technical field of data communication, as shown in fig. 4 and 5, and comprises the following steps:
step S1, outputting a clock signal according to a preset rule according to the rising edge and/or the falling edge of a data signal to be transmitted, wherein the clock signal comprises a plurality of pulse waves;
Step S2, decoding is carried out according to the interval between pulse waves of the clock signal, so as to obtain a data signal to be transmitted according to the clock signal.
Considering that the phenomenon that the data will be distorted in pulse width when the data is transmitted, in the existing scheme, a clock transmission path is required to be added or a CDR circuit is added, aiming at the problems existing in the prior art, in the invention, clock pulses (namely clock signals formed by pulse waves) are transmitted according to the rising edge and/or the falling edge of the data signals, and the data signals are decoded at the receiving end according to the pulse intervals (namely the intervals between the pulse waves) of the received clock signals.
Based on the principle that the transmission path delay is fixed by converting the existing transmission data into the transmission clock pulse and extracting the data from the clock signal, and the transmission clock pulse can be selected to be the same as the rising edge transmission (or the falling edge transmission), two specific examples of the two possible embodiments are presented.
Embodiment one:
in a preferred embodiment of the present invention, as shown in fig. 7a, in step S1, the preset rule includes:
The method comprises the steps of starting to send first pulse waves of a clock signal from the rising edge of a data signal, wherein the time interval between two adjacent first pulse waves is a first preset period T1;
transmitting second pulse waves of the clock signal from the falling edge of the data signal, wherein the time interval between two adjacent second pulse waves is a second preset period T2;
The pulse wave of the clock signal includes a first pulse wave and a second pulse wave.
In a preferred embodiment, the time interval between the last first pulse wave of the plurality of first pulse waves and the adjacent first second pulse wave is greater than or equal to the first preset period.
As a preferred embodiment, the waveform periods of the first pulse wave and the second pulse wave are the same.
Specifically, processing is performed on the data signal at ASIDE, taking rising edge transmission as an example, generating a first pulse wave at the rising edge of the data signal, continuing to transmit the first pulse wave every first preset period T1, until a second pulse wave is transmitted every second preset period T2 before the data signal is converted from the rising edge to the falling edge (i.e., the second preset period T2 before the falling edge), then continuing to transmit the second pulse wave every second preset period T2, continuing to transmit the first pulse wave at the next rising edge of the data signal in the above manner, and realizing edge encoding of the data signal in this manner, see fig. 7a, in which data_aside is the data signal to be transmitted, and clk_ ASIDE is the clock signal output at ASIDE.
Further, the first pulse wave and the second pulse wave have the same waveform amplitude and pulse width, and the difference is only that the repetition period (i.e. the time interval) of the transmitted pulses is different, and the first pulse wave and the second pulse wave may take the form of rising edges, falling edges, square waves, and the like, which contain clock information.
As a preferred embodiment, as shown in fig. 6, in step S2, specifically, the method includes:
Step S21A, comparing the time interval between two adjacent pulse waves in the clock signal with a preset period threshold;
step S22A, decoding the first pulse wave received from the first time to the first decoded data when the time interval is less than or equal to the first preset period; and
Decoding the first and second pulse waves received from the first and second source into second decoded data when the time interval is greater than the first preset period and less than or equal to the second preset period;
in step S23A, a data signal is obtained according to the decoded data decoded by all adjacent two pulse waves in the clock signal.
Specifically, at the end BSIDE, the receiving end receives the same delayed signal, the DATA signal is obtained by judging the time, when the first pulse wave of the clock signal received at the end BSIDE, namely, the pulse wave moment, the DATA signal is changed from 0 to 1, if there is a pulse wave in the first preset period T1 at intervals, the DATA signal is continuously kept to 1 to 0 at the next pulse wave moment, if there is no pulse wave in the first preset period T1 at intervals, the DATA signal is continuously kept to 0 if there is a pulse wave in the second preset period T2 at intervals, if the interval time is changed to the first preset period T1, the DATA signal is changed from 0 to 1 from the first pulse wave in the first preset period T1 at intervals, decoding is performed in this way, and the final DATA signal is obtained, see fig. 7b, clk_bsbs25 is the clock signal received at the end BSIDE, and data_ BSIDE is the DATA signal obtained by decoding.
By adopting the scheme, as the transmission paths corresponding to the rising edge and the falling edge of the data signal to be transmitted are the same pulse signal (both are the rising edge or the falling edge), path delays are counteracted, and the pulse width distortion PWD= |Tr1-Tr2|=0, so that the recovered data has no pulse width distortion, and the pulse width distortion caused by the mismatch of the rising edge and the falling edge transmission path delays of the transmission data is avoided.
In a preferred embodiment, in step S2, further includes:
when the time interval between the two pulse waves is larger than a third preset period, setting the decoded data as default decoded data, wherein the default decoded data is identical to the second decoded data.
As a preferred embodiment, the third preset period is greater than the second preset period;
The second preset period is greater than the first preset period.
Specifically, in order to solve the problem that the DATA is in error for a long time when an electromagnetic interference (EMI) occurs in an error pulse, the invention can also add an error correction circuit, when no pulse wave occurs in a third preset period T3 after the DATA signal is changed from 0 to 1, the DATA is set to a default value, that is, the DATA signal is changed from 1 to 0, see fig. 7c, clk_bside is a clock signal received at BSIDE terminal, and data_ BSIDE is a DATA signal obtained by decoding.
Embodiment two:
in another preferred embodiment of the present invention, as shown in fig. 9a, in step S1, the preset rule includes:
Transmitting pulse waves of a clock signal from the rising edge of the data signal, wherein the time interval between two adjacent pulse waves is a first preset period;
the pulse wave of the clock signal is stopped from being transmitted from the falling edge of the data signal.
As a preferred embodiment, a time interval between last two pulse waves of the plurality of pulse waves is less than or equal to the first preset period.
Specifically, processing is performed on the data signal at ASIDE, taking rising edge transmission as an example, a pulse wave is generated at the rising edge of the data signal, the pulse wave is continuously transmitted every first preset period T1, until the time interval between the last two pulse waves before the data signal is converted from the rising edge to the falling edge may be smaller than the first preset period, the pulse wave is not transmitted at the beginning (i.e. at the low level) of the falling edge of the data signal, and edge coding of the data signal is implemented in this way, see fig. 9a, data_aside is the data signal to be transmitted, and clk_ ASIDE is the output clock signal.
Further, the pulse wave may take the form of a rising edge, a falling edge, a square wave, etc. containing clock information.
As a preferred embodiment, as shown in fig. 8, in step S2, specifically, the method includes:
step S21B, judging whether the clock signal has pulse waves in a second preset period:
if so, decoding the second preset period from the interval after receiving the pulse wave into first decoded data;
If the first decoded data does not exist, decoding the second preset period of the interval after the last pulse in the plurality of pulse waves with the time interval being the first preset period into the second decoded data;
Step S22B, obtaining a data signal according to the decoded data decoded in all second preset periods in the second clock signal.
Specifically, decoding is performed at the end BSIDE, the receiving end receives the same delayed signal, the DATA signal is obtained by judging the time, when the first pulse wave of the clock signal received at the end BSIDE, namely the first pulse wave time +t2 (namely the second preset period T2 is delayed again), the DATA signal is changed from 0 to 1, if the pulse wave with the interval of the first preset period T1 exists, the DATA signal is kept to be 1, if the pulse wave with the interval of the first preset period T1 does not exist, the second preset period T2 is delayed after the last pulse wave, the DATA signal is changed from 1 to 0 until the time +t2 of the next pulse wave is received, the DATA signal is changed from 0 to 1 again, decoding is performed in this way, and the final DATA signal is obtained, see fig. 9b, clk_bside is the clock signal received at the end BSIDE, and data_ BSIDE is the DATA signal obtained by decoding.
By adopting the scheme, as the transmission paths corresponding to the rising edge and the falling edge of the data signal to be transmitted are the same pulse signal (both are rising edges or falling edges)) + delay the second preset period T2, the path delays are counteracted, and the pulse width distortion PWD= |Tr1+T2-Tr2-T2|=0, so that the recovered data has no pulse width distortion, and the pulse width distortion caused by the mismatch of the rising edge and the falling edge transmission path delays of the transmitted data is avoided.
In a preferred embodiment, in step S2, further includes:
when the time interval between the two pulse waves is larger than a third preset period, setting the decoded data as default decoded data, wherein the default decoded data is identical to the second decoded data.
As a preferred embodiment, the third preset period is greater than the second preset period;
The second preset period is greater than the first preset period.
Specifically, in order to solve the problem that the DATA is in error for a long time when the electromagnetic interference generates an error pulse, the invention can also add an error correction circuit, when the pulse wave does not generate in the third preset period T3 after the DATA signal is changed from 0 to 1, the DATA is set as a default value, namely, the DATA signal is changed from 1 to 0, see fig. 9c, clk_bside is a clock signal received by BSIDE terminal, and data_ BSIDE is a DATA signal obtained by decoding.
The invention has the beneficial effects that: the invention eliminates the improvement scheme of the prior art on the basis of data transmission, only one transmission path is needed, the transmission path transmits clock signals instead of data signals, clock pulses are transmitted according to the rising edge and/or the falling edge of the data signals, the data signals are decoded at the receiving end according to the pulse interval of the received clock signals, and the delay of the transmission path is fixed by adopting the same-edge transmission method, so that the delay is counteracted, and the phenomenon of pulse width distortion is avoided.
The foregoing is merely illustrative of the preferred embodiments of the present invention and is not intended to limit the embodiments and scope of the present invention, and it should be appreciated by those skilled in the art that equivalent substitutions and obvious variations may be made using the description and illustrations of the present invention, and are intended to be included in the scope of the present invention.

Claims (8)

1. A delay cancellation method of transmission data, comprising:
Step S1, outputting a clock signal according to a preset rule according to the rising edge and/or the falling edge of a data signal to be transmitted, wherein the clock signal comprises a plurality of pulse waves;
step S2, decoding is carried out according to the interval between pulse waves of the clock signal so as to obtain the data signal to be transmitted according to the clock signal;
in the step S1, the preset rule includes:
transmitting first pulse waves of the clock signal from the rising edge of the data signal, wherein the time interval between two adjacent first pulse waves is a first preset period;
Transmitting second pulse waves of the clock signal from the falling edge of the data signal, wherein the time interval between two adjacent second pulse waves is a second preset period;
The pulse wave of the clock signal includes the first pulse wave and the second pulse wave;
In the step S2, the method includes:
step S21A, comparing the time interval between two adjacent pulse waves in the clock signal with a preset period threshold;
Step S22A, decoding the first pulse wave received from the first time interval to first decoded data when the time interval is smaller than or equal to the first preset period; and
Decoding the first pulse wave received from the first pulse wave into second decoded data when the time interval is larger than the first preset period and smaller than or equal to the second preset period;
step S23A, obtaining the data signal according to the decoded data decoded by all adjacent two pulse waves in the clock signal.
2. The delay canceling method of claim 1 wherein a time interval between a last one of said first pulse waves and an adjacent first one of said second pulse waves having a time interval of a first predetermined period is greater than or equal to said first predetermined period.
3. The delay cancellation method of transmission data according to claim 1, wherein in the step S2, further comprising:
and when the time interval between the two pulse waves is larger than a third preset period, setting the decoded data as default decoded data, wherein the default decoded data is identical to the second decoded data.
4. A method of delay cancellation of transmitted data according to claim 3, wherein the third predetermined period is greater than the second predetermined period;
the second preset period is greater than the first preset period.
5. A delay cancellation method of transmission data, comprising:
Step S1, outputting a clock signal according to a preset rule according to the rising edge and/or the falling edge of a data signal to be transmitted, wherein the clock signal comprises a plurality of pulse waves;
step S2, decoding is carried out according to the interval between pulse waves of the clock signal so as to obtain the data signal to be transmitted according to the clock signal;
in the step S1, the preset rule includes:
Transmitting pulse waves of the clock signal from the rising edge of the data signal, wherein the time interval between two adjacent pulse waves is a first preset period;
Stopping transmitting a pulse wave of the clock signal from a falling edge of the data signal;
In the step S2, the method specifically includes:
step S21B, determining whether the clock signal has a pulse wave in a second preset period:
If so, decoding the interval second preset period after the pulse wave is received into first decoded data;
If not, decoding an interval second preset period after the last pulse in a plurality of pulse waves with the time interval being the first preset period into second decoded data;
step S22B, obtaining the data signal according to the decoded data decoded in all the second preset periods in the second clock signal.
6. The delay canceling method of claim 5 wherein a time interval between last two of said plurality of pulse waves is less than or equal to said first predetermined period.
7. The delay cancellation method of transmission data according to claim 5, wherein in step S2, further comprising:
and when the time interval between the two pulse waves is larger than a third preset period, setting the decoded data as default decoded data, wherein the default decoded data is identical to the second decoded data.
8. The delay cancellation method of claim 7, wherein the third predetermined period is greater than the second predetermined period;
the second preset period is greater than the first preset period.
CN202111146452.7A 2021-09-28 2021-09-28 Delay counteracting method for transmission data Active CN114090482B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111146452.7A CN114090482B (en) 2021-09-28 2021-09-28 Delay counteracting method for transmission data

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111146452.7A CN114090482B (en) 2021-09-28 2021-09-28 Delay counteracting method for transmission data

Publications (2)

Publication Number Publication Date
CN114090482A CN114090482A (en) 2022-02-25
CN114090482B true CN114090482B (en) 2024-06-07

Family

ID=80296306

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111146452.7A Active CN114090482B (en) 2021-09-28 2021-09-28 Delay counteracting method for transmission data

Country Status (1)

Country Link
CN (1) CN114090482B (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE804062A (en) * 1972-09-07 1973-12-17 Ibm PULSE RATE MODULATED DATA DECODING PROCESS AND CIRCUIT
CN103679077A (en) * 2012-09-18 2014-03-26 北京中电华大电子设计有限责任公司 Decoding circuit of pulse interval encoding
CN110417440A (en) * 2013-09-04 2019-11-05 联发科技(新加坡)私人有限公司 Envelope extraction device, signal decoding apparatus and short distance non-contact communication device and correlation technique

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE804062A (en) * 1972-09-07 1973-12-17 Ibm PULSE RATE MODULATED DATA DECODING PROCESS AND CIRCUIT
CN103679077A (en) * 2012-09-18 2014-03-26 北京中电华大电子设计有限责任公司 Decoding circuit of pulse interval encoding
CN110417440A (en) * 2013-09-04 2019-11-05 联发科技(新加坡)私人有限公司 Envelope extraction device, signal decoding apparatus and short distance non-contact communication device and correlation technique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Power Control and Adaptive Digital Pulse Interval Modulation for Free Space Optical Links;Mohammad Taghi Dabiri;《IEEE》;20161215;184-187 *
S 模式应答机 DPSK 信号解调处理方法分析;王华军;《电子技术与软件工程》;20201015;77-79 *

Also Published As

Publication number Publication date
CN114090482A (en) 2022-02-25

Similar Documents

Publication Publication Date Title
US5412697A (en) Delay line separator for data bus
US9479363B2 (en) Partial response receiver and related method
US7920601B2 (en) Vehicular communications system having improved serial communication
JPS61112449A (en) Data transmission system
US7405650B2 (en) Device with improved serial communication
CN108063661A (en) Sample circuit and receiving circuit based on Manchester's code
JP2017028489A (en) Skew correction circuit, electronic device and skew correction method
CN114090482B (en) Delay counteracting method for transmission data
US20060093029A1 (en) Apparatus and method for grey encoding modulated data
US7106753B2 (en) Interpolated timing recovery system for communication transceivers
CN110995249B (en) Clock jitter generating device
US7092439B2 (en) Means and method of data encoding and communication at rates above the channel bandwidth
KR101023640B1 (en) Oversampling technique to reduce jitter
JP2005020308A (en) Serial communication method and equipment
RU172181U1 (en) DEVICE FOR JOINT TRANSMISSION OF INFORMATION AND TEST SIGNALS WITH FREQUENCY SHIFT IN CHANNELS WITH INTER-CHARACTER INTERFERENCE
RU2549360C1 (en) Signal demodulator with relative phase modulation
Oletu et al. The smearing filter design techniques for data transmission
CN118054796A (en) Receiving and decoding circuit based on symmetrical differential non-return-to-zero coding and two-bus communication method
JP4207809B2 (en) Encoding circuit and transmission system
CN115580307A (en) Manchester decoding method and device and battery management system applying manchester decoding method and device
US20030210748A1 (en) Digital signal modulation and demodulation method
JPS60245332A (en) Synchronizing data transmission equipment
JPH04332219A (en) Manchester code generating circuit
JPS61182343A (en) Timing transmission system
JPS61194941A (en) Timing extracting circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant