CN114088224B - Calculating plate chip temperature monitoring system - Google Patents
Calculating plate chip temperature monitoring system Download PDFInfo
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- CN114088224B CN114088224B CN202111385792.5A CN202111385792A CN114088224B CN 114088224 B CN114088224 B CN 114088224B CN 202111385792 A CN202111385792 A CN 202111385792A CN 114088224 B CN114088224 B CN 114088224B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K3/00—Thermometers giving results other than momentary value of temperature
- G01K3/02—Thermometers giving results other than momentary value of temperature giving means values; giving integrated values
- G01K3/06—Thermometers giving results other than momentary value of temperature giving means values; giving integrated values in respect of space
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01K—MEASURING TEMPERATURE; MEASURING QUANTITY OF HEAT; THERMALLY-SENSITIVE ELEMENTS NOT OTHERWISE PROVIDED FOR
- G01K13/00—Thermometers specially adapted for specific purposes
Abstract
The invention provides a chip temperature monitoring system of a computing board, which comprises a main controller and a plurality of chips arranged on the same computing board, wherein a temperature sensor is integrated in each chip. Compared with the prior art that temperature monitoring is carried out by means of an external small amount of temperature sensors, the temperature monitoring method is more accurate, and when the temperature is monitored, the temperature of each chip is calibrated, so that deviation caused by differences of different temperature sensors is made up, monitoring precision is further improved, and in addition, cost is saved.
Description
Technical Field
The invention relates to the technical field of chips, in particular to a computing plate chip temperature monitoring system.
Background
The computing board generally comprises tens of computing chips with the same specification, and the temperature of each chip on the computing board needs to be monitored during normal operation so as to ensure that the computing board works within a reasonable temperature range and avoid the chip damage caused by overhigh temperature or abnormal operation caused by overlow temperature.
The existing temperature monitoring mode of the computing board chip is that a small number of external temperature sensors are welded in different areas of the computing board, a main controller polls all the temperature sensors in sequence to obtain the approximate temperatures of the chips in different areas on the computing board, and the temperature sensors cannot be too many due to the limitation of cost, PCB layout space and the like, so that the temperature monitoring precision is insufficient, and the cost of the external temperature sensors is higher.
Disclosure of Invention
Based on the above, an accurate and low-cost computing board chip temperature monitoring system is provided for the technical problems.
In order to solve the technical problems, the invention adopts the following technical scheme:
the system is characterized by comprising a main controller and a plurality of chips arranged on the same computing board, wherein a temperature sensor is integrated in the chips;
the master controller is configured to:
average temperature determination: after the computing board is electrified, sending a temperature inquiry command to the chip; receiving a temperature accumulated value sent by a chip, determining an average temperature in an initial power-on state according to the temperature accumulated value and the number of the chips, and sending the average temperature to each chip;
upper limit temperature monitoring: sending an upper limit temperature monitoring command to the chip, and receiving a judging result sent by the chip;
lower limit temperature monitoring: sending a lower limit temperature monitoring command to the chip, and receiving a judging result sent by the chip;
the plurality of chips are configured to:
temperature compensation value determination: after the computing board is electrified, responding to a temperature inquiry command sent by the main controller, determining the respective initial chip temperature through the respective temperature sensor, accumulating, and sending a temperature accumulated value to the main controller; receiving the average temperature sent by the main controller, calculating the deviation between the respective initial chip temperature and the average temperature, and determining respective temperature compensation values according to the deviation;
and (5) upper limit exceeding judgment: determining respective current chip temperatures through respective temperature sensors in response to an upper limit temperature monitoring command sent by the main controller, and calibrating the respective current chip temperatures according to the respective temperature compensation values; judging whether the respective calibrated temperatures exceed an upper limit temperature threshold value, and sending respective judgment results to the main controller;
and (5) exceeding a lower limit judgment: determining respective current chip temperatures through respective temperature sensors in response to a lower limit temperature monitoring command sent by the main controller, and calibrating the respective current chip temperatures according to the respective temperature compensation values; and judging whether the respective calibrated temperature is lower than a lower limit temperature threshold value, and sending respective judgment results to the main controller.
Compared with the prior art that temperature monitoring is carried out by means of an external small number of temperature sensor chips, the temperature monitoring method is more accurate, and when the temperature is monitored, the temperature of each chip is calibrated, so that deviation caused by differences of different temperature sensors is made up, monitoring precision is further improved, and in addition, cost is saved.
Drawings
The invention is described in detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is an internal schematic diagram of a chip of the present invention;
FIG. 3 is a flowchart illustrating steps performed by the master controller of the present invention;
FIG. 4 is a flowchart of steps performed by a plurality of chips of the present invention.
Detailed Description
As shown in fig. 1, the embodiment of the present disclosure provides a chip temperature monitoring system of a computing board, which includes a main controller 110 and a plurality of chips 120 disposed on the same computing board, wherein a temperature sensor is integrated in the chips 120.
The main controller 110 may be located on a computing board or on a separate control sub-board.
The temperature sensor is arranged in each chip, only one-time investment is needed, and the temperature sensor has the advantage of high cost when the mass production quantity is relatively large. For example, various chips (south bridge chip, north bridge chip, etc.) on the computer motherboard are numerous, and most of the peripheral chips are integrated into one chip of the CPU until the last time, thereby greatly reducing the cost.
Wherein, as shown in fig. 3, the main controller 110 is configured to perform the steps of:
s101, determining an average temperature: after the computing pad is powered on, the main controller 110 sends a temperature query command to the chip 120; the temperature accumulated value transmitted from the chip 120 is received, an average temperature in the initial state of power-up is determined according to the temperature accumulated value and the number of chips, and the average temperature is transmitted to each chip.
S102, monitoring upper limit temperature: the main controller 110 sends an upper limit temperature monitoring command to the chip 120, and receives the judgment result sent by the chip 120.
S103, monitoring the lower limit temperature: the main controller 110 sends a lower limit temperature monitoring command to the chip 120, and receives the judgment result sent by the chip 120.
Of course, steps S102 and S103 are not sequential.
Accordingly, as shown in fig. 4, the plurality of chips 120 are configured to:
s201, determining a temperature compensation value: after the computing board is powered on, each chip 120 determines a respective initial chip temperature through a respective temperature sensor 123 in response to a temperature query command sent by the main controller 110, and accumulates the initial chip temperatures to send a temperature accumulated value to the main controller 110; each chip 120 receives the average temperature sent by the main controller 110, calculates the deviation between the respective initial chip temperature and the average temperature, and determines the respective temperature compensation value according to the deviation.
The temperature compensation value is used for calibrating the temperature of the chip when the upper limit judgment and the lower limit judgment are exceeded, and the temperature value read by each chip possibly has deviation due to the fact that the sensors inside the chip are different, so that the temperature of all the chips needs to be calibrated first.
If the average temperature is 23 DEG, the initial temperature of the chip a is 25 DEG, the temperature compensation value of the chip a is-2 DEG, the initial temperature of the chip b is 22 DEG, and the temperature compensation value of the chip b is 1 deg.
S202, judging whether the upper limit is exceeded: in response to the upper limit temperature monitoring command sent by the main controller 110, each chip 120 determines a respective current chip temperature through a respective temperature sensor 123, and calibrates the respective current chip temperature according to the respective temperature compensation value, taking the chip a as an example, when the current chip temperature is 30 °, the calibrated temperature is 30-2=28°; each chip 120 determines whether the respective calibrated temperatures exceed the upper temperature threshold, and transmits the respective determination results to the main controller 110.
S203, judging whether the lower limit is exceeded: in response to the lower limit temperature monitoring command sent by the main controller 110, each chip 120 determines a respective current chip temperature through a respective temperature sensor 123, and calibrates the respective current chip temperature according to the respective temperature compensation value; each chip 120 determines whether the respective calibrated temperature is lower than the lower temperature threshold, and transmits the respective determination result to the main controller 110.
In this embodiment, the main controller 110 and the plurality of chips 120 are sequentially connected with the main controller 110 as a first example, so as to form a daisy chain ring topology.
As shown in fig. 2, the chip 120 includes a main controller 121, a plurality of computing cores 122, a phase-locked loop unit 123, a temperature sensor 124, a first interface 125 and a second interface 126, the phase-locked loop unit 123 is connected with the main controller 121, the plurality of computing cores 122 and the temperature sensor 124, and provides clock signals, and the main controller 121 is connected with the plurality of computing cores 122, the temperature sensor 124 and the first interface 125 and the second interface 126, and performs internal data interaction, external data communication and task processing.
The first interface 125 is used for connecting with an upper level, the second interface 126 is used for connecting with a lower level, and the chip 120 logically has a downstream data path and an upstream data path, so that bidirectional communication access between the main controller 110 and all the chips 120 on the computing board can be realized.
When the data is down, the first interface 125 is in the receiving mode, the second interface 126 is in the transmitting mode, and the down data path receives the data from the upper stage from the first interface 125 and transmits the data to the lower stage through the second interface 126.
When data is uplink, the first interface 125 is in a transmitting mode, the second interface 126 is in a receiving mode, and the uplink data path receives data from a lower level from the second interface 126 and transmits the data to an upper level through the first interface 125.
The first interface 125 and the second interface 126 are full duplex or half duplex interfaces, and the interface protocol adopts UART protocol, USB protocol or SPI protocol, although other protocols may be adopted.
The downstream data path and the upstream data path of the last chip form a loop through the second interface 126, so that the main controller 110 and the plurality of chips 120 form a daisy-chained topology.
In this embodiment, the specific procedure of step S101 is as follows:
1. after the computing pad is powered up, the main controller 110 sends a temperature inquiry command to the first chip, the temperature inquiry command having a temperature accumulation value with an initial value of 0.
2. The main controller 110 receives a temperature inquiry command from the first chip, determines an average temperature in the initial state of power-up according to the temperature accumulated value in the temperature inquiry command and the number of chips (the number of chips is known in advance to the main controller 110), and transmits the average temperature to the first chip.
Accordingly, in the present embodiment, the specific procedure of step S201 is as follows:
1. after the computing board is powered on, each chip 120 sequentially receives the temperature inquiry command issued by the upper stage, after each chip 120 receives the temperature inquiry command, the temperature sensor 123 determines the initial chip temperature of the chip, the initial chip temperature is accumulated into the temperature accumulation value of the temperature inquiry command, the temperature inquiry command is sent to the next chip 120, and after the last chip accumulates the initial chip temperature into the temperature accumulation value of the temperature inquiry command, each chip 120 sequentially sends the temperature inquiry command to the upper stage from the last chip.
2. Each chip 120 sequentially receives the average temperature issued by the upper stage, and after each chip 120 receives the average temperature, the deviation between the initial chip temperature and the average temperature of the chip is calculated, and the temperature compensation value of the chip is determined according to the deviation.
In this embodiment, the specific procedure of step S102 is as follows:
1. the main controller 110 sends an upper limit temperature monitoring command to the first chip, wherein the upper limit temperature monitoring command has a first overrun flag bit and a plurality of temperature maximum values, the number of bits of the first overrun flag bit is the same as that of the chips, initial values of all bits of the first overrun flag bit are 0, and initial values of the plurality of temperature maximum values are 0.
2. The main controller 110 receives the upper limit temperature monitoring command from the first chip, determines the chip with the temperature exceeding the upper limit according to the first exceeding zone bit in the upper limit temperature monitoring command, and determines the highest temperature of the computing board according to a plurality of maximum temperature values in the upper limit temperature monitoring command.
Accordingly, in the present embodiment, the specific procedure of step S202 is as follows:
1. each chip 120 sequentially receives the upper limit temperature monitoring command issued by the upper level, and after each chip receives the upper limit temperature monitoring command, the current chip temperature of the chip is determined through the temperature sensor 123 and calibrated according to the temperature compensation value of the chip.
2. After the current chip temperature calibration of each chip 120 is completed:
on the one hand, whether the current chip temperature after the chip calibration exceeds the upper limit temperature threshold value is judged, if so, the corresponding bit of the first overrun flag bit in the upper limit temperature monitoring command is set to be 1, otherwise, 0 is kept.
If there are 8 chips in total, and the 2 nd and 7 th chips exceed the upper limit temperature threshold, the first over-limit flag bit in the upper limit temperature monitoring command finally sent to the main controller 110 is: 01000010, the main controller 110 can determine that the chips whose temperatures exceed the upper limit are the 2 nd and 7 th chips.
And on the other hand, comparing and judging the current chip temperature after the chip calibration with a plurality of maximum temperature values in sequence, if the current chip temperature after the chip calibration exceeds the current maximum temperature value, updating the current maximum temperature value by using the current chip temperature, otherwise, keeping the current maximum temperature value unchanged, and comparing and judging the current chip temperature after the chip calibration with the next maximum temperature value until the comparison and judgment are completed with all the maximum temperature values.
Taking three temperature maximum values as an example, if the temperature value after the current chip calibration exceeds the first temperature maximum value, the first temperature maximum value is updated by the temperature value after the current chip calibration, otherwise, if the temperature value after the current chip calibration exceeds the second temperature maximum value, the second temperature maximum value is updated by the temperature value after the current chip calibration, otherwise, if the temperature value after the current chip calibration exceeds the third temperature maximum value, the temperature value after the current chip calibration is replaced by the third temperature maximum value.
If the main controller 110 determines that the maximum values of the three temperatures are 98 °, 97 °, 95 ° from the upper limit temperature monitoring command, which represents that the three maximum temperatures of the current computing board are 98 °, 97 °, 95 °, the three maximum temperature values can be further intuitively displayed to the user, so that the user can intuitively know that none of the three maximum temperatures on the current computing board exceeds the upper limit temperature threshold value of 100 °, which represents that the operation is normal.
The number of the temperature maximum values is preferably three, so that the scientificity of probability statistics is considered, the efficiency problem is considered, if the number of the temperature maximum values is set too much, the efficiency is reduced, and if the number of the temperature maximum values is too small, misjudgment is caused by the possibility that individual deviation abnormality exists.
On the contrary, if the maximum values of the three temperatures are 102 °, 101 °, 98 °, respectively, which represents that at least two chips on the computing board exceed 100 °, the main controller 110 is required to perform cooling treatment to avoid the temperature of the computing board from being too high, and the frequency is usually reduced or the voltage is reduced, so that heat dissipation is reduced to reduce the temperature.
Therefore, the purpose of setting a plurality of maximum temperature values in the upper limit temperature monitoring command and comparing and judging the chip temperature with the maximum temperature value is to intuitively reflect the temperature condition on the computing board to the user, and is not necessary.
3. After each chip 120 completes the above judgment, the upper limit temperature monitoring command is sent to the next chip, and after the last chip completes the judgment, each chip 120 sequentially sends the upper limit temperature monitoring command to the upper level from the last chip.
In this embodiment, the specific procedure of step S103 is as follows:
1. the main controller 110 sends a lower limit temperature monitoring command to the first chip, wherein the lower limit temperature monitoring command has a second overrun flag bit and a plurality of temperature minimum values, the number of bits of the second overrun flag bit is the same as that of the chips, the initial values of all bits of the second overrun flag bit are 0, and the initial values of the plurality of temperature minimum values are 0.
2. The main controller 110 receives the lower limit temperature monitoring command from the first chip, determines a chip whose temperature exceeds the lower limit according to the second overrun flag bit in the lower limit temperature monitoring command, and determines the lowest temperature of the computing board according to a plurality of temperature minimums in the lower limit temperature monitoring command.
Accordingly, in the present embodiment, the specific procedure of step S203 is as follows:
1. each chip 120 sequentially receives the lower limit temperature monitoring command issued by the upper stage, and after each chip 120 receives the lower limit temperature monitoring command, the current chip temperature of the chip is determined through the temperature sensor 123 and calibrated according to the temperature compensation value of the chip.
2. After the current chip temperature calibration of each chip to the chip is finished:
on the one hand, whether the current chip temperature after the chip calibration is lower than the lower limit temperature threshold value is judged, if yes, the corresponding bit of the second overrun flag bit in the lower limit temperature monitoring command is set to be 1, otherwise, 0 is kept.
And on the other hand, comparing and judging the current chip temperature after the chip calibration with a plurality of temperature minimums in turn, if the current chip temperature after the chip calibration is lower than the current temperature minimums, updating the current temperature minimums with the current chip temperature, otherwise, keeping the current temperature minimums unchanged, and comparing and judging the current chip temperature after the chip calibration with the next temperature minimums until the comparison and judgment are completed with all the temperature minimums.
The purpose here is also to intuitively reflect the temperature condition on the computing board to the user, and reference is made to the example and description in step S202, which will not be repeated here.
3. After each chip 120 completes the above judgment, the lower limit temperature monitoring command is sent to the next chip, and after the last chip completes the judgment, each chip 120 sequentially sends the lower limit temperature monitoring command to the upper level from the last chip.
It should be noted that the upper temperature threshold and the lower temperature threshold are respectively sent to each chip 120 by the main controller 110 before the upper temperature monitoring and before the lower temperature monitoring, or are preset in each chip.
Preferably, the plurality of chips 120 are uniformly distributed on the computing pad, so that it is possible to further precisely monitor whether the temperature within each small area on the computing pad is abnormal.
However, it will be appreciated by persons skilled in the art that the above embodiments are provided for illustration of the invention and not for limitation thereof, and that changes and modifications to the above described embodiments are intended to fall within the scope of the appended claims as long as they fall within the true spirit of the invention.
Claims (8)
1. The chip temperature monitoring system of the computing board is characterized by comprising a main controller and a plurality of chips arranged on the same computing board, wherein the main controller and the chips are sequentially connected by taking the main controller as a head to form a daisy chain ring topology structure, and a temperature sensor is integrated in the chips;
the master controller is configured to:
average temperature determination: after the computing board is electrified, sending a temperature inquiry command to the chip; receiving a temperature accumulated value sent by a chip, determining an average temperature in an initial power-on state according to the temperature accumulated value and the number of the chips, and sending the average temperature to each chip;
upper limit temperature monitoring: sending an upper limit temperature monitoring command to the chip, and receiving a judging result sent by the chip;
lower limit temperature monitoring: sending a lower limit temperature monitoring command to the chip, and receiving a judging result sent by the chip;
the plurality of chips are configured to:
temperature compensation value determination: after the computing board is electrified, responding to a temperature inquiry command sent by the main controller, determining the respective initial chip temperature through the respective temperature sensor, accumulating, and sending a temperature accumulated value to the main controller; receiving the average temperature sent by the main controller, calculating the deviation between the respective initial chip temperature and the average temperature, and determining respective temperature compensation values according to the deviation;
and (5) upper limit exceeding judgment: determining respective current chip temperatures through respective temperature sensors in response to an upper limit temperature monitoring command sent by the main controller, and calibrating the respective current chip temperatures according to the respective temperature compensation values; judging whether the respective calibrated temperatures exceed an upper limit temperature threshold value, and sending respective judgment results to the main controller;
and (5) exceeding a lower limit judgment: determining respective current chip temperatures through respective temperature sensors in response to a lower limit temperature monitoring command sent by the main controller, and calibrating the respective current chip temperatures according to the respective temperature compensation values; judging whether the respective calibrated temperature is lower than a lower limit temperature threshold value, and sending respective judgment results to the main controller;
the average temperature determination further comprises:
after the computing board is electrified, the main controller sends a temperature inquiry command to a first chip, wherein the temperature inquiry command has a temperature accumulated value, and the initial value is 0;
the main controller receives a temperature inquiry command from the first chip, determines the average temperature in the initial power-on state according to the temperature accumulated value in the temperature inquiry command and the number of chips, and sends the average temperature to the first chip;
the temperature compensation value determination further includes:
after the computing board is electrified, each chip sequentially receives a temperature inquiry command issued by an upper stage, after each chip receives the temperature inquiry command, the temperature sensor is used for determining the initial chip temperature of the chip, the initial chip temperature is added into a temperature accumulation value of the temperature inquiry command, the temperature inquiry command is sent to the next chip, and after the last chip is added into the temperature accumulation value of the temperature inquiry command, each chip sequentially sends the temperature inquiry command to the upper stage from the last chip;
each chip sequentially receives the average temperature issued by the upper stage, and after each chip receives the average temperature, the deviation between the initial chip temperature of the chip and the average temperature is calculated, and the temperature compensation value of the chip is determined according to the deviation.
2. The computing pad chip temperature monitoring system of claim 1, wherein the chip comprises a plurality of computing cores and a phase-locked loop unit, the phase-locked loop unit being coupled to the plurality of computing cores and the temperature sensor.
3. The computing plate chip temperature monitoring system of claim 2, wherein the upper limit temperature monitor further comprises:
the main controller sends an upper limit temperature monitoring command to the first chip, wherein the upper limit temperature monitoring command is provided with a first overrun zone bit, the number of bits of the first overrun zone bit is the same as the number of the chips, and the initial value of each bit of the first overrun zone bit is 0;
the main controller receives an upper limit temperature monitoring command from the first chip and determines a chip with temperature exceeding the upper limit according to a first overrun flag bit in the upper limit temperature monitoring command;
the above upper limit judgment further includes:
each chip sequentially receives an upper limit temperature monitoring command issued by an upper level, after each chip receives the upper limit temperature monitoring command, the current chip temperature of the chip is determined through a temperature sensor, and the current chip temperature of the chip is calibrated according to the temperature compensation value of the chip;
after the current chip temperature calibration of each chip is finished, judging whether the current chip temperature after the chip calibration exceeds an upper limit temperature threshold value, if so, setting the corresponding bit of a first overrun flag bit in the upper limit temperature monitoring command to be 1, otherwise, keeping 0;
after the judgment of each chip is finished, the upper limit temperature monitoring command is sent to the next chip, and after the judgment of the last chip is finished, each chip sequentially sends the upper limit temperature monitoring command to the upper level from the last chip.
4. A computing plate chip temperature monitoring system according to claim 3, wherein the upper limit temperature monitoring command further has a plurality of temperature maxima, each having an initial value of 0;
in the upper limit temperature monitoring process, after receiving an upper limit temperature monitoring command from the first chip, the main controller also determines the highest temperature of the computing board according to a plurality of maximum temperature values in the upper limit temperature monitoring command;
and in the process of the upper limit judgment, after the current chip temperature of the chip is calibrated, each chip sequentially compares and judges the current chip temperature calibrated by the chip with the plurality of temperature maximum values, if the current chip temperature calibrated by the chip exceeds the current temperature maximum value, the current temperature maximum value is updated by the current chip temperature, otherwise, the current temperature maximum value is kept unchanged and is compared and judged with the next temperature maximum value until the comparison and judgment are completed with all the temperature maximum values.
5. The computing plate chip temperature monitoring system of claim 4, wherein the lower limit temperature monitor further comprises:
the main controller sends a lower limit temperature monitoring command to the first chip, wherein the lower limit temperature monitoring command is provided with second overrun zone bits, the number of the second overrun zone bits is the same as that of the chips, and the initial values of all the bits of the second overrun zone bits are 0;
the main controller receives a lower limit temperature monitoring command from the first chip and determines a chip with temperature exceeding the lower limit according to a second exceeding zone bit in the lower limit temperature monitoring command;
the lower limit exceeding judgment further includes:
each chip sequentially receives a lower limit temperature monitoring command issued by an upper stage, after each chip receives the lower limit temperature monitoring command, the current chip temperature of the chip is determined through a temperature sensor, and the current chip temperature of the chip is calibrated according to the temperature compensation value of the chip;
after the current chip temperature calibration of each chip is finished, judging whether the current chip temperature after the chip calibration is lower than a lower limit temperature threshold value, if so, setting the corresponding bit of a second overrun flag bit in the lower limit temperature monitoring command to be 1, otherwise, keeping 0, and after the judgment of each chip is finished, sending the lower limit temperature monitoring command to the next chip;
after the last chip is judged to be finished, each chip sequentially sends the lower limit temperature monitoring command to the upper level from the last chip.
6. The system of claim 5, wherein the lower temperature monitoring command further has a plurality of temperature minimums, each having an initial value of 0;
in the process of monitoring the lower limit temperature, after receiving a lower limit temperature monitoring command from the first chip, the main controller also determines the lowest temperature of the computing board according to a plurality of temperature minimum values in the lower limit temperature monitoring command;
and in the process of exceeding the lower limit, after the current chip temperature of the chip is calibrated, each chip sequentially compares and judges the current chip temperature calibrated by the chip with the plurality of temperature minimums, if the current chip temperature calibrated by the chip is lower than the current temperature minimums, the current temperature minimums are updated by the current chip temperature, otherwise, the current temperature minimums are kept unchanged and compared and judged with the next temperature minimums until the comparison and judgment are completed with all the temperature minimums.
7. The computing pad chip temperature monitoring system of claim 6, wherein the upper temperature threshold and the lower temperature threshold are sent to each chip by the master controller before upper temperature monitoring and before lower temperature monitoring, respectively, or are preset in each chip.
8. The computing plate chip temperature monitoring system of claim 7, wherein the plurality of chips are evenly distributed on the computing plate.
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| CN207456644U (en) * | 2017-11-13 | 2018-06-05 | 安徽蓝海之光科技有限公司 | A kind of mining temperature sensor |
| CN109947556A (en) * | 2017-12-21 | 2019-06-28 | 北京比特大陆科技有限公司 | Method for allocating tasks |
| CN108304341A (en) * | 2018-03-13 | 2018-07-20 | 算丰科技（北京）有限公司 | AI chip high speeds transmission architecture, AI operations board and server |
| CN111189561A (en) * | 2019-11-21 | 2020-05-22 | 上海申矽凌微电子科技有限公司 | Ultra-high temperature far-end temperature measurement calibration method, measurement calibration circuit and medium |
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