CN114080749A

CN114080749A - Device for DC voltage conversion and electronic equipment

Info

Publication number: CN114080749A
Application number: CN202080006186.5A
Authority: CN
Inventors: 胡章荣; 吴琨; 周卓敏; 产竹标; 衡草飞
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2020-06-20
Filing date: 2020-06-20
Publication date: 2022-02-22
Also published as: WO2021253457A1

Abstract

An apparatus and an electronic device for DC voltage conversion. The arrangement (210) for direct voltage conversion comprises: a frequency converter (310) configured to increase a frequency of the periodic signal from a first frequency to a second frequency based on a first selection signal; and a voltage regulator (350) coupled to the frequency converter (310) and configured to convert the first direct current voltage to a second direct current voltage based on a periodic signal of a second frequency in a pulse width modulation mode. The device and the electronic equipment can dynamically change the switching frequency in the pulse width modulation mode according to events, namely, the switchable switching frequency is realized. In this way, the performance of voltage conversion can be improved, and the reduction of the electric energy utilization efficiency caused by simply improving the switching frequency can be relieved.

Description

Device for DC voltage conversion and electronic equipment

Technical Field

The embodiments of the present application relate generally to the field of circuit technology, and more particularly, to an apparatus and an electronic device for dc voltage conversion.

Background

With the development of electronic technology, the performance of electronic devices such as smart phones and tablet computers is increasing, and diversified functional applications can be provided for users. Accordingly, the operating speed of various components (e.g., processing units) within electronic devices is increasing. The increased operating speed of components such as processing units has led to increased power consumption in electronic devices. For this reason, in the power supply of such electronic devices, a Dynamic Voltage Scaling (DVS) technique is generally employed. For example, a Power Management Integrated Circuit (PMIC) dynamically adjusts an output voltage of the PMIC in real time according to a Power consumption condition of a load. Such a load may include components such as a processing unit.

In a typical power architecture based on DVS technology, a processor, such as on a System-on-a-chip (SOC), sends instructions to a PMIC based on the voltage required by the load. The PMIC adjusts an output voltage, which is provided to the load, such as the SOC or the processor, according to an instruction from the processor. When the output voltage is adjusted to the target value, the processor as the load starts to execute the corresponding service. In this architecture, the output voltage is optimized to the voltage required by the load. Subject to the speed of voltage regulation, it is difficult in practice for the output voltage to accurately track the voltage demanded by the load. This results in wasted energy efficiency.

The means for dc voltage conversion usually have at least a Pulse Width Modulation (PWM) mode. One development has been to use higher switching frequencies in the PWM mode in order to implement fast DVS techniques. That is, operating at a relatively high switching frequency at all times may provide several benefits in terms of performance of the voltage conversion, such as increased start-up speed of the device, increased voltage regulation speed, increased transient response performance of the device, and so forth. However, operating at a preset high switching frequency also reduces power utilization efficiency.

Disclosure of Invention

Embodiments of the present disclosure provide an apparatus for dc voltage conversion and an electronic device to improve voltage conversion performance and alleviate a decrease in electric energy utilization efficiency.

In a first aspect, embodiments of the present disclosure provide an apparatus for dc voltage conversion. The device includes: a frequency converter configured to increase a frequency of the periodic signal from a first frequency to a second frequency based on a first selection signal; and a voltage regulator coupled to the frequency converter and configured to convert the first direct current voltage to a second direct current voltage based on a periodic signal of a second frequency in a pulse width modulation mode. The first dc voltage is also called an input voltage, and the second dc voltage is also called an output voltage.

In the proposed device, the switching frequency in the pulse width modulation mode can be increased upon triggering of an event, i.e. the switching frequency is no longer fixed but rather is switchable. In this way, the performance of voltage conversion can be improved, for example, the speed of voltage conversion can be improved, the reduction of electric energy utilization efficiency caused by working at a preset high switching frequency can be relieved, and the system requirements can be better adapted. Accordingly, embodiments of the present disclosure may balance voltage conversion performance and power utilization efficiency.

In some embodiments, the frequency translator is further configured to: reducing the frequency of the periodic signal from the second frequency to the first frequency based on a second selection signal different from the first selection signal; and the voltage regulator is further configured to: in the pulse width modulation mode, the first direct current voltage is converted into a second direct current voltage based on a periodic signal of a first frequency. In this way, a return to a lower switching frequency is automatically made at the end of the event, enabling a dynamic shift of the switching frequency. This further contributes to the balance between the voltage conversion performance and the electric power utilization efficiency.

In some embodiments, the frequency translator is further configured to: reducing the frequency of the periodic signal from the second frequency to a third frequency different from the first frequency based on a second selection signal different from the first selection signal; and the voltage regulator is further configured to: in the pulse width modulation mode, the first direct current voltage is converted into a second direct current voltage based on a periodic signal of a third frequency. In this way, a return to a lower switching frequency is automatically made at the end of the event, enabling a dynamic shift of the switching frequency. This further contributes to the balance between the voltage conversion performance and the electric power utilization efficiency.

In some embodiments, the first selection signal and the second selection signal are different indication states of the same indication signal, the first selection signal being used to indicate occurrence of at least one event, the second selection signal being used to indicate end of the at least one event. In this way, the conversion of the periodic signal between high and low frequencies can be achieved with a simple circuit configuration.

In some embodiments, the apparatus further comprises: a selection signal determination circuit coupled to the frequency converter and configured to determine a first selection signal based on the at least one event signal. In this way, multiple event signals may be configured to account for switching frequency shifts under a variety of scenarios.

In some embodiments, the at least one event signal comprises at least one of: a first event signal indicating that the voltage regulator is enabled, a second event signal indicating that a target value of the second dc voltage is adjusted, or a third event signal indicating that an actual value of the second dc voltage is outside a predetermined range.

In some embodiments, the selection signal determination circuit comprises an or gate, an input of the or gate being the at least one event signal, and an output of the or gate being the first selection signal.

In some embodiments, the frequency converter comprises: a first multiplexer configured to select a second candidate periodic signal as a periodic signal from a first candidate periodic signal having a first frequency and a second candidate periodic signal having a second frequency based on a first selection signal. In some embodiments, the first candidate periodic signal and the second candidate periodic signal may be ramp signals. In some embodiments, the first candidate periodic signal and the second candidate periodic signal may be PWM signals.

In some embodiments, the frequency converter further comprises: a second multiplexer coupled to the first multiplexer and configured to select one candidate periodic signal from a third candidate periodic signal having a fourth frequency and a fourth candidate periodic signal having a fifth frequency as the first candidate periodic signal based on a third selection signal representing a specification constraint of the load. In this way, the switching frequency in the pulse width modulation mode can be configured according to the power supply requirements of the load (e.g., requirements on ripple voltage, requirements on transient response speed, etc.), thereby better adapting to system requirements. This further contributes to the balance between the voltage conversion performance and the electric power utilization efficiency.

In some embodiments, a voltage regulator includes: an error amplifier configured to generate an error signal based on a reference signal and a feedback signal indicative of the second direct current voltage; a comparator coupled to the error amplifier and the frequency converter and configured to generate a pulse width modulated signal based on the periodic signal and the error signal; a switch drive circuit coupled to the comparator and configured to generate a switch drive signal based on the pulse width modulation signal; and a switching circuit coupled to the switch drive circuit and configured to convert the first direct current voltage to a second direct current voltage based on the switch drive signal.

In some embodiments, the voltage regulator further comprises: a loop compensator coupled to the error amplifier and an output of the voltage regulator and configured to adjust a pole-zero configuration of a loop formed by the voltage regulator.

In some embodiments, the loop compensator comprises: a first loop compensation circuit configured to adjust a pole-zero configuration in response to a second select signal different from the first select signal; and a second loop compensation circuit configured to adjust the pole-zero configuration in response to a first select signal. In this way, accurate compensation can be made for pulse width modulation patterns of different frequencies. This helps the device to operate stably at different frequencies.

In a second aspect, embodiments of the present disclosure provide an electronic device. The electronic device includes: a processor configured to generate a first frequency translated signal in response to an occurrence of at least one event; and means for dc voltage conversion coupled to the processor and configured to: in response to receiving the first frequency converted signal, increasing the frequency of the periodic signal from a first frequency to a second frequency, and in a pulse width modulation mode, converting the first direct current voltage to a second direct current voltage based on the periodic signal of the second frequency. The first dc voltage is also called an input voltage, and the second dc voltage is also called an output voltage. Alternatively, the apparatus may enable a first selection signal based on a first frequency translation signal and increase the frequency of the periodic signal from a first frequency to a second frequency based on the first selection signal.

In the provided electronic device, the switching frequency in the pulse width modulation mode may be shifted according to the triggering of an event. In this way, the performance of voltage conversion can be improved, for example, the speed of voltage conversion can be improved, the reduction of the electric energy utilization efficiency caused by the operation at the preset high switching frequency can be relieved, and the power supply requirement of the electronic equipment can be better adapted. This contributes to the realization of an electronic device optimized in power supply energy efficiency.

In some embodiments, the at least one event comprises at least one of: the device is started or the target value of the second dc voltage is adjusted.

In some embodiments, the apparatus is further configured to: in response to determining the end of the at least one event, decreasing the frequency of the periodic signal from the second frequency to the first frequency; and converting the first direct current voltage into a second direct current voltage based on a periodic signal of a first frequency in a pulse width modulation mode. In particular, the apparatus enables a second selection signal for reducing the frequency of the periodic signal from the second frequency to the first frequency in response to determining the end of the at least one event.

In some embodiments, the processor is further configured to: determining specification constraint conditions of the load; and generating a second frequency converted signal based on the specification constraint. The apparatus is further configured to: in response to receiving the second frequency converted signal, the first frequency of the periodic signal is set to one of a plurality of preset frequencies. Alternatively, the apparatus may enable a third selection signal based on the second frequency conversion signal and set the first frequency of the periodic signal to one of a plurality of preset frequencies based on the third selection signal. For example, the apparatus may select a periodic signal from a plurality of candidate periodic signals based on a third selection signal. Each of the plurality of candidate periodic signals has a respective frequency of a plurality of preset frequencies. In this way, the switching frequency in the pulse width modulation mode can be configured according to the power supply requirements of the load, thereby better adapting the power supply requirements inside the electronic device. This further contributes to the balance between the voltage conversion performance and the electric power utilization efficiency.

Optionally, the apparatus for dc voltage conversion may further include: an enabling section that enables the first selection signal based on the first frequency conversion signal. Additionally, in some embodiments, the enabling component that enables the first selection signal may be further configured to: the first selection signal is enabled in response to the actual value of the second dc voltage exceeding a predetermined range. Alternatively or additionally, the apparatus for direct voltage conversion may further comprise: an enabling section that enables the third selection signal based on the second frequency conversion signal. The enable part enabling the first selection signal and the enable part enabling the third selection signal may be the same or different parts.

Optionally, the apparatus for dc voltage conversion may further include: a frequency translator coupled to the enable component that enables the first select signal and configured to increase a frequency of the periodic signal from a first frequency to a second frequency based on the first select signal; and a voltage regulator coupled to the frequency converter and configured to convert the first direct current voltage to a second direct current voltage based on a periodic signal of a second frequency in a pulse width modulation mode. Optionally, the apparatus for dc voltage conversion may further include: a detection component for determining an end of at least one event. Alternatively, the detection component may determine the end of at least one event by detecting an electrical parameter. Such electrical parameters may comprise the output voltage of the device for direct voltage conversion.

Optionally, the detection means may be coupled to an enable means for enabling the first selection signal. The detection part may transmit an event end signal to the enabling part enabling the first selection signal if it is determined that the at least one event is ended. The enable component that enables the first selection signal may enable a second selection signal different from the first selection signal and disable the first selection signal based on the event end signal.

Optionally, the frequency converter may be further configured to: reducing the frequency of the periodic signal from the second frequency to the first frequency based on a second selection signal; and the voltage regulator is further configured to: in the pulse width modulation mode, the first direct current voltage is converted into a second direct current voltage based on a periodic signal of a first frequency. In some embodiments, the frequency translator is further configured to: reducing the frequency of the periodic signal from the second frequency to a third frequency different from the first frequency based on a second selection signal; and the voltage regulator is further configured to: in the pulse width modulation mode, the first direct current voltage is converted into a second direct current voltage based on a periodic signal of a third frequency.

Optionally, the first selection signal and the second selection signal are different indication states of the same indication signal, wherein the first selection signal is used for indicating the occurrence of at least one event, and the second selection signal is used for indicating the end of the at least one event.

Alternatively, the frequency converter may include: a first multiplexer configured to select a second candidate periodic signal as a periodic signal from a first candidate periodic signal having a first frequency and a second candidate periodic signal having a second frequency based on a first selection signal. In some embodiments, the first candidate periodic signal and the second candidate periodic signal may be ramp signals. In some embodiments, the first candidate periodic signal and the second candidate periodic signal may be PWM signals.

Optionally, the frequency converter may further include: and a second multiplexer having a control terminal coupled to the enable unit enabling the third selection signal and an output terminal coupled to the first multiplexer and configured to select one of the third candidate periodic signal having the fourth frequency and the fourth candidate periodic signal having the fifth frequency as the first candidate periodic signal based on the third selection signal.

Optionally, the voltage regulator may include: an error amplifier configured to generate an error signal based on a reference signal and a feedback signal indicative of the second direct current voltage; a comparator coupled to the error amplifier and the frequency converter and configured to generate a pulse width modulated signal based on the periodic signal and the error signal; a switch drive circuit coupled to the comparator and configured to generate a switch drive signal based on the pulse width modulation signal; and a switching circuit coupled to the switch drive circuit and configured to convert the first direct current voltage to a second direct current voltage based on the switch drive signal.

Optionally, the voltage regulator may further include: a loop compensator coupled to the error amplifier and an output of the voltage regulator and configured to adjust a pole-zero configuration of a loop formed by the voltage regulator.

Optionally, the loop compensator may comprise: a first loop compensation circuit configured to adjust a pole-zero configuration in response to a second select signal; and a second loop compensation circuit configured to adjust the pole-zero configuration in response to a first select signal. In this way, accurate compensation can be made for pulse width modulation patterns of different frequencies. This helps the device to operate stably at different frequencies.

In a third aspect, embodiments of the present disclosure provide an apparatus for dc voltage conversion. The device includes: a frequency converter configured to convert a frequency of the periodic signal based on the selection signal; and a voltage regulator coupled to the frequency converter and configured to convert the first dc voltage to a second dc voltage based on the periodic signal in the pulse width modulation mode. The first dc voltage is also called an input voltage, and the second dc voltage is also called an output voltage.

In the proposed device, the switching frequency in the pulse width modulation mode can be changed, i.e. the switching frequency is no longer fixed but is changeable. In this way, system requirements can be better adapted.

In some embodiments, the frequency translator may be further configured to: the frequency of the periodic signal is increased from a first frequency to a second frequency based on a first selection signal.

In some embodiments, the frequency translator may be further configured to: the frequency of the periodic signal is reduced from the second frequency to the first frequency based on a second selection signal different from the first selection signal. In some embodiments, the frequency translator may be further configured to: the frequency of the periodic signal is reduced from the second frequency to a third frequency different from the first frequency based on a second selection signal different from the first selection signal.

Furthermore, the embodiments described herein with respect to the apparatus of the first aspect may be applied to the apparatus of the third aspect and have the same advantageous effects.

In a fourth aspect, embodiments of the present disclosure provide an electronic system comprising an electronic device according to the second aspect and a memory for storing computer program instructions for execution by a processor in the electronic device to generate the first frequency translated signal.

In a fifth aspect, embodiments of the present disclosure provide a chip system including a first chip and a second chip. The first chip comprises the processor in the electronic device according to the second aspect and the second chip comprises the means for dc voltage conversion in the electronic device according to the second aspect.

In a sixth aspect, an embodiment of the present disclosure provides a chip including the apparatus for dc voltage conversion of the first aspect, and an interface for receiving the first frequency-converted signal from a processor in the electronic device of the second aspect.

It should be understood that the statements herein reciting aspects are not intended to limit the critical or essential features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:

FIG. 1 shows a schematic block diagram of an electronic device to which embodiments of the present disclosure can be applied;

FIG. 2 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure;

FIG. 3 illustrates a schematic block diagram of an apparatus for DC voltage conversion in accordance with some embodiments of the present disclosure;

FIG. 4 illustrates a graph of switching frequency versus load current according to some embodiments of the present disclosure;

FIG. 5 shows a schematic block diagram of an apparatus for DC voltage conversion according to some embodiments of the present disclosure;

FIG. 6 illustrates a schematic structural diagram of an apparatus for DC voltage conversion according to some embodiments of the present disclosure;

FIG. 7 illustrates a schematic diagram of an apparatus for DC voltage conversion according to further embodiments of the present disclosure;

FIG. 8 illustrates a schematic structural diagram of an apparatus for DC voltage conversion in accordance with further embodiments of the present disclosure;

FIG. 9 shows a schematic diagram of a frequency converter according to some embodiments of the present disclosure;

FIG. 10 illustrates a graph of switching frequency versus load current according to some embodiments of the present disclosure;

FIG. 11 illustrates a schematic structural diagram of an apparatus for DC voltage conversion according to some embodiments of the present disclosure;

fig. 12 illustrates an example process of frequency translation according to some embodiments of the present disclosure; and

fig. 13 illustrates a schematic block diagram of an electronic device in accordance with some embodiments of the present disclosure.

Detailed Description

Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.

In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect, that are equivalent to a broad coupling or electrical communication.

As briefly described above, in order to implement the fast DVS technique, one solution is to set the switching frequency of a device for dc voltage conversion (hereinafter, may also be referred to as a conversion device) in the PWM mode to a high frequency. The peak-to-peak value of the current flowing through the same inductor is lower at high switching frequencies compared to low switching frequencies. In the case where the Current limiting Protection (OCP) configuration is the same in each cycle, the Current Iout flowing through the inductor increases. During soft start, voltage regulation, output voltage droop response, etc. of the conversion device, the output capacitance of the conversion device is essentially charged. This increases Iout, which shortens the time for soft start, voltage regulation, and output voltage droop response. On the other hand, a high switching frequency significantly reduces the loop hardware delay of the conversion means compared to a low switching frequency. When the load changes transiently, transient drop or transient overshoot of the output voltage can be reduced. The high switching frequency admittedly brings several benefits in terms of the performance of the voltage conversion, such as an increase in the starting speed of the conversion means, an increase in the voltage regulation speed, a reduction in the droop or overshoot amplitude of the output voltage, etc. However, using a fixed high switching frequency also reduces the power conversion efficiency. Therefore, it is difficult to achieve efficient power efficiency by only employing a fixed high switching frequency to achieve fast DVS.

To address, at least in part, the above problems, as well as other potential problems, embodiments of the present disclosure provide a scheme for dc voltage conversion. In general, according to various embodiments described herein, an apparatus for dc voltage conversion increases the switching frequency by increasing the frequency of the periodic signal in the PWM mode when an event occurs. An event that causes the device to increase the frequency of the periodic signal may also be referred to hereinafter as a "trigger event". Thereby, the switching frequency in the PWM mode can advantageously be dynamically changed in dependence of events, i.e. the switching frequency is switchable. In this way, the voltage conversion performance can be improved, and the loss of the electric energy utilization efficiency caused by the operation at the preset high switching frequency can be relieved. Embodiments of the present disclosure may achieve a balance between voltage conversion performance and power utilization efficiency.

Various example embodiments of the present disclosure will be described below with reference to the accompanying drawings. Fig. 1 shows a schematic block diagram of an electronic device 100 to which embodiments of the present disclosure can be applied. As shown, the electronic device 100 includes a processor 101. The Processor 101 may be any suitable type of Processing Unit, including but not limited to a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), an Artificial Intelligence (AI) based Processing Unit, and the like.

The processor 101 may perform various appropriate actions and processes in accordance with computer program instructions stored in a Read-Only Memory (ROM) 102 or loaded from a storage unit 108 into a Random Access Memory (RAM) 103. In the random access memory 103, various programs and data necessary for the operation of the electronic apparatus 100 can also be stored. The processor 101, the read only memory 102 and the random access memory 103 are connected to each other by a bus 104. An Input/Output (I/O) interface 105 is also connected to the bus 104.

The electronic device 100 further includes a power supply unit 110. The power supply unit 110 may supply power required for operation to components within the electronic device 100. In some embodiments, the power supply unit 110 may include a PMIC.

A number of components in the electronic device 100 are connected to the I/O interface 105, including: an input unit 106 such as a keyboard, a mouse, and the like; an output unit 107 such as various types of displays, speakers, and the like; a storage unit 108, such as a magnetic disk, optical disk, or the like; and a communication unit 109 such as a network card, modem, wireless communication transceiver, etc. The communication unit 109 allows the electronic apparatus 100 to exchange information or data with other apparatuses through a computer network such as the internet or various telecommunication networks.

The processor 101 may perform methods and processes. For example, in some embodiments, the methods and processes may be implemented as a computer software program or computer program product that is tangibly embodied in a machine-readable medium, such as storage unit 108. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 100 via the read only memory 102 and/or the communication unit 109.

In some embodiments, multiple components in electronic device 100 may be integrated on the same chip. For example, components including, but not limited to, processor 101, bus 104, read only memory 102, random access memory 103 may be integrated on the SoC. As another example, the processor 101, the bus 104, and the communication unit 109 may be integrated on an SoC, which is defined as a first chip.

In some embodiments, electronic device 100 may comprise a smartphone. In some embodiments, the electronic device 100 may include at least one of: a set top box, an entertainment unit, a navigation device, a communications device, a fixed location data unit, a mobile phone, a cellular phone, a tablet computer, a phablet, a computer, a portable computer, a desktop computer, a Personal Digital Assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a Digital music player, a portable music player, a Digital video player, a Digital Video Disc (DVD) player, a portable Digital video player, and the like.

Fig. 2 illustrates a schematic block diagram of an electronic device 200 in accordance with some embodiments of the present disclosure. The electronic device 200 may be implemented in the electronic device 100. As shown in fig. 2, the electronic device 200 includes a processor 101. The processor 101 is configured to generate a frequency translated signal in response to the occurrence of an event. The specific operation of the processor 101 will be described below with reference to fig. 11. In some embodiments, processor 101 may be integrated on a SoC.

The electronic device 200 further comprises means 210 for direct voltage conversion, which may also be referred to below simply as converting means 210, in communication with the processor 101. The conversion means 210 is configured to convert the direct voltage Vin into a direct voltage Vout. In other words, the converting means 210 may convert the input voltage into the output voltage to be provided to the load. The load may include the processor 101. Alternatively or additionally, the load may comprise one or more other components of the electronic device 100, such as the read only memory 102, the random access memory 103, the storage unit 108, the communication unit 109, etc. The input voltage may come from a battery or a charging adapter of the electronic device 100, or may come from an output of the power supply unit 110 or other circuitry within the PMIC. The means 210 for dc voltage conversion may be located inside the power supply unit 110, for example inside the PMIC. Alternatively, the means 210 for dc voltage conversion may be another chip independent from the PMIC, which is not limited in this embodiment. The means 210 for dc voltage conversion is typically on a different chip than the SoC on which the processor 101 is located, i.e. the means 210 may be located on a second chip and coupled to the processor 101 within the SoC through an interface. The apparatus 210 may interact with the processor 101 via an interface as shown in fig. 2, and may refer to various signals described later.

The switching device 210 may operate in a PWM mode. The switching device 210 may be configured with a plurality of PWM modes of different switching frequencies. For example, if a triggering event occurs, the switching device 210 may increase the frequency of the periodic signal in the PWM mode, thereby switching to the high frequency PWM mode. If the triggering event is over, the switching device 210 may decrease the frequency of the periodic signal in the PWM mode, thereby switching back to the low frequency PWM mode. That is, the converting device 210 can selectively adjust the frequency of the periodic signal to better adapt to the system requirements.

In some embodiments, the conversion device 210 may also be configured with a Pulse-Frequency Modulation (PFM) mode to improve the efficiency of the conversion device 210 under light load conditions. For example, if the load current is less than a predetermined value, the switching device 210 may switch to the PFM mode. That is, the switching device 210 can dynamically reduce the switching frequency according to the load current, so as to improve the power supply efficiency under the light load condition.

The conversion means 210 may be implemented as a part of the power supply unit 110 shown in fig. 1. In some embodiments, the conversion device 210 may be at least a portion of a PMIC. The conversion device 210 may include any suitable dc-dc type circuit having a PWM mode, including but not limited to a BUCK (BUCK) circuit, a BOOST (BOOST) circuit, a BUCK-BOOST (BUCK-BOOST) circuit, a Switched-Capacitor (SC) circuit, a charge pump, a switching Low Dropout regulator (LDO), and the like. Alternatively, the conversion device 210 may be independent of the power supply unit 110 or the PMIC.

Fig. 3 illustrates a schematic block diagram of an apparatus 210 for dc voltage conversion according to some embodiments of the present disclosure. As shown, for frequency conversion, the conversion device 210 includes a frequency converter 310. The frequency converter 310 is configured to increase the frequency of the periodic signal Vp from the first frequency to the second frequency based on the selection signal S1. The selection signal S1 may indicate the occurrence of a triggering event. The conversion means 210 further comprises a voltage regulator 350 coupled to the frequency converter 310. The voltage regulator 350 is configured to convert the dc voltage Vin into the dc voltage Vout based on the periodic signal Vp of the second frequency in the PWM mode. The dc voltage Vin, also called the first dc voltage in the embodiment, is the input voltage of the voltage regulator 350. The dc voltage Vout, also called the second dc voltage in the embodiment, is the output voltage of the voltage regulator 350.

In some embodiments, the frequency converter 310 may be further configured to decrease the frequency of the periodic signal Vp from the second frequency based on a selection signal S2 (not shown in fig. 3) different from the selection signal S1. The selection signal S2 may indicate the end of the triggering event. Accordingly, the voltage regulator 350 may be further configured to convert the dc voltage Vin to the dc voltage Vout based on the periodic signal Vp having a frequency lower than the second frequency in the PWM mode. The frequency converter 310 may decrease the frequency of the periodic signal Vp from the second frequency back to the first frequency based on the selection signal S2. Alternatively, the frequency converter 310 may decrease the frequency of the periodic signal Vp from the second frequency to a third frequency different from the first frequency based on the selection signal S2. This may be the case, for example, in the embodiment described below with reference to fig. 9.

In some embodiments, the periodic signal Vp may be a ramp signal, which is also referred to as a triangular wave signal. For example, in the case where the voltage regulator 350 is a closed-loop mode voltage regulator, the periodic signal Vp may be a ramp signal, such as the embodiments described below with reference to fig. 5-8. In some embodiments, the periodic signal Vp may be a PWM signal. For another example, where the voltage regulator 350 is an open-loop mode voltage regulator, the periodic signal Vp may be a PWM signal, such as the embodiment described below with reference to fig. 11.

In some embodiments, the selection signal S1 and the selection signal S2 may be two different indications or indication states of the same indication signal received by the frequency converter 310. For example, taking the example that the indication signal is a 1 bit (bit) signal, the high level of the indication signal indicates the occurrence of the trigger event, i.e., the indication signal is embodied as the selection signal S1; the low level of the indication signal indicates the end of the trigger event, i.e. the indication signal is embodied as the selection signal S2. Alternatively, the selection signal S1 and the selection signal S2 may be two independent indication signals. Although the following embodiments describe the selection signal S1 and the selection signal S2 as being represented by two different indication values or indication states of the same indication signal, it should be understood that embodiments of the present disclosure are not limited in this respect.

The switching frequency of the switching device 210 in the PWM mode depends on the frequency of the periodic signal Vp. Therefore, the conversion of the frequency of the periodic signal Vp between the low frequency (e.g., the first frequency or the third frequency) and the high frequency (e.g., the second frequency) causes the switching frequency of the conversion device 210 in the PWM mode to be converted between the high frequency and the low frequency. The following describes an example of the conversion of the frequency of the periodic signal Vp between the first frequency and the second frequency. Herein, the PWM mode corresponding to the first frequency is referred to as a "first PWM mode", and the PWM mode corresponding to the second frequency is referred to as a "second PWM mode".

Fig. 4 illustrates a graph 400 of switching frequency versus load current, in accordance with some embodiments of the present disclosure.

Curves

451 and 452 show the switching frequency versus load current in the first PWM mode and the second PWM mode, respectively. As shown, the switching device 210 may be switched between a first PWM mode and a second PWM mode. As indicated by dashed line 453, in some embodiments, the transition device 210 may operate in PFM mode if the load current is less than a predetermined value.

In this context, the base PWM mode refers to the PWM mode in which the switching device 210 is in when no triggering event occurs. The high frequency PWM mode refers to the PWM mode in which the switching device 210 is in during the occurrence of a triggering event. It will be appreciated that the high frequency PWM mode is a transient mode compared to the base PWM mode. In fig. 4, the first PWM mode may be regarded as a base PWM mode, and the second PWM mode may be regarded as a high frequency PWM mode.

As an example, the triggering event may be the voltage regulator 350 being started. For example, when the voltage regulator 350 is in the slow start phase, the switching device 210 may switch to the second PWM mode to achieve fast start. After the soft start is completed, the switching device 210 may switch back to the first PWM mode.

Alternatively or additionally, in other embodiments, the triggering event may be that a target value of the dc voltage Vout is adjusted, indicating that the voltage regulator 350 has entered or is about to enter a voltage adjustment phase, and that the particular dc voltage Vout may be adjusted by the reference signal Vref. For example, when the voltage regulator 350 is in the voltage regulation phase, the converting means 210 may switch to the second PWM mode to achieve fast voltage regulation. After the voltage regulation is completed, the switching device 210 may switch back to the first PWM mode. In this embodiment, the output voltage switching of the voltage regulator 350 occurs during the voltage adjustment stage, and in order to increase the output voltage switching or adjusting speed, the switching device 210 enters the second PWM mode and switches back to the first PWM mode after the voltage switching or adjusting is finished.

As another example, in some examples, the triggering event may be the actual value of the dc voltage Vout exceeding a predetermined range. The converter device 210 may monitor the dc voltage Vout. For example, if the actual value of the dc voltage Vout falls below a threshold value, the switching means 210 may switch to the second PWM mode. The high switching frequency in the second PWM mode can reduce the droop amplitude of the dc voltage Vout. When the actual value of the dc voltage Vout is restored to the predetermined range, the switching device 210 may switch back to the first PWM mode. Likewise, if the actual value of the dc voltage Vout rises above the threshold, the conversion means 210 may operate similarly. This can reduce the overshoot amplitude of the dc voltage Vout. Alternatively or additionally, the conversion means 210 may also determine a change in the actual value of the dc voltage Vout by monitoring the output current.

It should be understood that the triggering events described above are merely exemplary and are not intended to limit the scope of the present disclosure. In embodiments of the present disclosure, one or more of the above-described triggering events, as well as any other suitable events, may be considered.

In a conventional scheme, the switching device employs a single switching frequency in the PWM mode. If the switching frequency is low, the voltage conversion performance is not good, for example, the device start-up speed is slow, the voltage regulation is slow, and the overshoot or the dip amplitude of the output voltage is large. If the switching frequency is high, the electric energy utilization efficiency is reduced, resulting in energy efficiency waste, although the voltage conversion performance is improved. There is a drawback to using a predetermined fixed switching frequency. In an embodiment of the present disclosure, the switching frequency in the PWM mode is dynamically changed according to the triggering event, i.e. the switching frequency is no longer fixed but can be switched. Thus, an increase in switching frequency during a triggering event may improve voltage conversion performance. Lower switching frequencies may mitigate the reduction in power utilization efficiency during the absence of a triggering event. In this way, a balance between the voltage conversion performance and the electric energy utilization efficiency can be achieved.

Fig. 5 illustrates a schematic block diagram of an apparatus 210-1 for dc voltage conversion according to some embodiments of the present disclosure. The switching arrangement 210-1 may be considered as a specific implementation of the switching arrangement 210, wherein the frequency converter 310-1 is a specific implementation of the frequency converter 310, the voltage regulator 350-1 in closed-loop mode is a specific implementation of the voltage regulator 350, and the ramp-form periodic signal Vramp is a specific implementation of the periodic signal Vp. As shown, in some embodiments, the translation device 210-1 may also include a select signal determination circuit 520. The selection signal determination circuit 520 is coupled to the frequency converter 310-1 and configured to determine the selection signal S1 or the selection signal S2 based on at least one event signal and output the selection signal S1 or the selection signal S2. For example, the select signal determination circuit 520 may receive one or more event signals and output the select signal S1 or the select signal S2 based on whether the one or more event signals are valid. The one or more event signals may include, but are not limited to, an event signal indicating that the voltage regulator 350-1 is enabled, an event signal indicating that a target value of the dc voltage Vout is adjusted, an event signal indicating that an actual value of the dc voltage Vout is outside a predetermined range.

It should be understood that in embodiments where only one event signal is present, the switching device 210-1 may not include the selection signal determination circuit 520. In such an embodiment, the event signal may be provided directly to the frequency translator 310-1 as the select signal.

Frequency translator 310-1 may include a multiplexer 512. The multiplexer 512 may be configured to select one ramp signal from a ramp signal F1_ Vramp having a first frequency and a ramp signal F2_ Vramp having a second frequency as the periodic signal Vramp based on a selection signal. In the embodiment of fig. 5, the periodic signal Vramp is implemented as a ramp signal.

Specifically, in such an embodiment, the multiplexer 512 is configured to select the ramp signal F2_ Vramp as the periodic signal Vramp from the ramp signal F1_ Vramp and the ramp signal F2_ Vramp based on the selection signal S1 indicating the occurrence of the trigger event. The multiplexer 512 is further configured to: the ramp signal F1_ Vramp is selected as the periodic signal Vramp from the ramp signal F1_ Vramp and the ramp signal F2_ Vramp based on the selection signal S2 indicating the end of the trigger event.

By configuring the multiplexer 512 in this way, the frequency of the periodic signal Vramp can be shifted in response to the occurrence and the end of the trigger event, thereby switching the switching device 210-1 between the first PWM mode and the second PWM mode. In other words, the switching frequency is no longer fixed but is switchable. Thus, during the occurrence of a triggering event, the benefits of the high frequency PWM mode may be obtained, improving voltage conversion performance. After the triggering event is finished, the low-frequency PWM mode is switched back to avoid the loss of the electric energy utilization efficiency under the high frequency. The voltage conversion performance and the power utilization efficiency can be balanced according to the embodiments of the present disclosure.

As shown in fig. 5, the select signal S1 and the select signal S2 are represented as two different indication values or indication states of the same indication signal. As briefly described above, the select signal S1 and the select signal S2 may also be two independent indication signals. For example, the enable of the selection signal S1 may supply the ramp signal F2_ Vramp to the input terminal of the comparator 556 as a periodic signal, and the enable of the selection signal S2 may supply the ramp signal F1_ Vramp to the input terminal of the comparator 556 as a periodic signal.

In the embodiment shown in fig. 5, voltage regulator 350-1 may include a comparator 556, a switch driver circuit 558, a switching circuit 560, an error amplifier 554, and a loop compensator 530. Comparator 556 is coupled to frequency converter 310-1. For example, the comparator 556 may be coupled to an output of the multiplexer 512 to receive the periodic signal Vramp. Comparator 556 is configured to generate a PWM signal based on periodic signal Vramp and an error signal from error amplifier 554. The frequency of the PWM signal generated by the comparator 556 is the same as the frequency of the periodic signal Vramp.

The switch drive circuit 558 is coupled to the comparator 556 to receive the PWM signal and is configured to generate a switch drive signal based on the PWM signal. The switch circuit 560 is coupled to the switch drive circuit 558 and is configured to convert the direct current voltage Vin to a direct current voltage Vout based on the switch drive signal. Specifically, depending on the particular type of voltage regulator 350-1, switching circuit 560 may include a plurality of transistors, such as metal-oxide-semiconductor field-effect transistors (MOSFETs). The switch driving signal may control the alternate conduction of the plurality of transistors, thereby converting the dc voltage Vin into the dc voltage Vout.

The error amplifier 554 is coupled to the comparator 556 and is configured to generate an error signal provided to the comparator 556 based on the reference signal Vref and a feedback signal Vfb indicative of the dc voltage Vout. The magnitude of the dc voltage Vout output by the converting means 210-1 in steady state will depend on the setting of the reference signal Vref, i.e. the reference signal Vref may determine the value of the output voltage Vout.

The loop compensator 530 is coupled to the error amplifier 554 and the output of the voltage regulator 350-1. The loop compensator 530 is configured to adjust the pole-zero configuration of the loop in which it is located. Thus, a negative feedback mechanism is formed within the voltage regulator 350-1. The use of the loop compensator 530 to adjust the pole-zero configuration ensures stable operation of the voltage regulator 350-1 within a certain bandwidth. The specific circuitry of the loop compensator is not shown in fig. 5. It will be appreciated that loop compensator 530 may include one or more components in parallel with error amplifier 554 and one or more components between the input of the error amplifier receiving feedback signal Vfb and the output of voltage regulator 350-1.

The configuration of the loop compensation may also be different in PWM modes with different switching frequencies. In some embodiments, the loop compensator 530 may include multiple loop compensation circuits for PWM modes of different switching frequencies. As shown in fig. 5, the first loop compensation circuit 531 may be used for a first PWM mode and the second loop compensation circuit 532 may be used for a second PWM mode. The loop compensator 530 may receive the select signal S1 or the select signal S2. In response to the selection signal S2, the first loop compensation circuit 531 is connected to the loop to adjust the pole-zero configuration. Or in response to the select signal S1, the second loop compensation circuit 532 is connected to the loop to adjust the pole-zero configuration.

In such an embodiment, the respective loop compensation circuit is selected in PWM modes at different switching frequencies. In this way, accurate loop compensation can be performed for PWM modes of different switching frequencies, such that the voltage regulator 350 can operate stably at different switching frequencies.

Some examples of apparatus for dc voltage conversion according to some embodiments of the present disclosure are described below with reference to fig. 6-8. FIG. 6 illustrates a schematic diagram of an apparatus 210-1-1 for DC voltage conversion according to some embodiments of the present disclosure. The switching apparatus 210-1-1 may be considered a specific implementation of the switching apparatus 210-1, wherein the OR gate 520-1 is a specific implementation of the selection signal determining circuit 520, the voltage regulator 350-1-1 is a specific implementation of the voltage regulator 350-1, and the switching circuit 560-1 is a specific implementation of the switching circuit 560.

As an example, fig. 6 shows event signals Vsoft _ going, Vset _ going, and Vdrop _ going. While the voltage regulator 350-1-1 is in a start-up process (e.g., a soft start-up process), the event signal vsoftgoing is active; after the start-up is finished, the event signal vsoftgoing is zeroed. The event signal Vset _ going is asserted while the voltage regulator 350-1-1 is in regulation of the dc voltage Vout (e.g., because the target value of the dc voltage Vout is regulated); after the adjustment is finished, the event signal Vset _ going is zeroed. The event signal Vdrop _ going is active during the period that the actual value of the direct current voltage Vout exceeds the predetermined range; after the actual value of the dc voltage Vout is restored to the predetermined range, the event signal Vdrop _ going is zeroed. Accordingly, the or gate 520-1 outputs the selection signal S1 at a high level as long as any one or more of the event signals vsoftgoing, Vset _ going, and Vdrop _ going are active. When the event signals vsoftgoing, Vset going and Vdrop going are all zeroed, the or gate 520-1 will output the select signal S2 at "0".

The assertion of the event signals vsoftgoing, Vset going may depend on instructions or signals from the processor 101. The validity of the event signal Vdrop _ going may depend on internal detection of the device 210, for example the detection of the dc voltage Vout. Zeroing of the event signals Vsoft _ going, Vset _ going and Vdrop _ going may all depend on internal detection of the device 210. This will be described below with reference to several figures.

The control terminal of the multiplexer 512 is coupled to the output terminal of the OR gate 520-1 to receive the select signal S1 or the select signal S2. Two input terminals of the multiplexer 512 respectively receive a ramp signal F1_ Vramp having a first frequency and a ramp signal F2_ Vramp having a second frequency. If the control terminal receives the selection signal S1, the multiplexer 512 selects the ramp signal F2_ Vramp as the periodic signal Vramp. If the control terminal receives the selection signal S2, the multiplexer 512 selects the ramp signal F1_ Vramp as the periodic signal Vramp.

In this way, the multiplexer 512 will select the ramp signal F2_ Vramp having the higher second frequency as the periodic signal Vramp if any event signal is active. After the event signals are all zeroed, the multiplexer 512 will select the ramp signal F1_ Vramp with the lower first frequency as the periodic signal Vramp.

Comparator 556 is coupled to the output of multiplexer 512 to receive periodic signal Vramp. The comparator 556 generates a PWM signal having the same frequency as the periodic signal Vramp based on the periodic signal Vramp and the error signal from the error amplifier 554. The switch drive circuit 558 is coupled to the comparator 556 to receive the PWM signal and generate a switch drive signal based on the PWM signal. Switch circuit 560-1 is coupled to switch drive circuit 558 to receive the switch drive signal. The switch driving signal controls the alternate conduction of the upper transistor 661 and the lower transistor 662, thereby converting the input voltage from the power supply PVDD to the direct current voltage Vout. In fig. 6, the upper transistor 661 is a P-type metal-oxide-semiconductor (PMOS) transistor, the lower transistor 662 is an N-type metal-oxide-semiconductor (NMOS) transistor, and similar transistors in subsequent figures are defined herein with reference to like drawings.

Loop compensator 530 is coupled to error amplifier 554 and the output of voltage regulator 550 to adjust the pole-zero configuration of the loop. In some embodiments, the loop compensator 530 may include both the first loop compensation circuit 531 for the first PWM mode and the loop compensation circuit 532 for the second PWM mode. In such an embodiment, the loop compensator 530 may be further coupled to an output of the OR gate 520-1 to receive the select signal S1 or the select signal S2.

The two inputs of the error amplifier 554 receive the feedback signal Vfb and the reference signal Vref, respectively. An output of the error amplifier 554 is coupled to a comparator 556 to provide an error signal generated based on the feedback signal Vfb and the reference signal Vref to the comparator 556. The feedback signal Vfb may be used to reflect the magnitude of the dc voltage Vout, and may be selectively equal to the dc voltage Vout or a divided voltage of the dc voltage Vout, which is not limited in this embodiment.

In general, the magnitude of the DC voltage Vout output by the voltage regulator 350-1 can be achieved by changing the setting of the reference signal Vref. For example, during the start-up of the voltage regulator 350-1, the voltage of the reference signal Vref is slowly adjusted to achieve a slow rise of the voltage of the DC voltage Vout. As shown in fig. 6, the control terminal of the multiplexer 652 receives the event signal vsoftgoog. Assertion of the event signal VsoftGOING indicates that the voltage regulator 350-1-1 is in the process of being enabled, at which time Vsoft is selected by the multiplexer 652 as the reference signal Vref; after the start-up is completed, the event signal Vsoft _ going is zeroed, and the multiplexer 652 selects Vset as the reference signal Vref. Vsoft denotes a reference soft start signal, and Vset corresponds to a target value of the dc voltage Vout and may be configured by, for example, the processor 101.

Based on fig. 6, in the embodiment of the present invention, the frequency converter 310-1 is configured to convert the frequency of the periodic signal based on the selection signal S1/S2, and increase the frequency of the periodic signal Vp from the first frequency to the second frequency based on the selection signal S1 when at least one event occurs; when all of the at least one event is over, the frequency of the periodic signal Vp is decreased from the second frequency based on the selection signal S2, so that the switching frequency of the voltage regulator 350-1 in the pwm mode, i.e., the frequency of the periodic signal Vramp, is variable, resulting in the switching frequency of the switching circuit 560 no longer being fixed but being changeable. In this way, system requirements can be better adapted.

FIG. 7 illustrates a schematic diagram of an apparatus 210-1-2 for DC voltage conversion according to further embodiments of the present disclosure. The switching apparatus 210-1-2 may be considered as another specific implementation of the switching apparatus 210-1, wherein the OR gate 520-1 is one specific implementation of the selection signal determining circuit 520, the voltage regulator 350-1-2 is one specific implementation of the voltage regulator 350-1, and the switching circuit 560-2 is one specific implementation of the switching circuit 560.

FIG. 8 illustrates a schematic diagram of an apparatus 210-1-3 for DC voltage conversion according to still further embodiments of the present disclosure. The switching apparatus 210-1-3 may be viewed as yet another specific implementation of the switching apparatus 210-1, wherein the OR gate 520-1 is one specific implementation of the selection signal determination circuit 520, the voltage regulator 350-1-3 is one specific implementation of the voltage regulator 350-1, and the switching circuit 560-3 is one specific implementation of the switching circuit 560.

The same portions of the transition devices 210-1-2, 210-1-3 as the transition device 210-1-1 will not be described repeatedly herein. The switching devices 210-1-2, 210-1-3 differ from the switching device 210-1-1 in the type of voltage regulator. The voltage regulator 350-1-1 of the conversion apparatus 210-1-1 is of the BUCK type and includes a switching circuit 560-1 of the BUCK type. In contrast, the voltage regulator 350-1-2 of the switching device 210-1-2 is of the BOOST type and includes a switching circuit 560-2 of the BOOST type. The voltage regulators 350-1-3 of the conversion means 210-1-3 are of the BUCK-BOOST type and comprise switching circuits 560-3 of the BUCK-BOOST type.

The voltage regulators described above with reference to fig. 6-8 are closed loop mode voltage regulators. It should be understood that in addition to the types of voltage regulators shown in fig. 6-8, embodiments of the present disclosure may also be applied to other types of dc-dc circuits having a PWM mode, including but not limited to switched capacitor circuits, charge pumps, switching LDOs, and the like.

FIG. 9 illustrates a schematic diagram of a frequency translator 310-1-1, according to some embodiments of the present disclosure. Frequency translator 310-1-1 may be considered a specific implementation of frequency translator 310-1. In the embodiment of fig. 9, frequency converter 310-1-1 may include a multiplexer 914 in addition to multiplexer 512. Multiplexer 914 is coupled to multiplexer 512. The multiplexer 914 may be configured to select one ramp signal from the ramp signal F4_ Vramp having the fourth frequency and the ramp signal F5_ Vramp having the fifth frequency as the ramp signal F1_ Vramp based on a selection signal S3 indicating a specification constraint of the load.

Specifically, the control terminal of the multiplexer 914 receives the selection signal S3. Two input terminals of the multiplexer 914 respectively receive the ramp signal F4_ Vramp having the fourth frequency and the ramp signal F5_ Vramp having the fifth frequency. The multiplexer 914 may be configured to select one from the ramp signal F4_ Vramp and the ramp signal F5_ Vramp as the ramp signal F1_ Vramp based on the selection signal S3.

The selection signal S3 represents the specification constraints of the load. In general, the load has requirements on the voltage provided by the device for dc voltage conversion based on its own specifications, for example, the specification constraints include: a requirement for a ripple voltage included in the voltage, a requirement for a transient response speed, or the like. The specification constraints of the load may be determined by the processor 101 according to the power supply requirements of the currently enabled load or the load to be enabled.

The ripple voltage constraint is described below as an example. The ripple voltage constraint of the load may be determined by the processor 101 according to the ripple voltage requirements of the currently enabled load or the load to be enabled (described in detail below). In this context, the ripple voltage requirement of the load refers to the maximum ripple voltage that the load can withstand. Different loads have different levels of ripple voltage requirements, and the magnitude of the ripple voltage in the dc voltage Vout is influenced by the switching frequency in the PWM mode. The higher the switching frequency, the smaller the ripple voltage. It is assumed here that the fourth frequency is higher than the fifth frequency. If the ripple voltage constraint of the load indicates that the load requires a relatively small ripple voltage, the selection signal S3 causes the ramp signal F4_ Vramp to be selected as the ramp signal F1_ Vramp. If the ripple voltage constraint of the load indicates that the load can withstand a relatively large ripple voltage, the selection signal S3 causes the ramp signal F5_ Vramp to be selected as the ramp signal F1_ Vramp.

In such an embodiment, the frequency of the ramp signal F1_ Vramp may be the fourth frequency or the fifth frequency depending on the selection signal S3. Since the frequency of the ramp signal F1_ Vramp corresponds to the switching frequency of the switching device 210 in the basic PWM mode, the switching frequency in the basic PWM mode may be the fourth frequency or the fifth frequency. The PWM mode corresponding to the fourth frequency is referred to herein as a "fourth PWM mode". In the fourth PWM mode, the ramp signal F4_ Vramp is selected as the periodic signal Vramp. The PWM mode corresponding to the fifth frequency is referred to as a "fifth PWM mode". In the fifth PWM mode, the ramp signal F5_ Vramp is selected as the periodic signal Vramp.

Fig. 10 shows a graph 1000 of switching frequency versus load current for a further optimized embodiment based on the embodiment of fig. 4, according to some embodiments of the present disclosure.

Curves

452, 1053, 1054 show the switching frequency versus load current for the second, fourth, and fifth PWM modes, respectively. The second PWM mode is the high frequency PWM mode described above. It is understood that the fourth PWM mode and the fifth PWM mode are both base PWM modes.

As shown in fig. 10, during the absence of a triggering event, the switching device 210 may operate in the fourth PWM mode or the fifth PWM mode depending on the selection signal S3 representing the specification voltage constraint of the load. During the occurrence of the triggering event, the switching means 210 will switch to the second PWM mode, i.e. the high frequency PWM mode.

Since the frequency converter selects the ramp signal F1_ Vramp as the periodic signal Vramp in the base PWM mode, the switching frequency in the base PWM mode is the same as the frequency of the ramp signal F1_ Vramp. That is, in such embodiments, the switching frequency in the base PWM mode may differ depending on the specification voltage constraints of the load.

Thus, in such embodiments, in addition to implementing dynamic switching of the switching frequency based on the triggering event, the switching frequency in the basic PWM mode may be configured based on the load's requirements for the supply voltage (e.g., requirements for ripple voltage). For example, in the case where the load can withstand a large ripple voltage, the switching frequency in the basic PWM mode may be reduced. Thus, the electric energy utilization efficiency can be improved without reducing the voltage conversion performance.

Fig. 11 illustrates a schematic structural diagram of an apparatus 210-2 for dc voltage conversion according to some embodiments of the present disclosure. The conversion means 210-2 can be seen as a specific implementation of the conversion means 210, wherein the frequency converter 310-2 is a specific implementation of the frequency converter 310, the open-loop mode voltage regulator 350-2 is a specific implementation of the voltage regulator 350, and the periodic signal Vpwm in PWM form is a specific implementation of the periodic signal Vp. The voltage regulator 350-2 in the open-loop mode does not have a feedback loop, and therefore, there is no circuit for realizing a feedback loop such as a comparator, so that the switch drive circuit 1158 directly receives the periodic signal Vpwm in the PWM form output from the multiplexer 1112. The magnitude of the dc voltage Vout output by the voltage regulator 350-2 in the open-loop mode is proportional to the magnitude of the input dc voltage Vin. The ratio is determined by the topology of the power stage circuit. Therefore, the dc voltage Vout will change as the dc voltage Vin changes.

As shown in FIG. 11, in some embodiments, the converting means 210-2 may further comprise a selection signal determining circuit 1120. In fig. 11, the selection signal determination circuit 1120 is shown as an or gate. The selection signal determination circuit 1120 is coupled to the frequency translator 310-2 and configured to determine the selection signal S1 or the selection signal S2 based on at least one event signal. For example, the select signal determination circuit 520 may receive one or more event signals and output the select signal S1 or the select signal S2 based on whether the one or more event signals are valid. As an example, fig. 11 shows event signals Vsoft _ going and Vdrop _ going. These event signals are similar to those described with reference to fig. 6, and the description of these event signals is not repeated here. Since the reference signal Vref is not present in fig. 11, the dc voltage Vout is not adjusted by the reference signal Vref, and therefore the event signal does not include Vset _ going.

It should be appreciated that in embodiments where only one event signal is present, the translation device 210-2 may not include the selection signal determination circuit 1120. In such an embodiment, the event signal may be provided directly to the frequency translator 310-2 as the select signal.

Frequency converter 310-2 may include a multiplexer 1112. The multiplexer 1112 may be configured to select one PWM signal from the PWM signal F1_ Vpwm having the first frequency and the PWM signal F2_ Vpwm having the second frequency as the period signal Vpwm based on the selection signal. In the embodiment of fig. 11, the periodic signal Vp is implemented as a PWM signal.

Specifically, a control terminal of the multiplexer 1112 is coupled to an output terminal of the selection signal determination circuit 1120 to receive the selection signal S1 or the selection signal S2. Two input terminals of the multiplexer 1112 receive the PWM signal F1_ Vpwm having the first frequency and the PWM signal F2_ Vpwm having the second frequency, respectively. If the control terminal receives the selection signal S1, the multiplexer 1112 selects the ramp signal PWM signal F2_ Vpwm as the periodic signal Vpwm. If the control terminal receives the selection signal S2, the multiplexer 512 selects the PWM signal F1_ Vpwm as the period signal Vpwm.

In some embodiments, frequency translator 310-2 may also include a multiplexer 1114. Multiplexer 1114 is coupled to multiplexer 1112. The multiplexer 1114 may be configured to select one PWM signal from among the PWM signal F4_ Vpwm having the fourth frequency and the PWM signal F5_ Vpwm having the fifth frequency as the PWM signal F1_ Vpwm based on the selection signal S3 indicating the specification constraint of the load.

Specifically, the control terminal of the multiplexer 1114 receives the selection signal S3. Two input terminals of the multiplexer 1114 receive the PWM signal F4_ Vpwm having the fourth frequency and the PWM signal F5_ Vpwm having the fifth frequency, respectively. The multiplexer 1114 may be configured to select one of the PWM signal F4_ Vpwm and the PWM signal F5_ Vpwm as the PWM signal F1_ Vpwm based on the selection signal S3. The selection signal S3 is similar to that described above with reference to fig. 9, and the description of the selection signal S3 is not repeated here.

In the embodiment shown in FIG. 11, voltage regulator 350-2 may include switch driver circuit 1158 and switch circuit 1160. Switch drive circuit 1158 is coupled to frequency translator 310-2 to receive periodic signal Vpwm. The switch drive circuit 1158 may be configured to generate a switch drive signal based on the periodic signal Vpwm. The switching circuit 1160 is coupled to the switch driving circuit 1158 and is configured to convert the direct current voltage Vin to a direct current voltage Vout based on the switch driving signal. In the embodiment of fig. 11, the switching circuit 1160 includes an SC type circuit, and optionally the dc voltage Vout is one-half of the dc voltage Vin.

Unlike the embodiments shown in fig. 6-8, in the embodiment shown in fig. 11, the switching device 210-2 includes a voltage regulator 350-2 in an open loop mode. Therefore, the event-based frequency translation scheme according to embodiments of the present disclosure may be applied to various types of voltage regulators, whether they are in an open-loop mode or a closed-loop mode.

The apparatus 210 for dc voltage conversion according to some embodiments of the present disclosure is described above with reference to fig. 3-11. Refer back to fig. 2. As mentioned above, the processor 101 and the conversion means 210 may communicate. An example of the processor 101 and the conversion means 210 cooperating to perform frequency conversion is described below in conjunction with fig. 2 and 12. Fig. 12 illustrates an example process 1200 of frequency translation according to some embodiments of the present disclosure.

As shown in fig. 11, the processor 101 determines 1205 whether a triggering event has occurred. If a triggering event occurs, the processor 101 generates a first frequency translation signal at 1210 and sends the first frequency translation signal to the conversion device 210 at 1215. The converting means 210 increases the frequency of the periodic signal from the first frequency to the second frequency in response to receiving the first frequency conversion signal at 1220, and converts the dc voltage Vin into the dc voltage Vout based on the periodic signal of the second frequency in the PWM mode.

The first frequency translation signal may enable the select signal S1 to increase the frequency of the periodic signal Vp from the first frequency to the second frequency. It should be understood that the conversion means 210 may comprise other components not shown in the figure in addition to the frequency converter 310 and the voltage regulator 350 shown in fig. 3. Such a component may be a switching component or an enabling component which enables the selection signal S1 based on the first frequency translated signal, i.e. generates the selection signal S1. For example, such a component may generate the event signal vsoftgoog or Vset _ going shown in fig. 6 to 8 and 11 or set the state of the event signal vsoftgoog or Vset _ going based on the first frequency conversion signal.

Alternatively, the apparatus 210 may determine the end of the trigger event and enable the selection signal S2 based on the end of the trigger event. The apparatus 210 may include a detection component for determining the end of a triggering event. Such a detection component may determine whether the triggering event is over by detecting an electrical parameter (e.g., voltage, current, power) internal to the device 210. In the case where it is determined that the trigger event is ended, the detection part may enable the selection signal S2, for example, to return the event signal vsoftgoing or Vset _ going to zero. Optionally, the detection component may be coupled to the enabling component. In the event that it is determined that the triggering event is over, the detection component may send a signal to the enable component, which may disable the select signal S1 while enabling the select signal S2 based on the signal from the detection component.

In some embodiments, the triggering event may include the transition device 210 being activated. If the processor 101 determines that the switching means 210 is activated, a first frequency converted signal may be generated. Accordingly, the conversion device 210 raises the frequency of the periodic signal Vp from the first frequency to the second frequency in response to receiving the first frequency conversion signal. Additionally, in some embodiments, the converting means 210 may also detect whether the start-up is over, and the operation of detecting whether the start-up is over may be performed by a detecting component inside the converting means 210. The detection component may determine whether the start is over by detecting an electrical parameter internal to the device 210. For example, if it is detected that the direct current voltage Vout has changed from zero to a preset value, the end of the startup may be determined. If the end of the start-up is detected, the conversion means 210 may decrease the frequency of the periodic signal Vp from the second frequency back to the first frequency.

For example, the first frequency conversion signal from the processor 101 may make the event signal vsoftgoing shown in fig. 6 to 8 valid. Thus, the multiplexer 512 may select the ramp signal F2_ Vramp as the periodic signal Vramp based on the selection signal S1. The event signal vsoftgoing may be zeroed if the end of the start is detected. For example, if it is detected that the direct current voltage Vout reaches a preset value, the above-described detection section or enable section may return the event signal vsoftgoing to zero. In the case where other event signals are also returned to zero, the multiplexer 512 may select the ramp signal F1_ Vramp as the periodic signal Vramp based on the selection signal S2.

Alternatively or additionally, in some embodiments, the triggering event may include the target value of the dc voltage Vout being adjusted. The first frequency converted signal may be generated if the processor 201 determines that the target value of the direct current voltage Vout is adjusted. Accordingly, the conversion device 210 raises the frequency of the periodic signal Vp from the first frequency to the second frequency in response to receiving the first frequency conversion signal. Additionally, in some embodiments, the converting means 210 may also detect the direct voltage Vout. For example, the detection means described above may be used to detect the direct-current voltage Vout. If it is detected that the dc voltage Vout reaches the target value, the conversion device 210 may decrease the frequency of the periodic signal Vp from the second frequency back to the first frequency.

For example, the first frequency conversion signal from the processor 101 may make the event signal Vset _ going shown in fig. 6 to 8 valid. Thus, the multiplexer 512 may select the ramp signal F2_ Vramp as the periodic signal Vramp based on the selection signal S1. The event signal Vset _ going may be zeroed if it is detected that the dc voltage Vout reaches the target value. For example, if the dc voltage Vout reaches a target value, the above-described detection part or enable part may return the event signal Vset _ going to zero. In the case where other event signals are also returned to zero, the multiplexer 512 may select the ramp signal F1_ Vramp as the periodic signal Vramp based on the selection signal S2.

Additionally, in some embodiments, the switching device 210 may also shift the frequency of the periodic signal in the PWM mode based on an internally detected triggering event. The transforming device 210 may detect an electrical parameter indicative of the current of a load (hereinafter also referred to as load current) coupled to the transforming device 210, which may be performed by a detecting means (not shown) within the transforming device 210. In case of an increase in the load current, the output voltage of the converting means 210 will decrease and the output current will increase; in case the load current decreases, the output voltage of the converting means 210 will increase and the output current will decrease. Thus, the conversion device 210 may detect an output voltage, an output current, or an output power. If it is detected that the electrical parameter is outside the predetermined range, the converting means 210 may increase the frequency of the periodic signal Vp from the first frequency to the second frequency. If it is detected that the electrical parameter returns to the predetermined range, the conversion means 210 may decrease the frequency of the periodic signal Vp from the second frequency back to the first frequency. The operation of detecting whether the electrical parameter is out of a predetermined range may also be performed by the detecting means. Therefore, the event triggering the frequency converter to raise the frequency of the periodic signal may be from the processor 101, or may be from a detection component inside the conversion device 210, which is not limited in this embodiment.

For example, if it is detected that the electrical parameter is outside the predetermined range, the conversion means 210 may assert the event signal Vdrop _ going shown in fig. 6 to 8. Thus, the multiplexer 512 may select the ramp signal F2_ Vramp as the periodic signal Vramp based on the selection signal S1. The event signal Vdrop _ going may be zeroed if it is detected that the electrical parameter returns to a predetermined range. For example, the above-mentioned detection means or enabling means may zero the event signal Vdrop _ going if it is detected that the electrical parameter returns to a predetermined range. In the case where other event signals are also returned to zero, the multiplexer 512 may select the ramp signal F1_ Vramp as the periodic signal Vramp based on the selection signal S2.

As mentioned above, in some embodiments, the switching frequency of the switching device 210 in the basic PWM mode may be adjusted based on the power requirements of the load. Fig. 13 illustrates a schematic block diagram of an electronic device 200 according to some embodiments of the present disclosure. As shown in FIG. 13, in addition to the processor 101 and the translation device 210, the electronic device 200 may also include loads 1321-1, 1321-2 powered by the translation device 210. Hereinafter, loads 1321-1, 1321-2 are also collectively referred to as loads 1321. The load 1321 may be in communication with the processor 101, and the processor 101 may control the enabling and disabling of the load 1321. The load 1321 may be any component in the electronic device 200, such as a camera, memory, other processor, etc. Alternatively, the processor 101 itself may be used as a load. In the embodiment of fig. 13, the processor 101 is also powered by the conversion means 210. In some embodiments, one or more of loads 1321-1, 1321-2 may be located on the same chip as processor 101, e.g., on the same SoC. Further, the number of loads shown in fig. 13 is merely illustrative and is not intended to limit the scope of the present disclosure.

Taking the ripple voltage as an example, different loads have different levels of requirements on the ripple voltage, and the magnitude of the ripple voltage in the dc voltage Vout is affected by the switching frequency in the PWM mode. The higher the switching frequency, the smaller the ripple voltage.

If the processor 101 determines that the load (e.g., the loads 1321-2) coupled to the conversion device 210 is to be enabled, the processor 1001 may determine a ripple voltage constraint for the dc voltage Vout. For example, the ripple voltage constraint may be determined based on the highest requirement for ripple voltage by the loads that have already been enabled and the loads that are to be enabled. Likewise, if one or more loads are disabled, the processor 101 may determine the ripple voltage constraint based on the ripple voltage requirements of the loads that are still enabled. In either case, the processor 101 may configure the switching frequency of the conversion device 210 in the fundamental PWM mode to a frequency that matches the ripple voltage constraint.

For example, if the processor 101 determines a ripple voltage constraint of the load, and generates the second frequency translated signal based on the ripple voltage constraint. The processor 101 sends the second frequency converted signal to the conversion means 210. In response to receiving the second frequency converted signal, the converting means 210 may set the above-mentioned first frequency of the periodic signal to one of a plurality of preset frequencies, which matches the ripple voltage constraint of the load. Optionally, the apparatus 210 may comprise a converting means or enabling means which determines or enables the selection signal S3, i.e. sets the state of the selection signal S3, based on the second frequency translated signal. The enable part that determines or enables the third selection signal S3 and the enable part that enables the first selection signal S1 may be the same or different parts, and this embodiment does not limit this. For example, the switch component or the enable component may set the state of the select signal S3 as shown in fig. 9 and 11 based on a second frequency translation signal from the processor 101. The selection signal S3 may have a plurality of states (such as a plurality of levels) corresponding to a plurality of preset frequencies, respectively. For example, in the case of two preset frequencies, the selection signal S3 may have an active state and a return-to-zero state.

As an example, assume that the load 1321-2 has a higher ripple voltage requirement than the load 1321-1 and the ramp signal F4_ Vramp has a higher frequency than the ramp signal F5_ Vramp. With both loads 1321-1 and 1321-2 enabled, or with loads 1321-2 enabled, the state of select signal S3 (e.g., select signal S3 active) will cause ramp signal F4_ Vramp to be selected as ramp signal F1_ Vramp. During the period when no trigger event occurs, the switching frequency of the switching device 210 in the PWM mode is the frequency of the ramp signal F4_ Vramp. For example, the switching device 210 operates in the fourth PWM mode shown in fig. 10. During the occurrence of the triggering event, the switching means 210 may switch to the second PWM mode, i.e. the high frequency PWM mode.

With load 1321-1 enabled and load 1321-2 not enabled, the state of select signal S3 (e.g., select signal S3 zeroed) will cause ramp signal F5_ Vramp to be selected as ramp signal F1_ Vramp. During the period when no trigger event occurs, the switching frequency of the switching device 210 in the PWM mode is the frequency of the ramp signal F5_ Vramp. For example, the switching device 210 operates in the fifth PWM mode shown in fig. 10. During the occurrence of the triggering event, the switching means 210 may switch to the second PWM mode, i.e. the high frequency PWM mode.

It should be understood that the switching frequency of the switching device 310 in the base PWM mode may also be adjusted based on other power requirements of the load (e.g., requirements for transient response speed, requirements for switching device start-up speed, etc.). In such an embodiment, the switching frequency in the basic PWM mode may be configured based on the power requirements of the load. When the power supply requirement of the load is high, the switching frequency of the converter can be increased appropriately, and the voltage conversion performance can be improved. When the power supply requirement of the load is low, the switching frequency of the converter can be appropriately reduced, and the power supply efficiency of the converter can be further improved.

The processor 101 may include any suitable type of processing unit, including but not limited to a CPU, GPU, artificial intelligence based processing unit, microprocessor, controller, microcontroller, or the like. The processor 101 may perform the various processes and actions described above in accordance with a computer software program. A computer software program may be tangibly embodied on a computer-readable medium.

The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination thereof. More detailed examples of a computer-readable storage medium include an electrical connection having one or more wires, a portable computer diskette, a hard disk, a RAM, a ROM, an erasable programmable Read-Only Memory (EPROM), a flash Memory, an optical fiber, a portable Compact Disc Read-Only Memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.

Claims

An apparatus for dc voltage conversion, comprising:

a frequency converter configured to increase a frequency of the periodic signal from a first frequency to a second frequency based on a first selection signal; and

a voltage regulator coupled to the frequency converter and configured to convert a first DC voltage to a second DC voltage based on the periodic signal of the second frequency in a pulse width modulation mode.
The apparatus of claim 1, wherein the frequency transformer is further configured to: reducing the frequency of the periodic signal from the second frequency to the first frequency based on a second selection signal different from the first selection signal; and

the voltage regulator is further configured to: in the pulse width modulation mode, the first direct current voltage is converted into the second direct current voltage based on the periodic signal of the first frequency.
The apparatus of claim 1, wherein the frequency transformer is further configured to: reducing the frequency of the periodic signal from the second frequency to a third frequency different from the first frequency based on a second selection signal different from the first selection signal; and

the voltage regulator is further configured to: in the pulse width modulation mode, the first direct current voltage is converted into the second direct current voltage based on the periodic signal of the third frequency.
The apparatus according to claim 2 or 3, wherein the first selection signal and the second selection signal are different indication states of the same indication signal, the first selection signal being used to indicate occurrence of at least one event, the second selection signal being used to indicate end of the at least one event.
The apparatus of claim 1, further comprising:

a selection signal determination circuit coupled to the frequency converter and configured to determine the first selection signal based on at least one event signal.
The apparatus of claim 5, wherein the at least one event signal comprises at least one of:

a first event signal indicating that the voltage regulator is enabled,

a second event signal indicating that the target value of the second DC voltage is adjusted, or

A third event signal indicating that the actual value of the second DC voltage is outside a predetermined range.
The apparatus of claim 5 or 6, wherein the selection signal determination circuit comprises an OR gate, an input of the OR gate being the at least one event signal, an output of the OR gate being the first selection signal.
The apparatus of any of claims 1-7, wherein the frequency converter comprises:

a first multiplexer configured to select the second candidate periodic signal as the periodic signal from a first candidate periodic signal having the first frequency and a second candidate periodic signal having the second frequency based on the first selection signal.
The apparatus of claim 8, wherein the frequency converter further comprises:

a second multiplexer coupled to the first multiplexer and configured to select one candidate periodic signal from a third candidate periodic signal having a fourth frequency and a fourth candidate periodic signal having a fifth frequency as the first candidate periodic signal based on a third selection signal representing a specification constraint of a load using the second direct current voltage.
The apparatus of claim 1, wherein the voltage regulator comprises:

an error amplifier configured to generate an error signal based on a reference signal and a feedback signal indicative of the second direct current voltage;

a comparator coupled to the error amplifier and the frequency converter and configured to generate a pulse width modulated signal based on the periodic signal and the error signal;

a switch drive circuit coupled to the comparator and configured to generate a switch drive signal based on the pulse width modulation signal; and

a switch circuit coupled to the switch drive circuit and configured to convert the first DC voltage to the second DC voltage based on the switch drive signal.
The apparatus of claim 10, wherein the voltage regulator further comprises:

a loop compensator coupled to the error amplifier and an output of the voltage regulator and configured to adjust a pole-zero configuration of a loop formed by the voltage regulator.
The apparatus of claim 11, wherein the loop compensator comprises:

a first loop compensation circuit configured to adjust the pole-zero configuration in response to a second select signal different from the first select signal; and

a second loop compensation circuit configured to adjust the pole-zero configuration in response to the first select signal.
An electronic device, comprising:

a processor configured to generate a first frequency translated signal in response to an occurrence of at least one event; and

an apparatus for DC voltage conversion coupled to the processor and configured to:

in response to receiving the first frequency converted signal, increasing the frequency of the periodic signal from a first frequency to a second frequency, an

In a pulse width modulation mode, converting a first direct current voltage to a second direct current voltage based on the periodic signal of the second frequency.
The electronic device of claim 13, wherein the at least one event comprises at least one of:

the device is activated, or

The target value of the second direct current voltage is adjusted.
The electronic device of claim 13 or 14, wherein the apparatus is further configured to:

in response to determining the end of the at least one event, decreasing the frequency of the periodic signal from the second frequency to the first frequency; and

in the pulse width modulation mode, the first direct current voltage is converted into the second direct current voltage based on the periodic signal of the first frequency.
The electronic device of claim 13, wherein the processor is further configured to:

determining specification constraint conditions of the load; and

generating a second frequency converted signal based on the specification constraint condition; and is

The apparatus is further configured to: setting the first frequency of the periodic signal to one of a plurality of preset frequencies in response to receiving the second frequency converted signal.