CN114078419A - Display control method and display control device - Google Patents
Display control method and display control device Download PDFInfo
- Publication number
- CN114078419A CN114078419A CN202010801777.3A CN202010801777A CN114078419A CN 114078419 A CN114078419 A CN 114078419A CN 202010801777 A CN202010801777 A CN 202010801777A CN 114078419 A CN114078419 A CN 114078419A
- Authority
- CN
- China
- Prior art keywords
- clock
- target
- display
- refreshing
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
Abstract
The present invention relates to a display control method and a display control apparatus, the method including: acquiring a target bit number and a target refreshing time corresponding to the target bit number; carrying out frequency multiplication on the gray level clock signal to obtain a gray level implementation clock after frequency multiplication; and performing T-round complete refreshing on the display unit array according to the target bit number and the multiplied gray scale implementation clock, wherein the value of T is a positive integer and is equal to the target refreshing time, and one frame of image refreshing is realized in each round of complete refreshing. The invention can solve the problem of abnormal display caused by incomplete gray scale display when the display screen performs gray scale display in the prior art, and improve the display effect of the display screen.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display control method and a display control apparatus.
Background
With the development of LED display technology, LED display screens are currently used in various fields due to their advantages of low cost, low power consumption, high visibility, freedom in assembly, etc. Meanwhile, with the popularization of the application of the LED display screen, people have higher and higher requirements on the display quality of the LED display screen, and therefore how to improve the display quality of the LED display screen becomes a research hotspot in the field.
At present, a PWM (Pulse Width Modulation) LED driving chip is generally used to drive and control an LED lamp panel to display, for example, a sixteen output channel PWM LED driving chip of a GCLK implementation clock based on gray scale is used to drive, at this time, if 16-bit gray scale data is displayed once, 65536 GCLK Pulse Width periods are needed at least, and the LED lamp point can be lighted at least in the time of one GCLK Pulse Width period, so that on one hand, the GCLK frequency is required to be relatively high, display of all gray scale data can be rapidly implemented, on the other hand, the GCLK frequency is required to be not too high, otherwise, the LED lamp point cannot be lighted, and the current PWM LED driving chip cannot implement 16-bit gray scale data within one frame time of an LED display screen, thus bringing about the problem of incomplete gray scale implementation to the LED display screen.
The existing processing method is to improve the frequency of the gray scale realization clock GCLK by using a PLL equal frequency doubling technology, thereby ensuring that the GCLK frequency can realize the display of all gray scale data and ensuring that LED lamp points are lightened. However, although the problem of GCLK frequency is solved in this method, the problem of incomplete gray scale realization of the LED display screen is not completely solved, that is, the problem of incomplete gray scale display during gray scale display of the LED display screen still occurs in the actual use process, and gray scale jump occurs.
Disclosure of Invention
Therefore, the embodiment of the invention discloses a display control method, a display control device, a display control system and a computer readable storage medium, which can solve the problem of display abnormality caused by incomplete gray scale display when a display screen performs gray scale display and improve the display effect of the display screen.
Specifically, in a first aspect, a display control method disclosed in an embodiment of the present invention includes: acquiring a target bit number and a target refreshing time corresponding to the target bit number; carrying out frequency multiplication on the gray level clock signal to obtain a gray level implementation clock after frequency multiplication; and performing T-round complete refreshing on the display unit array according to the target bit number and the multiplied gray scale implementation clock, wherein the value of T is a positive integer and is equal to the target refreshing time, and one frame of image refreshing is realized in each round of complete refreshing.
In the prior art, the frequency of a gray scale realization clock GCLK is improved by using a PLL (phase locked loop) equal frequency doubling technology, so that the GCLK frequency is ensured to realize the display of all gray scale data and ensure that LED lamp points are lightened, however, the problem of incomplete gray scale realization of an LED display screen is not completely solved although the problem of the GCLK frequency is solved by the method, namely, the problem of gray scale jump caused by incomplete gray scale display during gray scale display still occurs in the actual use process of the LED display screen, and abnormal display of the display screen is generated; in the embodiment of the invention, the target bit number and the corresponding target refreshing times are obtained, then the T-round complete refreshing is carried out on the display unit array based on the multiplied gray scale realization clock and the target bit number, wherein the value of T is a positive integer and is equal to the target refreshing times, and one frame of image refreshing is realized in each round of complete refreshing, so that the problem of abnormal display caused by incomplete gray scale display during gray scale display of the display screen in the prior art is solved, and the display effect of the display screen is improved.
In an embodiment of the present invention, before the obtaining the target number of bits and the target number of refreshes corresponding to the target number of bits, the method further includes: calculating and generating a plurality of data bit numbers and a plurality of groups of image refreshing wheel numbers respectively corresponding to the data bit numbers based on a preset bit number range, an input video source frequency, a frequency-multiplied gray scale realization clock frequency and N scanning lines included by the display unit array; selecting one data bit digit from the plurality of data bit digits as the target bit digit according to user input information, and taking the image refreshing round number corresponding to the target bit digit as the target refreshing time.
The target bit number is selected from the plurality of data bit numbers based on the user input information, and the image refreshing round number corresponding to the target bit number is used as the target refreshing time, so that the T-round complete refreshing setting can be realized according to the user selection, and the requirements of the user on different corresponding scenes are met.
In an embodiment of the present invention, the generating a plurality of data bit numbers and a plurality of groups of image refresh rounds corresponding to the plurality of data bit numbers respectively based on a preset bit number range, an input video source frequency, a multiplied gray scale implementation clock frequency, and N scan lines included in the display unit array by calculation includes: dividing based on the range of the preset bit digits to obtain the plurality of data bit digits; calculating to obtain an image display period based on the input video source frequency; calculating the frequency of the gray scale implementation clock after frequency multiplication to obtain the clock period of the gray scale implementation clock after frequency multiplication; obtaining a plurality of clock cycle numbers respectively corresponding to the plurality of data bit bits based on the plurality of data bit bits; calculating and generating corresponding single-round image refreshing time based on each clock cycle number, the clock cycle and the N scanning lines; and calculating and generating the corresponding image refreshing wheel number based on the single-wheel image refreshing time and the image display period.
In an embodiment of the present invention, after the calculating and generating the corresponding number of image refresh rounds based on the single-round image refresh time and the image display period, the method further includes: calculating the remaining time corresponding to the number of image refreshing rounds based on the single-round image refreshing time, the number of image refreshing rounds and the image display period; and calculating the number of extra clocks corresponding to the number of image refreshing rounds based on the remaining time, the number of image refreshing rounds, the N scanning lines and the clock period.
In an embodiment of the present invention, the performing a T-round complete refresh on a display cell array according to the target bit number and the multiplied gray scale implementation clock includes: acquiring the number of the extra clocks corresponding to the target bit number as the number of target extra clocks; and performing line scanning on the N scanning lines of the display unit array according to the multiplied gray scale implementation clock, the target bit number and the target extra clock number to implement one round of complete refreshing.
In an embodiment of the present invention, the performing row scanning on the N scanning lines of the display unit array according to the multiplied gray scale implementation clock, the target bit number and the target extra clock number to implement a round of complete refresh includes: sequentially generating a plurality of display driving signals respectively corresponding to the plurality of display units of each scanning line based on the multiplied gray scale implementation clock, the target bit number and the target extra clock number; driving and controlling the plurality of display units according to the plurality of display driving signals to complete line scanning of corresponding scanning lines; and generating a count zero clearing value corresponding to a clock based on the target bit number and the multiplied gray scale required by the line scanning to which the display driving signal belongs, wherein the sum of the gray scale number represented by the target bit number and the target extra clock number is equal to the count zero clearing value.
The sum of the gray level number represented by the target bit number and the number of the target extra clocks is set to be a counting clear zero value, so that the problem of abnormal display caused by an overlarge black field can be avoided, and the display effect of the display screen is further improved.
In a second aspect, a display control apparatus disclosed in an embodiment of the present invention includes: the data acquisition module is used for acquiring a target bit number and target refreshing times corresponding to the target bit number; the clock frequency multiplication module is used for carrying out frequency multiplication processing on the gray level clock signal so as to obtain a gray level implementation clock after frequency multiplication; and the complete refreshing module is used for carrying out T-round complete refreshing on the display unit array according to the target bit number and the multiplied gray scale implementation clock, wherein the value of T is a positive integer and is equal to the target refreshing time, and one frame of image refreshing is realized in each round of complete refreshing.
In one embodiment of the present invention, the display control apparatus further includes: the data generation module is used for calculating and generating a plurality of data bit numbers and a plurality of groups of image refreshing wheel numbers respectively corresponding to the data bit numbers based on a preset bit number range, an input video source frequency, a frequency-multiplied gray scale realization clock frequency and N scanning lines included by the display unit array; and the data selection module is used for selecting one data bit digit from the plurality of data bit digits as the target bit digit according to user input information, and taking the image refresh round number corresponding to the target bit digit as the target refresh frequency.
In one embodiment of the present invention, the data generation module includes: the bit dividing unit is used for dividing the range of the preset bit number to obtain a plurality of data bit numbers; the display period calculating unit is used for calculating an image display period based on the input video source frequency; a clock period calculation unit, configured to calculate a clock frequency based on the multiplied gray scale implementation clock frequency to obtain a clock period of the multiplied gray scale implementation clock; a clock number calculation unit configured to obtain a plurality of clock cycle numbers respectively corresponding to the plurality of data bit numbers based on the plurality of data bit numbers; the time calculation unit is used for calculating and generating corresponding single-round image refreshing time based on each clock cycle number, the clock cycles and the N scanning lines; and the round number calculation unit is used for calculating and generating the corresponding image refreshing round number based on the single-round image refreshing time and the image display period.
In an embodiment of the present invention, the data generating module further includes: the residual time calculation unit is used for calculating residual time corresponding to the number of image refreshing rounds based on the single-round image refreshing time, the number of image refreshing rounds and the image display period; and the extra clock calculation unit is used for calculating and obtaining the number of extra clocks corresponding to the number of image refreshing rounds based on the remaining time, the number of image refreshing rounds, the N scanning lines and the clock period.
In one embodiment of the invention, the full refresh module comprises: a data obtaining unit configured to obtain the number of extra clocks corresponding to the target bit number as a target number of extra clocks; and the line scanning unit is used for performing line scanning on the N scanning lines of the display unit array according to the frequency-multiplied gray scale implementation clock, the target bit number and the target extra clock number so as to implement one round of complete refreshing.
In an embodiment of the present invention, the line scanning unit is specifically configured to: sequentially generating a plurality of display driving signals respectively corresponding to the plurality of display units of each scanning line based on the multiplied gray scale implementation clock, the target bit number and the target extra clock number; driving and controlling the plurality of display units according to the plurality of display driving signals to complete line scanning of corresponding scanning lines; and generating a count zero clearing value corresponding to a clock based on the target bit number and the multiplied gray scale required by the line scanning to which the display driving signal belongs, wherein the sum of the gray scale number represented by the target bit number and the target extra clock number is equal to the count zero clearing value.
In a third aspect, the embodiment of the present invention discloses a display control system, which includes a processor and a memory connected to the processor; wherein the memory stores instructions for execution by the processor, and the instructions cause the processor to perform operations for performing any of the display control methods described above.
In a fourth aspect, an embodiment of the present invention discloses a computer-readable storage medium, which stores computer-readable instructions, where the computer-readable instructions include instructions for executing any one of the display control methods described above.
As can be seen from the above, the embodiments of the present invention can achieve one or more of the following advantages: the method comprises the steps of obtaining a target bit number and a corresponding target refreshing time, then carrying out T-round complete refreshing on a display unit array based on a frequency-doubled gray scale realization clock and the target bit number, wherein the value of T is a positive integer and is equal to the target refreshing time, and each round of complete refreshing realizes one-frame image refreshing, so that the problem of abnormal display caused by incomplete gray scale display when the display screen carries out gray scale display in the prior art is solved, and the display effect of the display screen is improved; and the sum of the gray level represented by the target bit number and the target extra clock number is set to be a counting clear zero value, so that the problem of abnormal display caused by an overlarge black field can be avoided, and the display effect of the display screen is further improved.
Other aspects and features of the present invention will become apparent from the following detailed description, which proceeds with reference to the accompanying drawings. It is to be understood, however, that the drawings are designed solely for purposes of illustration and not as a definition of the limits of the invention. It should be further understood that the drawings are not necessarily drawn to scale and that, unless otherwise indicated, they are merely intended to conceptually illustrate the structures and procedures described herein.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a flowchart illustrating a display control method according to a first embodiment of the present invention;
fig. 2 is a flowchart illustrating other steps included in the display control method shown in fig. 1 before step S11;
FIG. 3 is a flowchart illustrating a step of step S101 of the display control method shown in FIG. 2;
FIG. 4 is a flowchart illustrating another step of step S101 of the display control method shown in FIG. 2;
fig. 5 is a flowchart of the step of step S15 in the display control method shown in fig. 1;
fig. 6 is a system architecture diagram according to a specific implementation of a display control method according to a first embodiment of the present invention;
FIG. 7 is a block diagram of a display control apparatus according to a second embodiment of the present invention;
FIG. 8 is a schematic block diagram of a display control apparatus according to a second embodiment of the present invention;
FIG. 9 is a schematic diagram of a data generation module 201 in the display control apparatus shown in FIG. 8;
fig. 10 is a schematic diagram of another unit of the data generation module 201 in the display control apparatus shown in fig. 8;
FIG. 11 is a schematic diagram of a complete refresh module 25 in the display control apparatus shown in FIG. 8;
fig. 12 is a schematic structural diagram of a display control system according to a third embodiment of the present invention.
Fig. 13 is a schematic structural diagram of a computer-readable storage medium according to a fourth embodiment of the present invention.
[ description of reference ]
S11-S15: S101-S103, S1011-S1018, S151-S152: displaying a control method;
20: a display control device; 21: a data acquisition module; 23: a clock frequency multiplication module; 25: a complete refresh module; 201: a data generation module; 202: a data selection module; 2011: a bit dividing unit; 2012: a display period calculation unit; 2013: a clock cycle calculation unit; 2014: a clock number calculation unit; 2015: a time calculation unit; 2016: a wheel count calculation unit; 2017: a remaining time calculating unit; 2018: an additional clock calculation unit; 251: a data acquisition unit; 252: a line scanning unit;
40: a display control system; 41: a processor; 42: a memory;
50: a computer readable storage medium.
Detailed Description
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict. The invention will be described in connection with embodiments with reference to the drawings.
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not a whole embodiment. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and claims of the present invention and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
It should be noted that the division of the embodiments of the present invention is only for convenience of description and should not be construed as a limitation, and features of various embodiments may be combined and referred to each other without contradiction.
[ first embodiment ] A method for manufacturing a semiconductor device
Referring to fig. 1, a display control method is disclosed in a first embodiment of the present invention. As shown in fig. 1, the display control method includes, for example, steps S11 to S15.
Step S11: acquiring a target bit number and a target refreshing time corresponding to the target bit number;
step S13: carrying out frequency multiplication on the gray level clock signal to obtain a gray level implementation clock after frequency multiplication;
step S15: and performing T-round complete refreshing on the display unit array according to the target bit number and the multiplied gray scale implementation clock, wherein the value of T is a positive integer and is equal to the target refreshing time, and one frame of image refreshing is realized in each round of complete refreshing.
The target bit number mentioned in step S11 is, for example, a bit number corresponding to a gray scale realized by the display cell array, for example, the gray scale realized by the display cell array is 2101024, then the corresponding target number of bits is 10. The mentioned target refresh times may be understood as the number of complete refresh rounds to be performed by the array of display cells.
The gradation clock signal mentioned in step S13 is, for example, a DCLK clock signal inside the display driving chip or an externally input clock signal. The frequency multiplication of the gray scale clock signal in step S13 is the conventional clock frequency multiplication operation, and is not described herein again. The complete gray scale display can be ensured by carrying out frequency multiplication processing on the gray scale clock signals.
The display unit array mentioned in step S15 is, for example, an LED lamp panel, and the mentioned display unit array includes, for example, N scan lines, where it is understood that the display driver chip is connected to the LED lamp panel, the LED lamp panel includes N rows of LED arrays, each row of LED array corresponds to one scan line, and each row of LED array includes, for example, a plurality of LED light points, that is, each display unit is one LED light point. The mentioned implementation of one frame image refresh per complete refresh round may be understood as a single complete refresh round comprising, for example, at least one refresh over which at least one refresh is performed to complete one frame image refresh. For example, if the target number of bits is 10, and the achievable number of bits per scan in a single refresh is also 10, for example, then a full refresh round includes one refresh; if the target number of bits is 12, and the achievable number of bits per scan in a single refresh is 10, for example, then a full refresh cycle includes 4 refreshes, and for convenience of illustration, the target number of bits and the achievable number of bits per scan are default to be the same in the following specific examples, although the invention is not limited thereto.
The target bit number and the corresponding target refreshing times are obtained, then the T-round complete refreshing is carried out on the display unit array based on the multiplied gray scale realization clock and the target bit number, wherein the value of T is a positive integer and is equal to the target refreshing times, and one-frame image refreshing is realized in each round of complete refreshing, so that the problem of abnormal display caused by incomplete gray scale display when the gray scale display is carried out on the display screen in the prior art is solved, and the display effect of the display screen is improved.
In another embodiment of the present invention, as shown in fig. 2, before the step S11, the display control method further includes: step S101 and step S103.
Step S101: calculating and generating a plurality of data bit numbers and a plurality of groups of image refreshing wheel numbers respectively corresponding to the data bit numbers based on a preset bit number range, an input video source frequency, a frequency-multiplied gray scale realization clock frequency and N scanning lines included by the display unit array;
step S103: selecting one data bit digit from the plurality of data bit digits as the target bit digit according to user input information, and taking the image refreshing round number corresponding to the target bit digit as the target refreshing time.
The preset bit number range mentioned in step S101 may be understood as a self-defined bit number value range or a default bit number value range, for example, the preset bit number range is, but not limited to, 10-16. The input video source frequency mentioned is understood to be 60HZ, but not limited thereto. The user input information mentioned in step S103 is, for example, information input by a user through an input device such as a keyboard or information selected directly by mouse clicking.
The target bit number is selected from the plurality of data bit numbers based on the user input information, and the image refreshing round number corresponding to the target bit number is used as the target refreshing time, so that the T-round complete refreshing setting can be realized according to the user selection, and the requirements of the user on different corresponding scenes are met.
In another embodiment of the present invention, as shown in fig. 3, the foregoing step S101 includes, for example: step S1011 to step S1016.
Step S1011: dividing based on the range of the preset bit digits to obtain the plurality of data bit digits;
step S1012: calculating to obtain an image display period based on the input video source frequency;
step S1013: calculating the frequency of the gray scale implementation clock after frequency multiplication to obtain the clock period of the gray scale implementation clock after frequency multiplication;
step S1014: obtaining a plurality of clock cycle numbers respectively corresponding to the plurality of data bit bits based on the plurality of data bit bits;
step S1015: calculating and generating corresponding single-round image refreshing time based on each clock cycle number, the clock cycle and the N scanning lines; and
step S1016: and calculating and generating the corresponding image refreshing turns based on the single-turn image refreshing time and the image display period.
For example, step S1011 can be understood as: the predetermined bit number range is, for example, 10 to 16, then a plurality of data bit numbers can be obtained by dividing: the number of data bits 10, the number of data bits 11, the number of data bits 12, the number of data bits 13, the number of data bits 14, the number of data bits 15, and the number of data bits 16. Step S1012 may be understood as an input video source frequency of, for example, 60HZ, and the image display period of 1/60S is approximately equal to 16.667 ms. Step S1013 may be understood as that the frequency of the multiplied gray scale implementation clock is, for example, 166MHz, and then the clock period is calculated to be 1/166M, which is approximately equal to 6 ns. Step S1014 can be understood as a plurality of data bit numbers such as data bit number 10, data bit number 11, data bit number 12, data bit number 13, data bit number 14, data bit number 15, and data bit number 16, and then the calculated number of the plurality of clock cycles is: the number of clock cycles corresponding to the number of data bits 10 is 2101024, the number of clock cycles corresponding to the data bit number 11 is 2112048, the number of clock cycles for the data bit number 12 is 2124096, the number of clock cycles corresponding to the number of data bits 13 is 2138192, the number of clock cycles for the data bit 14 is 21416384, the number of clock cycles corresponding to the number of data bits 15 is 21532768, the number of clock cycles for the data bit number 16 is 21665536. Step S1015 may be understood as that, taking the number of the clock cycles of 1024 as an example to illustrate that the number of the N scanning lines is 32 scanning lines, the refresh time of the single-round image corresponding to the data bit number 10 is 1024 × 6ns × 32, which is approximately equal to 0.2ms, and the calculation of the refresh time of the single-round image corresponding to the other data bit numbers is similar, and will not be described herein again. Step S1016 can be understood as an example where the refresh time of the single-round image corresponding to the data bit number 10 is 0.2ms, and the data bit number is 10The number of image refresh rounds corresponding to 10 is 16.667/0.2 ═ 83, that is, the number of image refresh rounds corresponding to the data bit number 10 is 83, and the same calculation for the number of image refresh rounds corresponding to the other data bit numbers is not repeated here.
In another embodiment of the present invention, as shown in fig. 4, the step S101 further includes, for example: step S1017 and step S1018.
Step S1017: calculating the remaining time corresponding to the number of image refreshing rounds based on the single-round image refreshing time, the number of image refreshing rounds and the image display period;
step S1018: and calculating the number of extra clocks corresponding to the number of image refreshing rounds based on the remaining time, the number of image refreshing rounds, the N scanning lines and the clock period.
For example, the image refresh round number corresponding to the data bit number 10 is 83 for explanation, and the step S1017 can be understood as: the remaining time corresponding to the data bit number 10 is 16.667- (83 × 0.2), which is approximately 0.067 ms. Step S1018 may be understood as: the number of extra clocks corresponding to the number of data bits 10 is: 0.067/83/32/6ns, roughly 4.
In another embodiment of the present invention, as shown in fig. 5, the foregoing step S15 includes, for example: step S151 and step S152.
Step S151: acquiring the number of the extra clocks corresponding to the target bit number as the number of target extra clocks;
step S152: and performing line scanning on the N scanning lines of the display unit array according to the multiplied gray scale implementation clock, the target bit number and the target extra clock number to implement one round of complete refreshing.
Further, step S152 includes, for example: sequentially generating a plurality of display driving signals respectively corresponding to the plurality of display units of each scanning line based on the multiplied gray scale implementation clock, the target bit number and the target extra clock number; driving and controlling the plurality of display units according to the plurality of display driving signals to complete line scanning of corresponding scanning lines; and generating a count zero clearing value corresponding to a clock based on the target bit number and the multiplied gray scale required by the line scanning to which the display driving signal belongs, wherein the sum of the gray scale number represented by the target bit number and the target extra clock number is equal to the count zero clearing value.
The display driving signal is, for example, a PWM signal. The counting clear value mentioned can be understood as that the counter inside the display driver chip continuously counts the received GCLK clock until a certain fixed value, and the display driver chip performs clear operation on the counter to restart counting, where the certain fixed value at this time corresponds to the counting clear value. For example, the target data bit number is 10, the target extra clock number is 4, and the target data bit number is 10, so that the gray scale represented by the target data bit number 10, i.e. the gray scale, is 210When the number of the gray scale represented by the target bit number and the number of the target extra clocks are set to be the counting clear value, the problem of abnormal display caused by overlarge black fields can be avoided, and the display effect of the display screen is further improved.
For convenience of understanding, a specific implementation of the display control method disclosed in the embodiment of the present invention is illustrated below with reference to fig. 6.
As shown in fig. 6, the display control method implemented by the present embodiment is implemented in an LED driving chip 12, and the LED driving chip 12 is connected between an LED lamp panel 13 and an LED display screen control system 11. The LED driving chip 12 is, for example, a sixteen output channel PWM type LED driving chip for implementing the clock GCLK based on gray scale, and the LED lamp panel 13 is, for example, a monochromatic LED lamp panel, and includes, for example, 32 × 16 LED lamp points, that is, the LED lamp panel 13 includes 32 scanning lines. The LED display screen control system 11 includes, for example, upper computer software, a sending card electrically connected to the upper computer software, and a receiving card electrically connected to the sending card, wherein the receiving card is electrically connected to the LED driving chip 12. Reference to a host computer is made, for example, to a personal computer, hand-held or portable device, tablet device, multiprocessor system, microprocessor-based system, editable consumer electronics, network PC, minicomputer, mainframe computer, distributed computing environment that includes any of the above systems or devices, and the like. The mentioned sending card includes, for example, a video source input interface, a programmable logic device connected to the video source input interface, a microprocessor connected to the programmable logic device, a memory connected to the microprocessor and the programmable logic device, and an ethernet interface connected to the programmable logic device. The mentioned receiving card includes, for example, an ethernet interface, a programmable logic device connected to the ethernet interface, a lamp panel interface connected to the programmable logic device, and the like, and the lamp panel interface is connected to, for example, the LED driving chip 12.
The aforementioned video source input interface is, for example, an HDMI interface or a DVI interface. The mentioned ethernet interface is for example an RJ45 interface, and the mentioned Programmable logic device is for example an FPGA (Field-Programmable Gate Array) or other similar logic device. The microprocessor mentioned is for example an MCU. The memory mentioned is for example a Flash memory. The mentioned lamp panel interface is for example a bus bar connector.
Before the LED driving chip 12 starts scanning, the LED display control system 11 configures an operating mode of the LED driving chip 12, that is, sets a target bit number required for the LED driving chip 12 to operate, a target refresh number corresponding to the target bit number, and the like.
For example, a user selects from upper computer software of the LED display screen control system, for example, selects one of a plurality of data bit numbers as a target bit number, and then obtains a corresponding number of image refresh rounds as a target refresh number based on the selected target bit number. For an example of the upper computer software calculating the plurality of data bit numbers and the plurality of sets of image refresh rounds corresponding to the plurality of data bit numbers, reference may be made to the specific example of step S101, which is not described herein again.
For example, the user selects the data bit number 10 as the target bit number,the upper computer software obtains a target refreshing time 83 corresponding to the target bit number 10 and a target extra clock number 4 and sends the target refreshing time 83 and the target extra clock number 4 to the LED driving chip 12, and after the LED driving chip 12 obtains the target bit number 10, the target refreshing time 83 and the target extra clock number 4, the counting clear value 2 corresponding to the frequency-doubled gray level realization clock is obtained through calculation based on the target bit number 10 and the target extra clock number 410And +4 is 1028, then the LED driving chip 12 generates a plurality of PWM signals corresponding to a plurality of LED light points of the current scanning line based on the multiplied gray scale implementation clock and the count zero value to control the line scanning of the current scanning line, wherein the maximum high level duration of each PWM signal is the multiplied gray scale implementation clock number corresponding to the target bit number 10, that is, 1024 clock cycles, and the total duration of each PWM signal is the time corresponding to the count zero value 1028 multiplied gray scale implementation clocks, and the display gray scale is not driven only in the last 4 clock cycles.
The LED driving chip 12 continues to perform the refresh operation after completing the refresh of one frame of image until the number of complete refresh cycles implemented by the LED driving chip 12 reaches the target refresh number of 83 times, and the configuration register in the LED driving chip controls the LED driving chip to stop the refresh, so that it is ensured that all the gray scales are displayed without loss.
It should be noted that, the operation performed by the aforementioned LED display screen control system may also be autonomously completed by the LED driving chip, which is not limited in this embodiment.
In summary, in the display control method disclosed in the embodiment of the present invention, the target bit number and the corresponding target refresh frequency are obtained, and then the clock and the target bit number are implemented based on the multiplied gray scale to perform a T-round complete refresh on the display unit array, where a value of T is a positive integer and is equal to the target refresh frequency, and each round of complete refresh implements one frame of image refresh, so that the problem of display abnormality caused by incomplete gray scale display when the display screen performs gray scale display in the related art is solved, and the display effect of the display screen is improved; and the sum of the gray level represented by the target bit number and the target extra clock number is set to be a counting clear zero value, so that the problem of abnormal display caused by an overlarge black field can be avoided, and the display effect of the display screen is further improved.
[ second embodiment ]
As shown in fig. 7, a display control apparatus 20 according to a second embodiment of the present invention includes a data obtaining module 21, a clock doubling module 23, and a complete refresh module 25.
The data obtaining module 21 is configured to obtain a target bit number and a target refresh number corresponding to the target bit number. The clock frequency doubling module 23 is configured to perform frequency doubling processing on the grayscale clock signal to obtain a grayscale implementation clock after frequency doubling. And the complete refreshing module 25 is configured to perform T-round complete refreshing on the display single array according to the target bit number and the multiplied gray scale implementation clock, where a value of T is a positive integer and is equal to the target refreshing time, and each round of complete refreshing implements one frame of image refreshing.
In another embodiment of the present invention, as shown in fig. 8, the display control device 20 further includes, for example, a data generation module 201 and a data selection module 202.
The data generating module 201 is configured to calculate and generate a plurality of data bit numbers and a plurality of groups of image refresh rounds corresponding to the data bit numbers respectively based on a preset bit number range, an input video source frequency, a multiplied gray scale implementation clock frequency, and N scan lines included in the display unit array. The data selecting module 202 is configured to select a data bit number from the multiple data bit numbers as the target bit number according to user input information, and use an image refresh round number corresponding to the target bit number as the target refresh number.
In other embodiments of the present invention, as shown in fig. 9, the data generating module 201 includes, for example: a bit dividing unit 2011, a display period calculation unit 2012, a clock period calculation unit 2013, a clock number calculation unit 2014, a time calculation unit 2015, and a round number calculation unit 2016.
The bit dividing unit 2011 is configured to divide the preset bit range to obtain the plurality of data bits. The display period calculating unit 2012 is used for calculating an image display period based on the input video source frequency. The clock period calculating unit 2013 is configured to calculate a clock frequency based on the multiplied gray scale implementation clock to obtain a clock period of the multiplied gray scale implementation clock. The clock number calculation unit 2014 is configured to obtain a plurality of clock cycle numbers respectively corresponding to the plurality of data bit numbers based on the plurality of data bit numbers. The time calculation unit 2015 is configured to calculate and generate a corresponding single-round image refresh time based on each of the number of clock cycles, and the N scan lines. The number-of-rounds calculation unit 2016 is configured to calculate and generate the number of corresponding image refresh rounds based on the single-round image refresh time and the image display period.
Further, as shown in fig. 10, the data generation module 201 further includes, for example: a remaining time calculating unit 2017 and an additional clock calculating unit 2018.
The remaining time calculating unit 2017 is configured to calculate, based on the single-round image refreshing time, the number of image refreshing rounds, and the image display period, a remaining time corresponding to the number of image refreshing rounds. The extra clock calculation unit 2018 is configured to calculate an extra clock number corresponding to the number of image refresh rounds based on the remaining time, the number of image refresh rounds, the N scan lines, and the clock period.
In other embodiments of the present invention, as shown in fig. 11, the complete refresh module 25 includes, for example: a data acquisition unit 251 and a line scanning unit 252.
The data obtaining unit 251 is configured to obtain the extra clock number corresponding to the target bit number as a target extra clock number. The line scanning unit 252 is configured to perform line scanning on the N scanning lines of the display unit array according to the multiplied gray scale implementation clock, the target bit number, and the target extra clock number to implement a round of complete refresh.
Further, the line scanning unit 252 is specifically configured to: sequentially generating a plurality of display driving signals respectively corresponding to the plurality of display units of each scanning line based on the multiplied gray scale implementation clock, the target bit number and the target extra clock number; driving and controlling the plurality of display units according to the plurality of display driving signals to complete line scanning of corresponding scanning lines; and generating a count zero clearing value corresponding to a clock based on the target bit number and the multiplied gray scale required by the line scanning to which the display driving signal belongs, wherein the sum of the gray scale number represented by the target bit number and the target extra clock number is equal to the count zero clearing value.
The display control method implemented by the display control apparatus 20 disclosed in this embodiment is as described in the first embodiment, and therefore, will not be described in detail here. Optionally, each module, unit and the other operations or functions in the second embodiment are respectively for implementing the method in the first embodiment of the present invention, and are not described herein for brevity.
[ third embodiment ]
Referring to fig. 12, a third embodiment of the present invention discloses a display control system. As shown in fig. 12, the display control system 40 includes, for example: a processor 41 and a memory 42 connected to the processor 41. Wherein the memory 42 stores instructions executed by the processor 41, and the instructions cause the processor 41 to perform operations to perform the display control method as described in the first embodiment.
[ fourth example ] A
Referring to fig. 13, a computer-readable storage medium is disclosed in a fourth embodiment of the present invention. As shown in fig. 13, the computer-readable storage medium 50 stores computer-readable instructions including instructions for executing the display control method according to the first embodiment.
In the embodiments provided in the present invention, it should be understood that the disclosed system, apparatus and/or method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and the actual implementation may have another division, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
So far, the principle and the implementation of the display control method, the display control apparatus, the display control system and the computer readable medium of the present invention have been explained by applying specific examples, and the above description of the embodiments is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention, and the scope of the present invention should be subject to the appended claims.
Claims (12)
1. A display control method, comprising:
acquiring a target bit number and a target refreshing time corresponding to the target bit number;
carrying out frequency multiplication on the gray level clock signal to obtain a gray level implementation clock after frequency multiplication;
and performing T-round complete refreshing on the display unit array according to the target bit number and the multiplied gray scale implementation clock, wherein the value of T is a positive integer and is equal to the target refreshing time, and one frame of image refreshing is realized in each round of complete refreshing.
2. The method according to claim 1, further comprising, before the obtaining a target number of bits and a target number of refreshes corresponding to the target number of bits:
calculating and generating a plurality of data bit numbers and a plurality of groups of image refreshing wheel numbers respectively corresponding to the data bit numbers based on a preset bit number range, an input video source frequency, a frequency-multiplied gray scale realization clock frequency and N scanning lines included by the display unit array;
selecting one data bit digit from the plurality of data bit digits as the target bit digit according to user input information, and taking the image refreshing round number corresponding to the target bit digit as the target refreshing time.
3. The method according to claim 2, wherein the generating a plurality of data bit numbers and a plurality of groups of image refresh rounds corresponding to the plurality of data bit numbers respectively based on a preset bit number range, an input video source frequency, a multiplied gray scale implementation clock frequency, and N scan lines included in the display unit array comprises:
dividing based on the range of the preset bit digits to obtain the plurality of data bit digits;
calculating to obtain an image display period based on the input video source frequency;
calculating the frequency of the gray scale implementation clock after frequency multiplication to obtain the clock period of the gray scale implementation clock after frequency multiplication;
obtaining a plurality of clock cycle numbers respectively corresponding to the plurality of data bit bits based on the plurality of data bit bits;
calculating and generating corresponding single-round image refreshing time based on each clock cycle number, the clock cycle and the N scanning lines; and
and calculating and generating the corresponding image refreshing turns based on the single-turn image refreshing time and the image display period.
4. The display control method according to claim 3, further comprising, after the generating of the corresponding number of image refresh rounds based on the single-round image refresh time and the image display period calculation:
calculating the remaining time corresponding to the number of image refreshing rounds based on the single-round image refreshing time, the number of image refreshing rounds and the image display period;
and calculating the number of extra clocks corresponding to the number of image refreshing rounds based on the remaining time, the number of image refreshing rounds, the N scanning lines and the clock period.
5. The method according to claim 4, wherein the performing T-round complete refresh on the display cell array according to the target bit number and the multiplied gray scale implementation clock comprises:
acquiring the number of the extra clocks corresponding to the target bit number as the number of target extra clocks;
and performing line scanning on the N scanning lines of the display unit array according to the multiplied gray scale implementation clock, the target bit number and the target extra clock number to implement one round of complete refreshing.
6. The method according to claim 5, wherein the row scanning the N scanning rows of the display cell array according to the multiplied gray scale implementation clock, the target bit number and the target extra clock number to implement a round of complete refresh comprises:
sequentially generating a plurality of display driving signals respectively corresponding to the plurality of display units of each scanning line based on the multiplied gray scale implementation clock, the target bit number and the target extra clock number; and
driving and controlling the plurality of display units according to the plurality of display driving signals to complete line scanning of corresponding scanning lines;
and generating a count zero clearing value corresponding to a clock based on the target bit number and the multiplied gray scale required by the line scanning to which the display driving signal belongs, wherein the sum of the gray scale number represented by the target bit number and the target extra clock number is equal to the count zero clearing value.
7. A display control apparatus, characterized by comprising:
the data acquisition module is used for acquiring a target bit number and target refreshing times corresponding to the target bit number;
the clock frequency multiplication module is used for carrying out frequency multiplication processing on the gray level clock signal so as to obtain a gray level implementation clock after frequency multiplication;
and the complete refreshing module is used for carrying out T-round complete refreshing on the display single array according to the target bit number and the multiplied gray scale implementation clock, wherein the value of T is a positive integer and is equal to the target refreshing time, and one frame of image refreshing is realized in each round of complete refreshing.
8. The display control apparatus according to claim 7, further comprising:
the data generation module is used for calculating and generating a plurality of data bit numbers and a plurality of groups of image refreshing wheel numbers respectively corresponding to the data bit numbers based on a preset bit number range, an input video source frequency, a frequency-multiplied gray scale realization clock frequency and N scanning lines included by the display unit array;
and the data selection module is used for selecting one data bit digit from the plurality of data bit digits as the target bit digit according to user input information, and taking the image refresh round number corresponding to the target bit digit as the target refresh frequency.
9. The display control apparatus according to claim 8, wherein the data generation module comprises:
the bit dividing unit is used for dividing the range of the preset bit number to obtain a plurality of data bit numbers;
the display period calculating unit is used for calculating an image display period based on the input video source frequency;
a clock period calculation unit, configured to calculate a clock frequency based on the multiplied gray scale implementation clock frequency to obtain a clock period of the multiplied gray scale implementation clock;
a clock number calculation unit configured to obtain a plurality of clock cycle numbers respectively corresponding to the plurality of data bit numbers based on the plurality of data bit numbers;
the time calculation unit is used for calculating and generating corresponding single-round image refreshing time based on each clock cycle number, the clock cycles and the N scanning lines; and
and the round number calculation unit is used for calculating and generating the corresponding image refreshing round number based on the single-round image refreshing time and the image display period.
10. The display control apparatus according to claim 9, wherein the data generation module further comprises:
the residual time calculation unit is used for calculating residual time corresponding to the number of image refreshing rounds based on the single-round image refreshing time, the number of image refreshing rounds and the image display period;
and the extra clock calculation unit is used for calculating and obtaining the number of extra clocks corresponding to the number of image refreshing rounds based on the remaining time, the number of image refreshing rounds, the N scanning lines and the clock period.
11. The display control device of claim 10, wherein the full refresh module comprises:
a data obtaining unit configured to obtain the number of extra clocks corresponding to the target bit number as a target number of extra clocks;
and the line scanning unit is used for performing line scanning on the N scanning lines of the display unit array according to the frequency-multiplied gray scale implementation clock, the target bit number and the target extra clock number so as to implement one round of complete refreshing.
12. The display control device according to claim 11, wherein the line scanning unit is specifically configured to: sequentially generating a plurality of display driving signals respectively corresponding to the plurality of display units of each scanning line based on the multiplied gray scale implementation clock, the target bit number and the target extra clock number; driving and controlling the plurality of display units according to the plurality of display driving signals to complete line scanning of corresponding scanning lines;
and generating a count zero clearing value corresponding to a clock based on the target bit number and the multiplied gray scale required by the line scanning to which the display driving signal belongs, wherein the sum of the gray scale number represented by the target bit number and the target extra clock number is equal to the count zero clearing value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010801777.3A CN114078419B (en) | 2020-08-11 | 2020-08-11 | Display control method and display control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010801777.3A CN114078419B (en) | 2020-08-11 | 2020-08-11 | Display control method and display control device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114078419A true CN114078419A (en) | 2022-02-22 |
| CN114078419B CN114078419B (en) | 2023-01-10 |
Family
ID=80279907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010801777.3A Active CN114078419B (en) | 2020-08-11 | 2020-08-11 | Display control method and display control device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114078419B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117059021A (en) * | 2023-10-11 | 2023-11-14 | 南京酷开智慧屏科技有限公司 | Lattice screen based on SOC and driving method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103390387A (en) * | 2013-07-23 | 2013-11-13 | 深圳市明微电子股份有限公司 | Frequency doubling display control method and system |
| CN105185316A (en) * | 2015-10-19 | 2015-12-23 | 西安诺瓦电子科技有限公司 | LED display drive control method and device, and LED lamp panel |
| CN108235121A (en) * | 2018-01-16 | 2018-06-29 | 青岛海信电器股份有限公司 | A kind of processing method and processing device that frequency multiplication is shown, electronic equipment |
| CN109147653A (en) * | 2018-10-09 | 2019-01-04 | 中国电子科技集团公司第五十八研究所 | A kind of LED drive chip display control OS-PWM method |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Multirow sweeps the all-colour LED driving chip and driving method of high refresh rate |
| CN111489685A (en) * | 2020-01-22 | 2020-08-04 | 南京浣轩半导体有限公司 | Multi-line scanning L ED gray scale switching display method and system |
-
2020
- 2020-08-11 CN CN202010801777.3A patent/CN114078419B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103390387A (en) * | 2013-07-23 | 2013-11-13 | 深圳市明微电子股份有限公司 | Frequency doubling display control method and system |
| CN105185316A (en) * | 2015-10-19 | 2015-12-23 | 西安诺瓦电子科技有限公司 | LED display drive control method and device, and LED lamp panel |
| CN108235121A (en) * | 2018-01-16 | 2018-06-29 | 青岛海信电器股份有限公司 | A kind of processing method and processing device that frequency multiplication is shown, electronic equipment |
| CN109147653A (en) * | 2018-10-09 | 2019-01-04 | 中国电子科技集团公司第五十八研究所 | A kind of LED drive chip display control OS-PWM method |
| CN110277052A (en) * | 2019-06-13 | 2019-09-24 | 华中科技大学 | Multirow sweeps the all-colour LED driving chip and driving method of high refresh rate |
| CN111489685A (en) * | 2020-01-22 | 2020-08-04 | 南京浣轩半导体有限公司 | Multi-line scanning L ED gray scale switching display method and system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117059021A (en) * | 2023-10-11 | 2023-11-14 | 南京酷开智慧屏科技有限公司 | Lattice screen based on SOC and driving method thereof |
| CN117059021B (en) * | 2023-10-11 | 2024-01-26 | 南京酷开智慧屏科技有限公司 | Lattice screen based on SOC and driving method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114078419B (en) | 2023-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104750339A (en) | Display device with integrated touch screen and driving method thereof | |
| CN101093658A (en) | Conversion of display refreshing speed | |
| CN106771974B (en) | Display module lighting test device and method | |
| CN101645244A (en) | Liquid crystal display device and driving method thereof | |
| CN104731399A (en) | Display device with integrated touch screen and driving method thereof | |
| JP2003536111A (en) | Method and system for providing intensity modulation | |
| CN103530078A (en) | System and method for displaying a mirror | |
| CN103310747A (en) | Liquid crystal display device, driving method of liquid crystal display device and electronic apparatus | |
| KR20110133760A (en) | Method and apparatus for generating dither patterns to display stereoscopic images | |
| CN107659800A (en) | A kind of DMD high frame frequency and high resolutions synchronous dynamic display system | |
| CN107545864A (en) | LED display and its drive circuit and driving method | |
| CN114078419B (en) | Display control method and display control device | |
| CN107624194A (en) | For the apparatus and method for the timing controller for operating display | |
| CN102486911A (en) | Organic light emitting diode display and method for driving same | |
| WO2023246828A1 (en) | Led display screen driving method, system and apparatus, and device and medium | |
| CN108922470A (en) | Picture element scan method, apparatus, display equipment and storage medium | |
| CN112785968B (en) | Control device, display device and operation method thereof | |
| WO2010005695A1 (en) | Programmable cycle state machine interface | |
| JPH10187138A (en) | Method for efficiently constructing display image and display processor system | |
| CN108958558A (en) | Semiconductor device, display device and its operating method | |
| CN103383710A (en) | Circuit board based on SOPC analog brain waves and method for constructing brain dynamic model | |
| CN110751924A (en) | Micro-LED display screen controlled in split screen mode | |
| CN114637711A (en) | Chip control method, control data transmission method and device and computer equipment | |
| Bushma | Software controlling the LED bar graph displays | |
| CN102194421B (en) | Method and equipment for controlling display |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |