CN114076938B - High-integration ultrasonic transmitting and receiving-transmitting switching chip - Google Patents
High-integration ultrasonic transmitting and receiving-transmitting switching chip Download PDFInfo
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- CN114076938B CN114076938B CN202210058793.7A CN202210058793A CN114076938B CN 114076938 B CN114076938 B CN 114076938B CN 202210058793 A CN202210058793 A CN 202210058793A CN 114076938 B CN114076938 B CN 114076938B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
- G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
- G01S7/52019—Details of transmitters
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
- G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
- G01S7/52023—Details of receivers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a high-integration ultrasonic transmitting and receiving-transmitting switching chip, which comprises: the sub-array chips are used for driving corresponding i transducer sub-arrays, and the transducer sub-arrays comprise j transducer elements; the subarray chip comprises a high-voltage transmitting circuit, a high-voltage switch array, transmitting waveform control logic and multi-path selection logic; the high-voltage transmitting circuit outputs a high-voltage waveform signal to the high-voltage switch array, and the multi-path selection logic controls the transmitting channel of the high-voltage switch array to be connected and the receiving channel to be disconnected, so that the high-voltage waveform signal is transmitted to the transducer array element, and the transmission of an ultrasonic signal is realized; the multi-channel selection logic controls the connection of a receiving channel and the disconnection of a transmitting channel of the high-voltage switch array, so that the ultrasonic signals received by the transducer array elements are transmitted to a signal receiving module arranged outside the chip, and the reception of the ultrasonic signals is realized. The invention realizes better isolation performance under the condition of high integration level and reduces the power consumption of high-voltage signal transmission.
Description
Technical Field
The invention relates to the technical field of ultrasonic transmitting and receiving-transmitting switching chips, in particular to a high-integration ultrasonic transmitting and receiving-transmitting switching chip.
Background
Medical ultrasound imaging is an important tool in modern human health examinations. Ultrasound imaging works by transmitting ultrasound waves into the body and then receiving and processing the echoes to produce images of objects in the detection range, such as static and motion maps of blood, organ tissue, and also to provide blood flow velocity information.
The hardware architecture of the ultrasonic imaging system consists of an ultrasonic probe, a digital signal processing circuit, a display processing circuit and peripheral equipment. An ultrasound probe typically includes a piezoelectric transducer array, a high voltage switch, high voltage transmit circuitry, transmit/receive switches, a receive analog front end, a beamformer. The piezoelectric transducer array typically comprises 64 or 128 or more array elements. To drive these array elements, the existing solution is to use multiple discrete chip high voltage switches and transmit/receive switches to implement the function of a multiplexer, and then connect to the high voltage transmit circuit channel and receive analog front end channel, where the number of transmit/receive circuit channels is less than the number of array elements.
Existing solutions require a large number of discrete chips and peripheral circuits to be integrated on a Printed Circuit Board (PCB) inside a probe, including a high voltage switch chip, a transmit/receive switch chip, a high voltage transmit circuit chip, and a receive analog front end chip. The integration of a large number of discrete components on the PCB leads to larger equipment volume and low integration level; a large number of discrete components can cause problems of material purchase, inventory management, welding yield and the like, and the cost is increased; high-voltage signals need to be transmitted among the array elements, the high-voltage switch chip, the transmitting/receiving switch chip and the high-voltage transmitting circuit chip, and extra power consumption can be consumed when the high-voltage signals are transmitted on a PCB with high parasitic capacitance and resistance. This solution is not conducive to the requirements of high-integration, low-cost, low-power ultrasound imaging applications, especially for use in hand-held ultrasound imaging devices.
Accordingly, the prior art is yet to be improved and developed.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a high-integration ultrasonic transmitting and receiving switching chip, which effectively improves the integration level, reduces the cost, and reduces the power consumption of high-voltage signal transmission.
The technical scheme adopted by the invention for solving the technical problem is as follows:
a high integration ultrasonic transmitting and transceiving switching chip, comprising:
the system comprises i sub-array chips, i sub-array chips and a controller, wherein the i sub-array chips are used for driving corresponding i transducer sub-columns, and each transducer sub-column comprises j transducer elements;
each subarray chip comprises a high-voltage transmitting circuit, a high-voltage switch array, transmitting waveform control logic and multi-path selection logic;
the high-voltage transmitting circuit outputs a high-voltage waveform signal to the high-voltage switch array, and the multi-path selection logic controls the transmitting channel of the high-voltage switch array to be communicated and the receiving channel to be disconnected, so that the high-voltage waveform signal is transmitted to the transducer array element, the transmission of an ultrasonic signal is realized, and the high-voltage waveform signal is isolated from a signal receiving module arranged outside the chip;
the multi-path selection logic controls the connection and disconnection of a receiving channel and a transmitting channel of the high-voltage switch array, so that ultrasonic signals received by the transducer array elements are transmitted to a signal receiving module arranged outside a chip to achieve the reception of the ultrasonic signals, and the transmitting waveform control logic controls the output signals of the high-voltage transmitting circuit to be 0 or direct current signals.
Preferably, the high voltage transmitting circuit includes:
the high-voltage current steering digital-to-analog converter, the high-voltage current mirror, the resistor Rt and the high-voltage output driving circuit;
the transmitting waveform control logic controls the high-voltage current steering digital-to-analog converter to generate programmable current, the programmable current generates proportional mirror image current through the high-voltage current mirror, the proportional mirror image current generates high-voltage signals with any waveform after flowing through the resistor Rt, and the high-voltage waveform signals generate waveform signals with high-current driving capability through the high-voltage output driving circuit.
Preferably, the high-voltage current steering digital-to-analog converter comprises an N-type high-voltage current steering digital-to-analog converter and a P-type high-voltage current steering digital-to-analog converter, and the high-voltage current mirror comprises a P-type high-voltage current mirror and an N-type high-voltage current mirror;
the N-type high-voltage current steering digital-to-analog converter is connected with the P-type high-voltage current mirror, and the P-type high-voltage current steering digital-to-analog converter is connected with the N-type high-voltage current mirror.
Preferably, the N-type high-voltage current steering digital-to-analog converter includes an N-type unit current mirror and an N-type high-voltage isolation switch, the N-type unit current mirror is implemented by using a low-voltage NMOS transistor with a fixed gate voltage bias, and the N-type high-voltage isolation switch is implemented by using an N-type high-voltage transistor to implement a gate voltage controlled switch.
Preferably, the P-type high-voltage current steering digital-to-analog converter comprises a P-type unit current mirror and a P-type high-voltage isolating switch, the P-type unit current mirror is implemented by using a low-voltage PMOS transistor with a fixed gate voltage bias, and the P-type high-voltage isolating switch is implemented by using a P-type high-voltage transistor to implement gate voltage controlled switching.
Preferably, after the programmable currents IR _ P, IR _ N generated by the N-type high voltage current steering dac and the P-type high voltage current steering dac are respectively input to the P-type high voltage current mirror and the N-type high voltage current mirror, the generated proportional mirror currents are respectively marked as IO _ P, IO _ N, and the proportional mirror currents IO _ P and IO _ N cannot be simultaneously different from 0, that is, when IR _ P ≠ 0, IR _ N =0, or when IR _ N ≠ 0, IR _ P = 0.
Preferably, the emission waveform control logic is further connected with a voltage comparison circuit, and is used for calibrating programmable current IR _ P, IR _ N generated by the N-type high-voltage current steering digital-to-analog converter and the P-type high-voltage current steering digital-to-analog converter;
the voltage comparison circuit compares the voltage Vr generated by the proportional mirror current IO _ P, IO _ N flowing through the resistor Rt with the reference voltage Vref.
Preferably, the high-voltage output driving circuit adopts a high-voltage tube and large-area source follower structure.
Preferably, the high voltage switches in the high voltage switch array comprise:
two back-to-back N-type LDMOS switches MNH1 and MNH2, sources of the switches MNH1 and MNH2 are connected to a common node vcm, drains of the MNH1 and MNH2 are respectively connected to io1 and io2, and the common node vcm is connected with a diode D1 and then is connected with a grounding switch MNH3 in series to be connected to a system low potential AVSS.
Preferably, the high voltage switches in the high voltage switch array comprise:
the source electrodes of two back-to-back P-type LDMOS switches MPH1 and MPH2, MPH1 and MPH2 are connected to a common node vcm, the drain electrodes of MPH1 and MPH2 are respectively connected to io1 and io2, the common node vcm is connected with a diode D1, and then the series grounding switch MPH3 is connected to a system high potential AVDD.
Compared with the prior art, the high-integration ultrasonic transmitting and receiving switching chip provided by the invention has the following beneficial effects:
the chip of the application comprises a plurality of sub-array chips, the sub-array chips are integrated in a packaging body, and an independent chip is arranged outside the packaging body, so that the number of discrete components on a PCB can be reduced, and the integration level and the cost are improved. Meanwhile, the capacitance of the interconnected parasitic resistor is far smaller than that of the PCB, so that the power consumption consumed by high-voltage signal transmission can be effectively reduced, and low power consumption is realized.
The high-voltage transmitting circuit can be divided into a waveform generating part and a high-voltage output large-current driving tube, the high-voltage large-current driving tube and the high-voltage switch array account for 80% of the total chip area, the two large-area large-current parts are produced by adopting low-cost process nodes, and the other parts are produced by adopting high-performance process nodes, so that the production cost of the chip is reduced on the premise of realizing high integration and high performance.
In addition, the high voltage switch of the present application is connected to a fixed potential via a ground switch at a common node between the back-to-back connected LDMOS; the main switch conduction function is realized by conducting the back-to-back LDMOS and disconnecting the grounding switch; the main switch disconnection function is realized by disconnecting the back-to-back LDMOS and connecting the grounding switch, and the common node can be clamped when the back-to-back LDMOS is disconnected, so that better isolation performance is realized.
Drawings
In order to illustrate the solution of the present application more clearly, the drawings that are needed in the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and that other drawings can be obtained by those skilled in the art without inventive effort.
Fig. 1 is a simplified schematic diagram of an architecture of a high-integration ultrasonic transmitting and transceiving switching chip according to the present invention.
Fig. 2 is a schematic diagram of a high-voltage transmitting circuit in a high-integration ultrasonic transmitting and transceiving switching chip of the present invention.
Fig. 3 is a schematic diagram of a high-voltage switch array in a high-integration ultrasonic transmitting and transceiving switching chip of the present invention.
Fig. 4 is a schematic diagram of an embodiment of a high-voltage switch in a high-integration ultrasonic transmitting and receiving/transmitting switching chip according to the present invention.
FIG. 5 is a schematic diagram of a second embodiment of a high-voltage switch in a high-integration ultrasonic transmitting and transceiving switching chip according to the present invention.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "including" and "having," and any variations thereof, in the description and claims of this application and the description of the above figures are intended to cover non-exclusive inclusions. The terms "first," "second," and the like in the description and claims of this application or in the above-described drawings are used for distinguishing between different objects and not for describing a particular order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by one skilled in the art that the embodiments described herein can be combined with other embodiments.
The embodiment of the invention provides an ultrasonic transmitting and receiving-transmitting switching chip with high integration degree, as shown in figure 1, comprising: i sub-array chips 1000, i of the sub-array chips 1000 being configured to drive i corresponding transducer sub-arrays 40, each of the transducer sub-arrays 40 including j transducer elements 401;
each sub-array chip 1000 comprises a high voltage transmitting circuit 1011, a high voltage switch array 1021, transmit waveform control logic 1012, and multiplexing logic 1022;
the high-voltage transmitting circuit 1011 outputs a high-voltage waveform signal to the high-voltage switch array 1021, and the multi-path selection logic 1022 controls the transmitting channel of the high-voltage switch array 1021 to be connected and the receiving channel to be disconnected, so that the high-voltage waveform signal is transmitted to the transducer array 401, the transmission of an ultrasonic signal is realized, and the high-voltage waveform signal is isolated from the signal receiving module 20 arranged outside the chip; the high voltage transmitting circuit 1011 can generate an arbitrary waveform and the voltage value can be calibrated.
The multi-channel selection logic 1022 controls the receiving channel of the high-voltage switch array 1021 to be connected and the transmitting channel to be disconnected, so that the ultrasonic signal received by the transducer array element 401 is transmitted to the signal receiving module 20 arranged outside the chip, the ultrasonic signal is received, and the transmitting waveform control logic 1012 controls the output signal of the high-voltage transmitting circuit to be 0 or a direct current signal.
The chip 10 is capable of driving i x j transducer elements in the transducer sub-array 40, and the number of spatially arranged rows of the elements is not limited by i or j. More specifically, j suggests an implementation value of 4. Since a value of 4 can cover the usual value of 1/2/4 and the area is half the value of 8, the trade-off between applicability and area cost is better.
In fig. 2, the sub-array chip 1000 includes a high voltage transmit circuit 1011 and transmit waveform control logic 1012, a high voltage switch array 1021, and multiplexing logic 1022. Each module of the sub-array chip 1000 can be integrated in a single die or a package, and the parasitic resistance capacitance of the interconnection is much smaller than that of a PCB board level parasitic resistance capacitance, so that the power consumption consumed by high-voltage signal transmission can be reduced, and low power consumption is realized.
Furthermore, a low-cost manufacturing and packaging method of the ultrasonic transmitting sub-chip is provided. The high-voltage output driving stage 1011_5 and the high-voltage switch array 1021 are produced in a low-cost process node, such as a high-voltage BCD process with a process node of 0.35um or more, so that the cost is reduced; other modules are produced in a high-performance process node, such as a 0.18 um-high-pressure SOI process, so that the performance is ensured; then 2 dies are packaged into one package. Because the high-voltage output driving stage 1011_5 and the high-voltage switch array 1021 account for 80% of the total chip area, and the production cost of the high-performance process node is more than 3 times of that of the low-cost process node, the production cost of the chip is reduced to less than half of the original cost on the premise of not greatly differing the packaging cost and ensuring the performance, and the cost can be greatly reduced.
In specific implementation, as shown in fig. 2, the high voltage transmitting circuit 1011 includes:
the high-voltage current steering digital-to-analog converter, the high-voltage current mirror, the resistor Rt and the high-voltage output driving circuit;
the transmitting waveform control logic controls the high-voltage current steering digital-to-analog converter to generate programmable current, the programmable current generates proportional mirror image current through the high-voltage current mirror, the proportional mirror image current generates high-voltage signals with any waveform after flowing through the resistor Rt, and the waveform signals generate waveform signals with high-current driving capability through the high-voltage output driving circuit.
In specific implementation, the high-voltage current steering digital-to-analog converter comprises an N-type high-voltage current steering digital-to-analog converter 1011_1 and a P-type high-voltage current steering digital-to-analog converter 1011_2, and the high-voltage current mirror comprises a P-type high-voltage current mirror 1011_3 and an N-type high-voltage current mirror 1011_ 4;
the N-type high-voltage current steering digital-to-analog converter 1011_1 is connected with the P-type high-voltage current mirror 1011_3, and the P-type high-voltage current steering digital-to-analog converter 1011_2 is connected with the N-type high-voltage current mirror 1011_ 4.
In specific implementation, the N-type high-voltage current steering digital-to-analog converter 1011_1 includes an N-type unit current mirror and an N-type high-voltage isolating switch, the N-type unit current mirror is implemented by using a low-voltage NMOS transistor with a fixed gate voltage bias, and the N-type high-voltage isolating switch is implemented by using an N-type high-voltage transistor to implement a gate voltage controlled switch.
In specific implementation, the P-type high-voltage current steering dac 1011_2 includes a P-type unit current mirror and a P-type high-voltage isolation switch, the P-type unit current mirror is implemented by using a low-voltage PMOS transistor with a fixed gate voltage bias, and the P-type high-voltage isolation switch is implemented by using a P-type high-voltage transistor to implement a gate voltage controlled switch.
The N-type high-voltage current steering digital-to-analog converter 1011_1 realizes the programmable and high-voltage isolation function of the positive high-voltage to ground output current. More specifically, the value of the total output current IR _ P, which includes the unit current sources generated by the k unit currents Iu, can be set between 0 and k Iu by the 1012 module. Each unit current source consists of a unit current mirror and a high-voltage isolating switch, the unit current mirror MN is realized by a low-voltage NMOS tube with fixed gate voltage bias, and the high-voltage isolating switch realizes gate voltage controlled switching by an N-type high-voltage tube.
The P-type high-voltage current steering digital-to-analog converter 1011_2 realizes the programmable and high-voltage isolation function of the ground-to-negative high-voltage output current. More specifically, as described with reference to the module 1011_1 above, the structure is the same as the module 1011_1, but the polarity is reversed. More specifically, the unit current source Iu between the modules 1011_1 and 1011_2 needs to be calibrated by using a current mirror reference circuit (not shown), so as to ensure that the output positive and negative voltage waveforms are consistent.
In specific implementation, after the programmable currents IR _ P, IR _ N generated by the N-type high voltage current steering dac 1011_1 and the P-type high voltage current steering dac 1011_2 are respectively input to the P-type high voltage current mirror 1011_3 and the N-type high voltage current mirror 1011_4, the generated proportional mirror currents are respectively denoted as IO _ P, IO _ N, and the proportional mirror currents IO _ P and IO _ N cannot be simultaneously different from 0, that is, when IR _ P ≠ 0, IR _ N =0, or when IR _ N ≠ 0, IR _ P = 0. This enables programmable positive high-voltage to ground output current IO _ P and ground to negative high-voltage output current IO _ N. The currents IO _ P and IO _ N are at the same node, and respectively realize two functions of positive voltage and negative voltage, so that the currents IO _ P and IO _ N work in a time-sharing mode and cannot be generated at the same time.
In specific implementation, the transmit waveform control logic 1012 is further connected to a voltage comparison circuit 1011_6, which is used to calibrate the programmable current IR _ P, IR _ N generated by the N-type high-voltage current steering digital-to-analog converter 1011_1 and the P-type high-voltage current steering digital-to-analog converter 1011_ 2; the voltage comparison circuit compares the voltage Vr generated by the proportional mirror current IO _ P, IO _ N flowing through the resistor Rt with the reference voltage Vref.
The proportional mirror currents IO _ P and IO _ N flow through the resistor Rt to generate the arbitrary waveform generation signal Vr. Because of the absolute accuracy error of the semiconductor process, the actual value of the on-chip resistor Rt may deviate and cause the voltage Vr to be inaccurate. Therefore, a voltage comparison circuit 1011_6 is introduced to compare the voltage Vr with the reference voltage Vref, the compared output is sent to the transmit waveform control logic 1012, and the module 1012 generates a calibration value and superimposes the calibration value on the corresponding value to control the modules 1011_1 and 1011_2 to generate the calibrated currents IO _ P and IO _ N, so that the accurate voltage value Vr can be realized.
In specific implementation, the high-voltage output driving circuit 1011_5 adopts a high-voltage tube and large-area source follower structure to have transient large-current driving capability, so that any high-voltage waveform generation signal TX of the large-current driving capability is realized.
Referring to fig. 3, a schematic diagram of an embodiment of a high voltage switch array 1021 is shown, and its control logic is described below.
In the ultrasonic transmitting stage, the high-voltage transmitting circuit 1011 outputs 1-channel high-voltage waveform to the high-voltage switch array 1021, the multi-path selection logic 1022 controls the high-voltage switch array 1021 to realize the multi-path selection function from 1 to j, and the gated high-voltage switch SW _ Tj transmits the high-voltage waveform to the transducer array element (PZ) to realize the signal transmitting function. Meanwhile, the series of the receiving switches SW _ R is disconnected, so that the effect of isolating the high-voltage signal from the receiving end RX is realized; when the receiving switches SW _ R series are all disconnected, the grounding switch SW _ RG is connected to the ground so as to achieve better effect of isolating the high-voltage signal from the receiving end.
In the ultrasonic receiving stage, the high-voltage switch array 1021 and the multiplexing logic 1022 realize the multiplexing function from j to 1, and the gating receiving switch SW _ Rj transmits the waveform received by the transducer array (PZj) to the off-chip receiving path 20, so as to realize the signal receiving function. At the moment, the transmitting waveform control logic controls the output TX to be 0 or other direct current values, the multi-path selection logic controls all transmitting switches SW _ T to be switched off, all receiving path switches which are not gated to be switched off, and the grounding switch SW _ TG of the transducer array elements which are not gated to be connected to the ground, so that the function of reducing the interference of the receiving signals of the adjacent transducer array elements is realized.
A switch composed of a conventional high-voltage Laterally Diffused Metal Oxide Semiconductor (LDMOS) tube and an equivalent schematic diagram. Because a body diode is parasitic inside the LDMOS, two LDMOS need to be connected back to ensure that io1 and io2 are not conducted through the body diode under different polarities when the LDMOS is turned off. However, the switch is equivalent to a large resistor connected in parallel with a capacitor, and the isolation performance under the high-voltage waveform is not good enough.
To solve the problem, the invention further provides a T-type high-voltage switch with high isolation performance, which is shown in fig. 4 and 5. The proposed high voltage switching principle is that the common node between the back-to-back connected LDMOS is connected to a fixed potential via a ground switch; the main switch is turned on by turning on the back-to-back LDMOS and turning off the grounding switch; the main switch disconnection function is realized by disconnecting the back-to-back LDMOS and connecting the grounding switch, so that the common node is clamped when the back-to-back LDMOS is disconnected, and better isolation performance is realized.
As shown in fig. 4, the high voltage switches in the high voltage switch array include:
two back-to-back N-type LDMOS switches MNH1 and MNH2, sources of the switches MNH1 and MNH2 are connected to a common node vcm, drains of the MNH1 and MNH2 are respectively connected to io1 and io2, and the common node vcm is connected with a diode D1 and then is connected with a grounding switch MNH3 in series to be connected to a system low potential AVSS.
As shown in fig. 5, the high voltage switches in the high voltage switch array include:
the source electrodes of the two back-to-back P-type LDMOS switches MPH1 and MPH2, MPH1 and MPH2 are connected to a common node vcm, the drain electrodes of MPH1 and MPH2 are respectively connected to io1 and io2, and the common node vcm is connected with a diode D1 and then connected in series with a grounding switch MPH3 to be connected to a system high potential AVDD.
In summary, the present invention discloses a high-integration ultrasonic transmitting and receiving switching chip, which includes: the system comprises i sub-array chips, i sub-array chips and a controller, wherein the i sub-array chips are used for driving corresponding i transducer sub-columns, and each transducer sub-column comprises j transducer elements; each subarray chip comprises a high-voltage transmitting circuit, a high-voltage switch array, transmitting waveform control logic and multi-path selection logic; the high-voltage transmitting circuit outputs a high-voltage waveform signal to the high-voltage switch array, and the multi-path selection logic controls the transmitting channel of the high-voltage switch array to be communicated and the receiving channel to be disconnected, so that the high-voltage waveform signal is transmitted to the transducer array element, the transmission of an ultrasonic signal is realized, and the high-voltage waveform signal is isolated from a signal receiving module arranged outside the chip; the receiving channel of the high-voltage switch array is controlled to be communicated and the transmitting channel of the high-voltage switch array is controlled to be disconnected by the multi-channel selection logic, so that ultrasonic signals received by the transducer array elements are transmitted to the signal receiving module arranged outside the chip, the ultrasonic signals are received, and the transmitting waveform control logic controls the output signals of the high-voltage transmitting circuit to be 0 or direct current signals, so that the integration level is effectively improved, the cost is reduced, and the power consumption consumed by high-voltage signal transmission is reduced.
It should be understood that the above-described embodiments are merely exemplary of some, and not all, embodiments of the present application, and that the drawings illustrate preferred embodiments of the present application without limiting the scope of the claims appended hereto. This application is capable of embodiments in many different forms and is provided for the purpose of enabling a thorough understanding of the disclosure of the application. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to one skilled in the art that the present application may be practiced without modification or with equivalents of some of the features described in the foregoing embodiments. All equivalent structures made by using the contents of the specification and the drawings of the present application are directly or indirectly applied to other related technical fields and are within the protection scope of the present application.
Claims (7)
1. A high-integration ultrasonic transmitting and receiving-transmitting switching chip is characterized by comprising:
the system comprises i sub-array chips, i sub-array chips and a controller, wherein the i sub-array chips are used for driving corresponding i transducer sub-columns, and each transducer sub-column comprises j transducer elements;
each subarray chip comprises a high-voltage transmitting circuit, a high-voltage switch array, transmitting waveform control logic and multi-path selection logic;
the high-voltage transmitting circuit outputs a high-voltage waveform signal to the high-voltage switch array, and the multi-path selection logic controls the transmitting channel of the high-voltage switch array to be communicated and the receiving channel to be disconnected, so that the high-voltage waveform signal is transmitted to the transducer array element, the transmission of an ultrasonic signal is realized, and the high-voltage waveform signal is isolated from a signal receiving module arranged outside the chip;
the multi-path selection logic controls the connection of a receiving channel and the disconnection of a transmitting channel of the high-voltage switch array, so that ultrasonic signals received by the transducer array element are transmitted to a signal receiving module arranged outside a chip to realize the reception of the ultrasonic signals, and the transmitting waveform control logic controls the output signals of the high-voltage transmitting circuit to be 0 or direct current signals;
the high-voltage switch in the high-voltage switch array comprises:
two back-to-back N-type LDMOS switches MNH1 and MNH2, sources of the switches MNH1 and MNH2 are connected to a common node vcm, drains of the MNH1 and MNH2 are respectively connected to io1 and io2, the common node vcm is connected with a diode D1, and then the serially connected grounding switch MNH3 is connected to a system low potential AVSS;
or two back-to-back P-type LDMOS switches MPH1 and MPH2, the sources of the switches MPH1 and MPH2 are connected to a common node vcm, the drains of MPH1 and MPH2 are respectively connected to io1 and io2, the common node vcm is connected with a diode D1, and then the series grounding switch MPH3 is connected to a system high potential AVDD.
2. The highly integrated ultrasonic transmitting and transceiving switching chip according to claim 1, wherein the high voltage transmitting circuit comprises:
the high-voltage current steering digital-to-analog converter, the high-voltage current mirror, the resistor Rt and the high-voltage output driving circuit;
the transmitting waveform control logic controls the high-voltage current steering digital-to-analog converter to generate programmable current, the programmable current generates proportional mirror image current through the high-voltage current mirror, the proportional mirror image current generates high-voltage signals with any waveform after flowing through the resistor Rt, and the high-voltage waveform signals generate waveform signals with high-current driving capability through the high-voltage output driving circuit.
3. The high-integration ultrasonic transmitting and receiving-switching chip of claim 2, wherein the high-voltage current steering dac comprises an N-type high-voltage current steering dac and a P-type high-voltage current steering dac, and the high-voltage current mirror comprises a P-type high-voltage current mirror and an N-type high-voltage current mirror;
the N-type high-voltage current steering digital-to-analog converter is connected with the P-type high-voltage current mirror, and the P-type high-voltage current steering digital-to-analog converter is connected with the N-type high-voltage current mirror.
4. The high-integration ultrasonic transmitting and receiving/transmitting switching chip according to claim 3, wherein the N-type high-voltage current steering DAC comprises an N-type unit current mirror and an N-type high-voltage isolation switch, the N-type unit current mirror is implemented by using a low-voltage NMOS transistor with a fixed gate voltage bias, and the N-type high-voltage isolation switch is implemented by using an N-type high-voltage NMOS transistor to implement a gate voltage controlled switch.
5. The high-integration ultrasonic transmitting and receiving/transmitting switching chip according to claim 3, wherein the P-type high-voltage current steering DAC comprises a P-type unit current mirror and a P-type high-voltage isolation switch, the P-type unit current mirror is implemented by using a low-voltage PMOS (P-channel metal oxide semiconductor) tube with a fixed gate voltage bias, and the P-type high-voltage isolation switch is implemented by using a P-type high-voltage tube to implement a gate voltage controlled switch.
6. The chip of claim 3, wherein the programmable currents IR _ P, IR _ N generated by the N-type HVDC DAC and the P-type HVDC DAC are respectively inputted into the P-type HVDC mirror and the N-type HVDC mirror, and then the generated proportional mirror currents are respectively denoted as IO _ P, IO _ N, and the proportional mirror currents IO _ P and IO _ N cannot be simultaneously different from 0, i.e. when IR _ P ≠ 0, IR _ N =0, or when IR _ N ≠ 0, IR _ P = 0.
7. The highly integrated ultrasound transmitting and transceiving switching chip of claim 6, wherein said transmit waveform control logic is further connected to a voltage comparator circuit for calibrating the programmable current IR _ P, IR _ N generated by the N-type high voltage current steering DAC and the P-type high voltage current steering DAC;
the voltage comparison circuit compares the voltage Vr generated by the proportional mirror current IO _ P, IO _ N flowing through the resistor Rt with the reference voltage Vref.
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| CN115586738A (en) * | 2022-11-25 | 2023-01-10 | 成都千嘉科技股份有限公司 | Switching circuit of ultrasonic flowmeter and control method thereof |
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| JP2008512168A (en) * | 2004-09-13 | 2008-04-24 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | Integrated circuit to realize high voltage ultrasonic function |
| CN101601594B (en) * | 2009-07-08 | 2012-01-18 | 汕头市超声仪器研究所有限公司 | Excitation method of medical B-ultrasound front-end excitation device |
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| US10517570B2 (en) * | 2014-06-13 | 2019-12-31 | Hitachi, Ltd. | Switch circuit, ultrasound probe using the same, and ultrasonic diagnosis apparatus |
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| CN109283251B (en) * | 2017-07-19 | 2021-02-09 | 中国科学院声学研究所 | Signal processing circuit of well wall imaging ultrasonic phased array |
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| CN111679263A (en) * | 2020-07-28 | 2020-09-18 | 郑州师范学院 | Multichannel ultrasonic ranging control system |
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