CN114070762A

CN114070762A - Network monitoring probe assembly, synchronization method and data acquisition and analysis device

Info

Publication number: CN114070762A
Application number: CN202010743304.2A
Authority: CN
Inventors: 张蕾; 李金艳; 李红祎; 赵一荣
Original assignee: China Telecom Corp Ltd
Current assignee: China Telecom Corp Ltd
Priority date: 2020-07-29
Filing date: 2020-07-29
Publication date: 2022-02-18
Anticipated expiration: 2040-07-29
Also published as: CN114070762B

Abstract

The invention relates to a network monitoring probe assembly, a synchronization method and a data acquisition and analysis device. The network monitoring probe assembly includes: the GPS time service module acquires GPS time information; a high frequency clock module for generating a high frequency clock signal; a data acquisition module which acquires data, generates a timestamp request when a timestamp is required for the acquired data, transmits the timestamp request to the clock synchronization control module, and reads the timestamp from the clock synchronization control module in response to receiving a timestamp ready notification; and a clock synchronization control module for acquiring GPS time information from the GPS time service module, acquiring a high frequency clock signal from the high frequency clock module, generating a coarse time part of the time stamp by using the GPS time information, generating a fine time part of the time stamp by using the high frequency clock signal and a correction factor, and generating the time stamp according to the coarse time part and the time part, wherein the correction factor is a time delay correction amount for synchronizing the time stamp of the network monitoring probe assembly with the time stamp of the network monitoring probe assembly as a reference.

Description

Network monitoring probe assembly, synchronization method and data acquisition and analysis device

Technical Field

The invention belongs to the technical field of 5G communication, and particularly relates to a network monitoring probe assembly, a synchronization method and a data acquisition and analysis device for safety monitoring of a 5G core network capacity open interface.

Background

Compared with the core Network of the fifth generation mobile communication Network, a special Function, namely Network Function opening (NEF), is added. The network function open service is a result that a core network of a mobile communication network is opened from the previous 2G/3G/4G closed state, can meet more personalized requirements, follows the market opening requirement, and adapts to a new market system.

In the 5G network architecture, the open services provided by the network function are: basic resources, value added services, data information and operation support. The 5G network function opening carries out capability adaptation, packaging and partial arrangement on basic resources, value-added services, data information, operation support, user data value-added services, infrastructure and the like of a core network, and finally provides network capability for a third party through a unified interface.

The network capability opening is a service facing a third party outside a network, the safety of the network is extremely important, all-weather monitoring and precaution are required, and a capability opening caller needs to be fully authenticated and network information needs to be effectively protected. At present, in order to effectively isolate network resources from third-party callers, a processing mode of information transfer by an NEF gateway is adopted, and the third-party callers acquire the network resources and need to pass through the NEF gateway.

In order to ensure the network security in the access process of the third-party caller, some necessary monitoring software can be deployed on the NEF gateway, and even a firewall and other devices are added on each route in the north direction and the south direction of the NEF gateway, but the load of the NEF gateway is greatly increased, the time delay and complexity of the call are also increased, and the effective analysis of the access association degree from the data depth and based on the time dimension is difficult to realize.

Probes for a monitoring system are distributed and deployed on different network element interfaces, the network elements often process different physical space positions, and the probes deployed in the system must form a whole to implement effective monitoring of the interfaces, wherein clock synchronization is particularly important; the probe is used for detecting the accurate moment when the information appears in the interface, the moment is an important judgment condition for judging the flow direction of the information and carrying out accurate tracking, and the precision is extremely important.

In the process of detecting information, the probe stamps a time stamp (namely a time tag) on the received information; one piece of information passes through a plurality of interfaces in sequence on the network and is detected by the probes on the corresponding interfaces, and the time stamps printed by the probes for the information correspond to the sequence of passing through each interface; if the time of each probe is asynchronous, serious consequences can be caused, the information is detected later, the time of the information is in front, and vice versa, so that the time of the information is out of order, the accurate tracking of the information flow direction cannot be realized, and reliable and basic support cannot be provided for later advanced statistical analysis, such as the occurrence time, the dwell time length of a certain network element, the occurrence frequency of associated information and the like.

Disclosure of Invention

The time synchronization problem of the probe is important in a distributed monitoring system, and particularly in a 5G core network, the flow and the flow speed of the probe are greatly improved compared with the prior art. Heretofore, each Network element in a core Network and monitoring software installed thereon often adopt an NTP (Network Time Protocol) mode to perform clock synchronization, and each Network element acquires synchronization Time from a designated Time server through the NTP Protocol. The NTP synchronization mode is realized by a software system through NTP protocol, transmission network and other modes, and the average precision of time synchronization is not high due to the processing process of the protocol, especially the delay of transmission on different network paths, so that the time stamp precision requirement of the probe cannot be met sometimes.

The present invention is made in view of the above problems, and an object of the present invention is to provide a network monitoring probe assembly and a clock synchronization method for the network monitoring probe assembly, which achieve higher accuracy time synchronization and better satisfy the requirement of the distributed probe on the accuracy of time synchronization.

The following presents a simplified summary of the invention in order to provide a basic understanding of some aspects of the invention. It should be understood, however, that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical elements of the invention or to delineate the scope of the invention. Its sole purpose is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

According to an aspect of the present invention, there is provided a network monitoring probe assembly comprising: the GPS time service module acquires GPS time information, wherein the GPS time information comprises a Pulse Per Second (PPS) and real-time clock information (RTC); a high frequency clock module for generating a high frequency clock signal; a data acquisition module which acquires data, generates a timestamp request when a timestamp is required for the acquired data, transmits the timestamp request to a clock synchronization control module, and reads a timestamp from the clock synchronization control module in response to receiving a timestamp ready notification from the clock synchronization control module; and the clock synchronization control module acquires the GPS time information from the GPS time service module, acquires the high-frequency clock signal from the high-frequency clock module, generates a coarse time part of a time stamp by using the GPS time information, generates a fine time part of the time stamp by using the high-frequency clock signal and a correction factor, and generates the time stamp according to the coarse time part and the time part, wherein the correction factor is a time delay correction amount for synchronizing the time stamp of the network monitoring probe assembly with the time stamp of a network monitoring probe assembly serving as a reference.

According to another aspect of the present invention, there is provided a data collecting and analyzing apparatus, comprising: one or more of the above-described network monitoring probe assemblies; a data storage for storing the collected data; and a data analysis device for analyzing the collected data.

According to an aspect of the present invention, there is provided a clock synchronization method for a network monitoring probe assembly, the network monitoring probe assembly being the above network monitoring probe assembly, the clock synchronization method comprising: when the corrected network monitoring probe assembly and the network monitoring probe assembly serving as the benchmark are started simultaneously, the nanosecond timer of the network monitoring probe assembly serving as the benchmark starts counting from the arrival time of the edge of the pulse signal per second, stops counting when the edge of the next pulse signal per second arrives, and informs the corrected network monitoring probe assembly through the synchronous interface; in response to receiving the notification, the calibrated network monitoring probe component stops counting; taking the difference value of the count value of the nanosecond counter of the corrected network monitoring probe assembly and the count value of the nanosecond counter of the network monitoring probe assembly as a reference as a correction factor; and generating a timestamp using the high frequency clock signal and a correction factor.

According to one or more embodiments of the invention, a higher-precision time stamp can be provided, a powerful support is provided for the integrated monitoring of the distributed deployed probes, and a basic guarantee is provided for the analysis of the data occurrence time and the flow direction tracking in the monitored network. .

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention. The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram illustrating a network monitoring probe assembly 1 according to one embodiment of the present invention.

Fig. 2 is a block diagram illustrating a data collection and analysis apparatus 100 according to an embodiment of the present invention.

FIG. 3 is a schematic diagram showing a correction factor for a network monitoring probe assembly.

FIG. 4 is a flow diagram illustrating a method of clock synchronization of a network monitoring probe assembly according to one embodiment of the present invention.

Fig. 5 shows a hardware structure diagram of an application example according to the present invention.

Fig. 6 shows a flow chart of the correction high frequency clock module.

Fig. 7 is a flow chart illustrating a flow of the network monitoring probe assembly generating a time stamp.

Detailed Description

Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.

Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

In fig. 1, the network monitoring probe assembly 1 includes a GPS time service module 11, a high-frequency clock module 12, a data acquisition module 13, and a clock synchronization control module 14.

The GPS Time service module 11 is configured to obtain GPS Time information, where the GPS Time information includes a Pulse Per Second (PPS) signal and Real Time Clock information (RTC, Real Time Clock). The GPS time service module 11 receives GPS satellite signals through an antenna and calculates PPS and RTC. The resolved PPS pulse signal GPS _ PPS is a high-precision signal with a period of 1 second, and the leading edge of each pulse signal is input to the clock synchronization control module 14 for a trigger signal of internal processing of the clock synchronization control module 14. The calculated RTC time GPS _ RTC is fed to the clock synchronization control module 14 as the "year, month, day, time minute and second" portion of the combined timestamp, i.e. the coarse time portion. In order to ensure the consistency of the solutions of the PPS and the RTC of each GPS module, the modules of the same manufacturer and the same batch are preferably used. The GPS time service module receives GPS satellite signals to calculate PPS and RTC, and since the probe is usually deployed inside the machine room, there is no signal or the signal is too weak, so in one embodiment, the outdoor GPS signals are introduced to the GPS time service module 11 through a mushroom antenna and a coaxial cable.

The high frequency clock module 12 is used for generating a high frequency clock signal to provide a stable timing signal for the local clock. In one embodiment, the high frequency clock module 12 may employ a high frequency active crystal oscillator. In one embodiment, the active crystal oscillator may be temperature compensated to improve the stability of the signal frequency. In one embodiment, the high frequency clock module 12 may employ a high precision crystal oscillator that is a 0.1ppm temperature compensated active crystal oscillator at 100 MHz.

The data acquisition module 13 is used to acquire data, generate a timestamp request when a timestamp is required for the acquired data, and send the timestamp request to the clock synchronization control module 14. Further, the data collection module 13 reads the time stamp from the clock synchronization control module 14 in response to receiving the time stamp ready notification from the clock synchronization control module 14.

The clock synchronization control module 14 acquires GPS time information from the GPS time service module 11, acquires a high frequency clock signal from the high frequency clock module 12, generates a coarse time portion of a time stamp using the GPS time information, generates a fine time portion of the time stamp using the high frequency clock signal and a correction factor, and generates a time stamp from the coarse time portion and the time portion. The correction factor is a time delay correction amount for synchronizing the time stamp of the network monitoring probe assembly 1 with the time stamp of the network monitoring probe assembly as a reference. In one embodiment, the clock synchronization control module 14 may be implemented by a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC).

In one embodiment, the clock synchronization control module 14 further includes a frequency multiplier that multiplies the acquired high frequency clock signal. In one embodiment, the frequency multiplier may be a phase-locked loop circuit.

In one embodiment, clock synchronization control module 14 includes a nanosecond counter that counts on the order of nanoseconds with a high frequency clock signal. By adopting a nanosecond counter, timing with precision of above microseconds can be realized.

In one embodiment, the clock synchronization control module 14 further comprises a synchronization interface via which the trigger signal is received, and the clock synchronization control module 14 calculates the delay correction amount based on the trigger signal and a count value of the nanosecond counter.

In one embodiment, the clock synchronization control module 14 includes a coarse TIME register (RTC _ TIME _ REG) that updates and stores real-TIME clock information as a coarse TIME part of a TIME STAMP in response to arrival of an edge of a pulse signal per second, a fine TIME register (NS _ COUNTER _ REG) that stores a fine TIME part of the TIME STAMP generated from a count value of a nanosecond COUNTER and a value corrected by a delay correction amount, and a delay correction register (NS _ CORRECT _ REG) that stores a count value of the nanosecond COUNTER and a delay correction amount.

In one embodiment, the delay correction amount is an amount of time corresponding to a difference value between a count value of a nanosecond counter of the network monitoring probe assembly 1 and a count value of a nanosecond counter of the network monitoring probe assembly as a reference during a period from when an edge of the pulse signal per second PPS arrives to when an edge of the next pulse signal per second PPS arrives in a case where the network monitoring probe assembly 1 and the network monitoring probe assembly as a reference are started simultaneously. In one embodiment, the delay correction amount is an average of a plurality of said amounts of time.

As shown in fig. 2, the data acquisition and analysis device 100 includes a data storage 2, a data analysis device 3, and a plurality of network monitoring probe assemblies 1. The memory 2, the data analysis device 3, and the plurality of network monitoring probe assemblies 1 are communicably connected. Two network monitoring probe assemblies 1 are exemplarily shown in fig. 2, but the number of network monitoring probe assemblies 1 may be arbitrary, which matches the number of network elements to be monitored.

And each network monitoring probe component monitors the data of each 5G network element port. For example, in one embodiment, the network monitoring probe assembly 1 monitors data of an access and mobility management function network element AMF (not shown) and the network monitoring probe assembly 1' monitors data of a session management function network element SMF (not shown). The network monitoring probe assemblies 1 and 1' respectively acquire data of AMF and SMF network elements and obtain time stamps from the clock synchronization control module 14, the network element data and the time stamps are combined and sent and stored in the data storage 2, and the data analysis device 3 directly acquires combination information of the network element data and the time stamps from the data storage 2 or from each network monitoring probe assembly, performs various analyses and outputs analysis results.

One embodiment of determining the correction FACTOR NS _ CORRECT _ FACTOR is described below with reference to fig. 3. Before the network monitoring probe assembly is deployed, one network monitoring probe assembly is selected from the multiple network monitoring probe assemblies to serve as a benchmark network monitoring probe assembly, and other network monitoring probe assemblies are aligned with the benchmark network monitoring probe assembly in a time delay mode.

As previously mentioned, each network monitoring probe assembly has a synchronization interface, and the interfaces are connected by cables. In one embodiment, the cable may be a coaxial cable. The network monitoring probe component with the corrected time delay and the network monitoring probe component with the reference time delay are started to work simultaneously, nanosecond counters are started to count when the GPS _ PPS edges are detected to arrive respectively, and the nanosecond counters of the network monitoring probe component with the reference time delay are started to count when the nanosecond counters of the network monitoring probe component with the reference time delay are detected to arriveThe counter value reaches a predetermined value (e.g., 10)⁹(corresponding to 1 second)) the delay corrected network monitor probe assembly is immediately notified via the synchronization interface to stop counting, and the relative delay difference is determined by calculating the difference between the count values in the nanosecond count register NS _ COUNTER _ REG of the two network monitor probe assemblies. In one embodiment, the relative delay difference may be determined from a multiple average of the difference, thereby further improving accuracy. In one embodiment, the number of counts may be set to 30. Assume that the count value for each time of the corrected delay probe is identified as NS _ COUNTER _ REG _ COR_nThen the value of NS _ CORRECT _ REG can be found by the following equation (1):

it should be understood that the number of counts is not limited to 30, and may be arbitrarily set according to actual needs.

NS_CORRECT_REG>Time 0, corrected time delay network monitor probe assembly early time delay T_delayIs small;

the early delay T of the network monitor probe component with corrected delay is 0 when NS _ CORRECT _ REG_delayThe same delay as the reference delay probe;

NS_CORRECT_REG<time 0, corrected time delay network monitor probe assembly early time delay T_delayIs large;

the calculated NS _ CORRECT _ REG is a signed number, the value of which is written to a memory stored in a non-volatile memory. At the start of the network monitor probe component, values are loaded into the NS _ CORRECT _ REG from the non-volatile memory.

As shown in FIG. 3, T_{delay_ref}And T_{delay_cor}Under the condition that GPS _ PPS occurs simultaneously, T is caused by the resolving time difference of respective GPS time service modules and the delay difference of signals on a circuit_{delay_ref}And T_{delay_cor}Are different in size. The correction factor reflects T_{delay_ref}And T_{delay_cor}The difference of (a). By compensation of a correction factor such thatTime stamps of the respective network monitoring probe assemblies are synchronized.

As shown in fig. 4, in step S401, in the case where the corrected network monitoring probe set and the network monitoring probe set as the reference are started simultaneously, the nanosecond timer of the network monitoring probe set as the reference starts counting from the arrival of the edge of the pulse signal per second PPS.

Next, in step S402, the counting is stopped when the edge of the next pulse signal per second arrives and the corrected network monitoring probe assembly is notified through the synchronization interface.

Next, in step S403, in response to receiving the notification, the corrected network monitoring probe component stops counting.

Next, in step S404, a difference between the count value of the nanosecond counter of the network monitoring probe assembly being corrected and the count value of the nanosecond counter of the network monitoring probe assembly being a reference is used as a correction factor.

Next, in step S405, a time stamp is generated using the high frequency clock signal and a correction factor.

< application example >

Hereinafter, a description will be given by referring to a specific hardware application example. It should be noted that the parameters, types, and the like of the hardware listed below are merely examples, and are not intended to limit the scope of the claims of the present invention, and may be appropriately replaced or modified within a scope conforming to the spirit and concept of the present invention.

For a 5G core network, especially for a network capacity open part, the network capacity open platform provides network services to external third-party applications, the network security is particularly prominent, and more effective monitoring can be performed through a distributed monitoring system. In a monitoring system, the acquisition of network data is realized by adopting network monitoring probe components distributed on a plurality of network nodes, and the time synchronization precision among the network monitoring probe components is important for realizing the accurate tracking of the network data. The more accurate the clock synchronization between the network monitoring probe assemblies, the higher the degree of integration of the network monitoring probe assemblies.

In the application example, in order to ensure the clock synchronization precision of above microsecond level, the network monitoring probe assembly adopts a high-speed FPGA, a GPS time service module and a 0.1ppm100MHz temperature compensation type crystal oscillator as hardware basis. In the application example, the FPGA realizes the functions of the data acquisition module and the clock synchronization control module. It should be understood that the data acquisition module and the clock synchronization control module may be implemented by separate devices, or may be implemented by using a dedicated chip.

Referring to fig. 5, in the implementation architecture of the present invention, the FPGA as the core control is connected to the GPS time service module through a level signal and a serial interface, connected to the 0.1ppm100MHz temperature compensation crystal oscillator through a clock interface, connected to the data acquisition module through an internal interface, and connected to other network monitoring probe components through a synchronous interface.

The GPS time service module provides a PPS second alignment function with extremely high precision on one hand, and provides RTC time information containing year, month, day, time, minute and second on the other hand, and the GPS time service precision can reach 10^-9The second is nanosecond and is represented by a high-precision PPS signal, namely, the time precision between two adjacent PPS pulse edges reaches nanosecond, but a thinner and uniformly distributed clock signal does not exist between the two PPS pulse edges. The GPS time service module is connected with the FPGA and provides 2 paths of signals, one path is a PPS pulse signal, and the other path is a serial signal.

The high-precision crystal oscillator as the high-frequency clock module is a 0.1ppm temperature compensation type active crystal oscillator of 100MHz, and provides a stable timing signal for a local clock. And the high-precision crystal oscillator is connected with the FPGA and provides a periodic oscillation signal of 100MHz to the FPGA. Of course, the high-precision crystal oscillator may select a suitable frequency and precision according to actual conditions, for example, a crystal oscillator with a higher frequency and a better precision is selected.

The FPGA acquires and processes 3 paths of clock signals from the GPS time service module and the high-precision crystal oscillator, and outputs high-precision time stamps with year, month, day, hour, minute, second and microsecond to the data acquisition module; in addition, a synchronous interface for time delay correction among different network monitoring probe components is arranged on the FPGA.

The GPS time service module receives GPS satellite signals and calculates PPS and RTC. The network monitoring probe assembly is usually deployed in a machine room, and has no signal or weak signal, so that an outdoor GPS signal needs to be introduced to the GPS time service module through a mushroom antenna and a coaxial cable. The resolved PPS pulse signal GPS _ PPS is a high-precision alignment signal with the period of 1 second, and the leading edge of each pulse is input to the FPGA to be used as a trigger signal for internal processing of the FPGA. The resolved RTC time GPS _ RTC is fed to the FPGA through a serial port in a fixed plaintext protocol format as the coarse time portion of the combined timestamp. In order to ensure the consistency of the PPS and RTC calculation of a plurality of GPS modules, it is preferable to select GPS modules of the same manufacturer and the same batch.

The high-precision active crystal oscillator singly provides a signal OSC-100 MHZ with the frequency of 100MHz and 0.1ppm to the FPGA, and a temperature compensation type is selected to improve the stability of the signal frequency. This signal serves as a source of counts in clock synchronization that produce "fine time".

The high-speed FPGA is a processing part in clock synchronization and is externally provided with 4 interfaces: the system comprises an interface connected with a GPS time service module, an interface connected with a high-precision crystal oscillator, a component synchronization interface and a timestamp output interface (in an application example, the interface is connected with other modules in the FPGA). The high-speed FPGA is internally designed with 5 registers: a coarse TIME register RTC _ TIME _ REG, a fine TIME register US _ TIME _ REG, a timestamp register TIME _ STAMP _ REG, a nanosecond count register NS _ COUNTER _ REG, a delay correction register NS _ CORRECT _ REG. In addition, a correction FACTOR NS _ CORRECT _ FACTOR stored in the non-volatile memory is provided.

The FPGA synchronous clock processing process comprises 2 stages: a basic synchronization phase and a delay correction phase.

First, the basic synchronization phase is explained.

The FPGA firstly utilizes a phase-locked loop in the FPGA to carry out 10 frequency multiplication on an input OSC _100MHZ signal to obtain a signal PLL _1GHZ at 1GHZ, and the signal is used for pushing nanosecond counting to count. When the FPGA detects that the GPS _ PPS edge arrives, the asynchronous clearing of the NS _ COUNTER _ REG is started immediately, the nanosecond COUNTER is started to start counting, when the FPGA detects that the time stamp signal which is requested by the data acquisition module arrives, the counting of the nanosecond COUNTER is stopped immediately and asynchronously, and at the moment, the counting value of the COUNTER is stored in the NS _ COUNTER _ REG. Nanosecond pulses are used for counting, and are finally converted into microseconds of fine time, so that the accuracy of time can be improved.

Next, the delay correction stage is explained.

The FPGA carries out delay correction on the NS _ COUNTER _ REG according to the value in the NS _ CORRECT _ REG, and a microsecond part is intercepted from the corrected value and is given to the US _ TIME _ REG. The RTC TIME is also read and assigned to the RTC _ TIME _ REG when the FPGA detects that the GPS _ PPS edge arrives. The FPGA assembles RTC _ TIME _ REG and US _ TIME _ REG into a completed timestamp to be stored in TIME _ STAMP _ REG, and informs an acquisition module to take the timestamp away.

The following two clock correction processes can be performed before the FPGA clock synchronization is formally enabled to ensure the accuracy of the time stamp: the high-frequency clock module is used for correcting the stability of the PLL _1GHZ signal within 1 second; and a correction FACTOR correction process for determining a correction FACTOR NS _ CORRECT _ FACTOR.

(1) High frequency clock module correction process

The high frequency clock module is used for correcting the PLL _1GHZ signal to enable the stability of the PLL _1GHZ signal to reach a specified range. Fig. 6 shows a flow chart of the correction high frequency clock module.

As shown in fig. 6, at the start of the correction, when the FPGA detects the arrival of a GPS _ PPS edge, the nanosecond COUNTER is started, when the arrival of the next GPS _ PPS edge is detected, the FPGA stops counting, and it is then determined whether the value in the NS _ COUNTER _ REG is 100 (i.e., 10)⁹×(±10^-7) ) was fluctuated within the range, and the measurement was repeated 30 times. If so, indicating that the OSC _100MHZ crystal oscillator meets the requirement of 0.1ppm of stability, lightening a green indicator lamp on the board card, otherwise, lightening a yellow indicator lamp on the board card to prompt the OSC _100MHZ crystal oscillator to be replaced, and continuing the stability measurement of a PLL _1GHZ signal until the stability measurement is finishedUntil the green indicator light is lit.

(2) Correction factor correction process

The correction FACTOR correction process is used to determine a correction FACTOR NS _ CORRECT _ FACTOR.

After the stability of the PLL _1GHZ corrected in the prior art meets the requirement, before the network monitoring probe assembly is deployed, one network monitoring probe assembly is selected from the multiple network monitoring probe assemblies to serve as the network monitoring probe assembly with clock reference time delay, and the other network monitoring probe assemblies and the network monitoring probe assembly with the reference time delay are subjected to time delay alignment. As mentioned above, each network monitoring probe component has a synchronous interface, the interfaces are connected through a coaxial cable, the two network monitoring probe components start to work simultaneously, a nanosecond counter is started to count when the GPS _ PPS edge is detected to arrive respectively, and when the reference time delay network monitoring probe component count reaches 10⁹At this time, another network monitor probe module (i.e., the delay-corrected network monitor probe module) is immediately notified via the inter-board synchronization interface to stop counting, and the relative delay difference is determined by averaging a plurality of times the difference between the NS _ COUNTER _ REGs of the two network monitor probe modules, the number of counts being selected as one example to be 30. The count value for each time a network monitor probe assembly is assumed to be corrected for latency is identified as NS _ COUNTER _ REG _ COR_n. The value of NS _ CORRECT _ REG is:

NS _ CORRECT _ REG is a signed number, the value of which is written to a memory stored in a non-volatile memory. The values fetched from non-volatile memory are loaded into the NS _ CORRECT _ REG at network monitor probe component startup.

As shown in FIG. 3, T_{delay_ref}And T_{delay_cor}Under the condition that GPS _ PPS occurs simultaneously, T is caused by the resolving time difference of respective GPS time service modules and the delay difference of signals on a circuit_{delay_ref}And T_{delay_cor}Are different in size. NS _ CORRECT _ REG reflects T_{delay_ref}And T_{delay_cor}The difference of (a).

After calibration is complete, the network monitoring probe assembly can be deployed to each monitored network interface to begin operation.

Fig. 7 is a flow chart illustrating a flow of the network monitoring probe assembly generating a time stamp. As shown in fig. 7, the time stamp generation includes the steps of:

when the FPGA detects that the GPS _ PPS edge arrives in step S701, it then starts asynchronous clearing of the NS _ COUNTER _ REG and starts a nanosecond COUNTER to start counting in step S702. Next, in step S703, the FPGA determines whether it detects a signal of the data acquisition module asking for a timestamp, and when the FPGA detects that the signal of the data acquisition module asking for a timestamp arrives (i.e., "yes" in step S703), the FPGA proceeds to step S704 to asynchronously stop counting of the nanosecond COUNTER, and the count value of the COUNTER is stored in the NS _ COUNTER _ REG. Next, in step S705, the FPGA performs delay correction on the NS _ COUNTER _ REG according to the value in the NS _ CORRECT _ REG, and cuts out the microsecond part from the corrected value and assigns the microsecond part to the US _ TIME _ REG, forming a microsecond part of a fine TIME (step S706). Next, in step S707, the FPGA reads the RTC TIME when detecting that the GPS _ PPS edge arrives, and assigns the RTC TIME to the RTC _ TIME _ REG, forming a coarse TIME portion. Next, in step S708, the FPGA assembles RTC _ TIME _ REG and US _ TIME _ REG into a completed timestamp and stores the timestamp in TIME _ STAMP _ REG, and notifies the collection module to take the timestamp away. If the data acquisition module does not retrieve the timestamp signal within the 1 second period, the count is re-counted when the next GPS _ PPS edge arrives. Thereafter, steps S701 to S707 are repeated.

Furthermore, in one embodiment, the fine time portion in step S706 is not limited to microseconds, for example, the fine time portion may be retained in a tenth microsecond, hundredth microsecond portion to further improve the precision of the time stamp.

According to the embodiment, the frequency of 100MHz of 0.1ppm is multiplied by a phase-locked loop in the FPGA, the counting granularity is refined, nanosecond-level clock counting is carried out in a mode that a GPS _ PPS edge triggers a nanosecond counter, and furthermore, the clock synchronization precision of the probe is improved by ensuring the counting stability and the time delay alignment among different network monitoring probe components through two correction modes. Therefore, the microsecond-level and even higher-precision time stamp can be provided, powerful support is provided for integrated monitoring of the distributed deployed probes, and basic guarantee is provided for analysis of data occurrence time and flow direction tracking and the like in a monitored network.

It should be appreciated that reference throughout this specification to "an embodiment" or similar language means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, appearances of the phrases "in embodiments of the invention" and similar language throughout this specification do not necessarily all refer to the same embodiment.

As will be appreciated by one skilled in the art, the present invention may be embodied as a system, apparatus, method, or computer-readable medium (e.g., non-transitory storage medium) as a computer program product. Accordingly, the present invention may be embodied in various forms, such as an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-program code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a "circuit," module "or" system. Furthermore, the present invention may also be embodied in any tangible medium as a computer program product having computer usable program code stored thereon.

The present invention is described with reference to flowchart illustrations and/or block diagrams of systems, apparatuses, methods and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and any combination of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be executed by a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, implement the functions or acts specified in the flowchart and/or block diagram block or blocks.

Flowcharts and block diagrams of the architecture, functionality, and operation that may be implemented by the systems, devices, methods and computer program products according to various embodiments of the present invention are shown in the accompanying drawings. Accordingly, each block in the flowchart or block diagrams may represent a module, segment, or portion of program code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in the drawings may be executed substantially concurrently, or in some cases, in the reverse order from the drawing depending on the functions involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the market technology, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A network monitoring probe assembly comprising:

the GPS time service module acquires GPS time information, wherein the GPS time information comprises a Pulse Per Second (PPS) and real-time clock information (RTC);

a high frequency clock module for generating a high frequency clock signal;

a data acquisition module which acquires data, generates a timestamp request when a timestamp is required for the acquired data, transmits the timestamp request to a clock synchronization control module, and reads a timestamp from the clock synchronization control module in response to receiving a timestamp ready notification from the clock synchronization control module; and

the clock synchronization control module acquires the GPS time information from the GPS time service module, acquires the high-frequency clock signal from the high-frequency clock module, generates a coarse time part of a time stamp by using the GPS time information, generates a fine time part of the time stamp by using the high-frequency clock signal and a correction factor, and generates the time stamp according to the coarse time part and the time part, wherein the correction factor is a time delay correction value for synchronizing the time stamp of the network monitoring probe assembly with the time stamp of the network monitoring probe assembly serving as a reference.

2. The network monitoring probe assembly of claim 1,

the clock synchronization control module comprises a frequency multiplier which multiplies the frequency of the high-frequency clock signal.

3. The network monitoring probe assembly of claim 1,

the clock synchronization control module comprises a nanosecond counter which counts on the nanosecond scale by using the high-frequency clock signal.

4. The network monitoring probe assembly of claim 1,

the clock synchronization control module comprises a synchronization interface, receives a trigger signal through the synchronization interface, and calculates the time delay correction value according to the trigger signal and the count value of the nanosecond counter.

5. The network monitoring probe assembly of claim 1,

the clock synchronization control module comprises a coarse time register, a fine time register, a timestamp register, a nanosecond counting register and a time delay correction register,

the coarse time register updates and stores the real-time clock information as a coarse time part of a time stamp in response to arrival of an edge of the pulse signal per second, the fine time register stores a fine time part of the time stamp generated according to a count value of the nanosecond counter and a value corrected by the delay correction amount, the time stamp register stores the generated time stamp, the nanosecond count register stores a count value of the nanosecond counter, and the delay correction register stores the delay correction amount.

6. The network monitoring probe assembly of claim 3,

the delay correction amount is an amount of time corresponding to a difference value between a count value of a nanosecond counter of the network monitoring probe assembly and a count value of a nanosecond counter of the network monitoring probe assembly serving as a reference in a period from when an edge of the pulse signal per second arrives to when an edge of the pulse signal per second arrives, in a case where the network monitoring probe assembly serving as a reference and the network monitoring probe assembly serving as a reference are simultaneously started.

7. The network monitoring probe assembly of claim 6,

the delay correction amount is an average of a plurality of the amounts of time.

8. The network monitoring probe assembly of claim 1,

the high-frequency clock module is a 0.1ppm temperature compensation type active crystal oscillator of 100 MHz.

9. A data collection and analysis device comprising:

the network monitoring probe assembly of any one of the preceding claims 1-8;

a data storage for storing the collected data; and

and the data analysis device is used for analyzing the acquired data.

10. A clock synchronization method of a network monitoring probe assembly as claimed in any one of claims 1 to 8, the clock synchronization method comprising:

when the corrected network monitoring probe assembly and the network monitoring probe assembly serving as the benchmark are started simultaneously, the nanosecond timer of the network monitoring probe assembly serving as the benchmark starts counting from the arrival time of the edge of the pulse signal per second, stops counting when the edge of the next pulse signal per second arrives, and informs the corrected network monitoring probe assembly through the synchronous interface;

in response to receiving the notification, the calibrated network monitoring probe component stops counting;

taking the difference value of the count value of the nanosecond counter of the corrected network monitoring probe assembly and the count value of the nanosecond counter of the network monitoring probe assembly as a reference as a correction factor; and

generating a timestamp using the high frequency clock signal and a correction factor.