CN114070316B - Multi-phase clock generation circuit and analog-to-digital converter - Google Patents
Multi-phase clock generation circuit and analog-to-digital converter Download PDFInfo
- Publication number
- CN114070316B CN114070316B CN202111364008.2A CN202111364008A CN114070316B CN 114070316 B CN114070316 B CN 114070316B CN 202111364008 A CN202111364008 A CN 202111364008A CN 114070316 B CN114070316 B CN 114070316B
- Authority
- CN
- China
- Prior art keywords
- latches
- group
- flip
- clock
- generation circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 claims description 16
- 238000000819 phase cycle Methods 0.000 description 15
- 238000010586 diagram Methods 0.000 description 13
- 230000000630 rising effect Effects 0.000 description 9
- 238000005070 sampling Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000009466 transformation Effects 0.000 description 3
- 238000000844 transformation Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000004458 analytical method Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000001976 improved effect Effects 0.000 description 1
- 230000000116 mitigating effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/462—Details of the control circuitry, e.g. of the successive approximation register
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Manipulation Of Pulses (AREA)
Abstract
The invention relates to a multi-phase clock generating circuit and an analog-to-digital converter, wherein the multi-phase clock generating circuit comprises a shift register chain. Wherein the shift register chain comprises 3 or more latches (Latch) divided into at least 2 groups, wherein a first group comprises 1 or more latches and a second group comprises 2 or more latches; wherein two adjacent latches in each group are cascaded. The multi-phase clock generation circuit can compromise the situation that the propagation delay inevitable inside a shift register chain and the phase interval of each path of frequency division clock signal is small.
Description
Technical Field
The present invention relates to clock generation circuits, and particularly to a multi-phase clock generation circuit and an analog-to-digital converter.
Background
Analog-to-Digital Converters (ADCs) are circuits that convert Analog signals into Digital signals, so as to process Analog signals in the nature with a Digital signal processor, and have a very wide application field and prospect. In order to increase the sampling rate of the ADC, an ADC with a multi-path time interleaving architecture has been developed. In the multi-path time-interleaved ADC, the multi-phase clock generation circuit adopted by the multi-path time-interleaved ADC plays a crucial role in realizing the function and ensuring the performance of the multi-phase clock generation circuit.
In order to determine the phase sequence relationship of the multiple clock signals, a shift register method based on a flip-flop is generally adopted in the industry. Assuming that the system master clock of the multi-path time-interleaved ADC is CK _ master, the phase delay between the multi-phase clocks is related to the period of the CK _ master.
Referring to fig. 1 and 2, a shift register chain 100 'composed of 4D Flip-flops (DFFs) 10' and its ideal output timing are shown. As shown, where CK4_ IP, CK4_ QP, CK4_ IN, and CK4_ QN are the divided-by-4 clocks of the system master clock CK _ master, the respective divided clock signals have a front-to-back phase difference of 90 °, i.e., the divided-by-first clock signal CK4_ IP and the divided-by-second clock signal CK4_ QP have a phase difference of 90 °, and the respective divided clock signals are delayed from each other by one system master clock cycle. CK16_ IN is a 16 division of the system master clock with a duty cycle of 1:4.
Further, IN the shift register chain 100 'composed of the 4D flip-flops 10', CK16_ IN is used as an input signal, and CK16_ IN is used as a clock signal for triggering the DFF by using the divided-by-4 clock signals CK4_ IP, CK4_ QP, CK4_ IN, and CK4_ QN of the master clock signal IN turn as clock signals for triggering the DFF<3:0>Is the output clock. Assuming propagation delay (CK-) of the D flip-flop>Q) is t c-q With a setup time of t set-up Then, one of the timing constraints required for the circuit to operate correctly is:
t c-q +t set-up ≤T
where T denotes the period of the system master clock CK _ master.
For ease of analysis, t can be ignored set-up The propagation delay of the D flip-flop needs to be less than one system master clock cycle. This condition is easier to satisfy when the system master clock frequency is low.
However, for the ADC with the multi-path time interleaving architecture, the system master clock frequency is generally higher. For example, if the system master clock frequency is 64GHz, the master clock period is 15.625ps, which may pose a great challenge to the normal operation of the clock generation circuit. If the propagation delay of the D flip-flop is greater than one system master clock cycle, then the correct timing cannot be obtained. FIG. 3 is a timing diagram of an error caused by an excessive propagation delay of the D flip-flop.
As shown IN fig. 3, the input clock CK16_ IN is transferred to CK16<0> triggered by the rising edge of CK4_ IP. Ideally, CK16<0> as the input to the next stage flip-flop should be sampled by the CK4_ QP rising edge immediately adjacent to the CK4_ IP rising edge. Due to the effect of the propagation delay of the D flip-flop 10', the interval between the CK16<0> rising edge and the CK4_ IP rising edge is larger than one system master clock cycle, so that CK16<0> cannot be sampled by the expected CK4_ QP rising edge, but is sampled by the next rising edge, and the output CK16<1> differs from the expected waveform by one CK4_ QP cycle. There is also a case where the propagation delay of the D flip-flop 10' is exactly one system master clock cycle, so that the rising edge of CK16<0> occurs exactly at the same time as the rising edge of CK4_ QP, and thus, the CK16<1> cannot be outputted correctly because the requirement of setup time or hold time cannot be satisfied.
Therefore, there is a need to develop a new clock generation circuit to overcome the drawbacks of the prior art.
Disclosure of Invention
The present invention is directed to a multi-phase clock generating circuit, which can compromise between the inevitable propagation delay inside a shift register chain and the small phase interval of each divided clock signal, and solve the problem of error timing caused by the large propagation delay inside the shift register chain of the clock generating circuit in the prior art.
To achieve the above object, one embodiment of the present invention provides a multiphase clock generation circuit including a shift register chain. Wherein the shift register chain comprises 3 or more latches (Latch) divided into at least 2 groups, wherein a first group comprises 1 or more latches and a second group comprises 2 or more latches; wherein adjacent latches in each group are cascaded.
Further, in different embodiments, the number of the groups of the latches may be 2, 3, 4, 5, 6, 7, 8 or more, and the specific number of the groups may be determined as needed and is not limited; the specific number of latches included in each independent group may be the same or different, and is also determined by the need, and is not limited.
For example, the number of latches included in the first group may be the same as or different from the number of latches included in the second group, and the number of latches may be determined as needed and is not limited. The same applies to the case of 3 packets, 4 packets, 5 packets, 6 packets, 7 packets, 8 packets or more. Some examples, but not limitations, of the grouping are given below.
Wherein in an embodiment the latches are divided into a first group comprising an even number of latches and a second group comprising an even number of latches. For example, the number of latches included in two groups is the same, and specifically may be 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32 …, 66, 68 … 124, 126, 128 … 254, 256, 258, and so on, but is not limited thereto.
Further, in various embodiments, the latches are divided into a first group and a second group, wherein the first group includes power of 2 latches and the second group includes power of 2 latches. For example, the number of latches included in the two groups is the same, and may be specifically 2, 4, 8, 16, 32, 64, 128, 256, and the like, but is not limited thereto.
Further, in various embodiments, the latches are divided into a first group and a second group, where the first group includes 2 latches and the second group includes 3 latches. In yet another embodiment, wherein the first packet includes 4 latches, the second packet includes 6 latches. In yet another embodiment, wherein the first group includes 8 latches, the second group includes 12 latches.
Further, in yet another embodiment, the latches are divided into a first group comprising 1 latch, a second group comprising 2 latches, and a third group comprising 3 latches. In yet another embodiment, the latches are divided into a first group comprising 2 latches, a second group comprising 3 latches, and a third group comprising 2 latches. In yet another embodiment, the latches are divided into a first group comprising an even number of latches, a second group comprising an even number of latches, and a third group comprising an even number of latches.
Further, in various embodiments, the latches are divided into a first group comprising 1 latch, a second group comprising 2 latches, a third group comprising 3 latches, and a fourth group comprising 4 latches. In yet another embodiment, the latches are divided into a first group comprising 4 latches, a second group comprising 4 latches, a third group comprising 4 latches, and a fourth group comprising 4 latches. In yet another embodiment, the latches are divided into a first group comprising power of 2 latches, a second group comprising power of 2 latches, a third group comprising power of 2 latches, and a fourth group comprising power of 2 latches.
Further, for more packet implementations and implementations with the number of latches included in each packet, those skilled in the art can make various equivalent transformations according to the above descriptions, and details are not described herein again. Such equivalent variations are not to be regarded as a departure from the scope of the present disclosure.
Further, in various embodiments, the delay between the trigger clock signals input by the two latches in each group is at least greater than one system master clock period of the system in which the two latches are located. Specifically, the number of the cells may be 1.2, 1.5, 1.8, 2, 2.5, 3, 3.5, 4, 5, etc., and is not limited to any specific value, depending on the actual needs.
Further, in various embodiments, the phase difference between the trigger clock signals respectively input to two adjacent latches in each group is greater than 90 °. Further, in various embodiments, the phase difference between the two may be one of 100 °, 120 °, 150 °, 180 °, 210 °, 240 °, 270 °, 300 °, 330 °, 360 °, 450 °, 540 °, 630 °, 720 °, 810 °, 900 °, 990 °, and 1080 °, or the like.
Further, in different specific embodiments, the phase difference between the two may be, specifically, 95 °, 100 °, 105 °, 110 °, 115 °, 120 °, 125 °, 130 °, 135 °, 140 °, 145 °, 150 °, 155 °, 160 °, 165 °, 170 °, 175 °, 180 °, 185 °, 190 °, 195 °, 200 °, 205 °, 210 °, 215 °, 220 °, 225 °, 230 °, 235 °, 240 °, 245 °, 250 °, 255 °, 260 °, 265 °, 270 °, 275 °, 280 °, 285 °, 290 °, 295 °, 300 °, 305 °, 310 °, 315 °, 320 °, 325 °, 330 °, 335 °, 340 °, 345 °, 355 °, 360 °, 450 °, 540 °, 630 °, 720 °, 810 °, 900 °, 990 °, and 1080 °, which are also illustrative and non-limiting.
Further, in different embodiments, the trigger clock signal input by each group of latches is a frequency division clock signal of the system master clock signal where the trigger clock signal is located, and the frequency division clock signal is sequentially and alternately input to the latches of each group according to a sequential phase sequence and is used as the input trigger clock signal of each group of latches.
Here, the "sequentially alternate" input implementation means that the divided clock signal is not sequentially input to the first group latch and the second group latch in order, that is, the divided clock signal input to the subsequent group latch is started after the first group latch is completed; the frequency division clock signal completes the input of the first bit latch of each group in turn according to the phase sequence, namely the first bit latch of the first group and the first bit latch of the second group in turn until the first bit latch of the last bit group carries out the input of the frequency division clock signal; then, the input of the second bit latch of each group is performed in the grouped sequence, and so on until the input of the last bit latch of each group, which is implemented as the 'sequentially alternate' input.
Further, in different embodiments, the same number of divided clock signals may correspond to different numbers of groups, for example, a 4-divided clock signal of a system master clock signal may correspond to a group of 2 latches, and may also correspond to a group of 4 latches; and under the same grouping quantity, the same quantity of frequency-divided clock signals can also correspond to the situation of different quantities of latches in the grouping, for example, under the situation of 2 groupings, the frequency-divided clock signal of 4 of a system master clock signal can correspond to the situation of 2 latches per grouping, also can correspond to the situation of 4 latches per grouping, also can correspond to the situation of 8 latches per grouping, and the situation of 16 latches, 32 latches, 64 latches, and so on; the specific property can be determined according to actual needs, and is not limited. That is, the number of latches is equal to or greater than the number of divided clock signals of the system master clock, preferably an integer multiple of the latter; for example, the amount may be specifically 1 time, 2 times, 3 times, 5 times, 6 times, 10 times, 20 times, and the like, and the specific amount may be determined as needed, and is not limited. Some examples, but not limitations, will be given below. For example, in one embodiment, the latches comprise 2 groups, each group comprising 2 cascaded latches, the input trigger clock signal of each cascaded latch being a divided-by-4 clock signal of a system master clock signal, the divided-by-4 clock signals being sequentially alternated in phase sequence as trigger clock signal inputs for the latches of the first group and the latches of the second group; namely, the frequency-divided clock signals of the first bit and the third bit are the trigger clock signals of the latches of the first packet two-cascade connection, and the frequency-divided clock signals of the second bit and the fourth bit are the trigger clock signals of the latches of the second packet two-cascade connection.
For example, in a further embodiment, the latches comprise 2 groups, each group comprising 4 cascaded latches, the input trigger clock signal of which is a divided by 4 clock signal of a system master clock signal, the divided by 4 clock signals being sequentially alternated in phase sequence as trigger clock signal inputs for the latches of the first and second groups; namely, the frequency-divided clock signals of the first bit, the third bit, the first bit and the third bit are the trigger clock signals of the first group of 4 cascaded latches, and the frequency-divided clock signals of the second bit, the fourth bit, the second bit and the fourth bit are the trigger clock signals of the second group of 4 cascaded latches.
In another embodiment, the latches include 3 groups, each group includes 2 cascaded latches, and the input trigger clock signal of each group is a divided-by-6 clock signal of a system master clock signal, the divided-by-6 clock signals are sequentially and alternately input as the trigger clock signals of the latches of the first group, the second group and the third group in phase sequence, that is, the divided-by-6 clock signals of the first bit and the fourth bit are the trigger clock signals of the latches of the two cascaded latches of the first group, the divided-by-second clock signal of the second bit and the fifth bit are the trigger clock signals of the latches of the two cascaded latches of the second group, and the divided-by-third bit and the sixth bit are the trigger clock signals of the latches of the two cascaded latches of the third group.
In yet another embodiment, the latches comprise 2 groups, wherein a first group comprises 5 cascaded latches and a second group comprises 4 cascaded latches; correspondingly, the input trigger clock signal is a 4-frequency division clock signal of a system master clock, and the 4-frequency division clock signals are sequentially and alternately used as the trigger clock input of the first grouping latch and the second grouping latch in a phase sequence; namely, the single-bit frequency-divided clock signal is the trigger clock signal of the latches of the first packet cascade, and the even-bit frequency-divided clock signal is the trigger clock of the latches of the second packet cascade.
In yet another embodiment, the latches comprise 2 groups, each group comprising 8 cascaded latches, the input trigger clock signal of each group being a divided-by-8 clock signal of a system master clock, the divided-by-8 clock signals being sequentially alternated in phase sequence as trigger clock signal inputs for latches of the first group and the second group; namely, the single-digit frequency-divided clock signal is the trigger clock signal of the first group of cascaded latches, and the even-digit frequency-divided clock signal is the trigger clock signal of the second group of cascaded latches.
In yet another embodiment, the latches comprise 4 groups, each group comprising 4 cascaded latches, the input trigger clock signal of each group being a divided-by-8 clock signal of a system master clock, the divided-by-8 clock signals being sequentially alternated in phase sequence as trigger clock signal inputs for latches of the first, second, third and fourth groups; namely, the frequency-divided clock signals of the first bit, the fifth bit, the first bit and the fifth bit are the trigger clock signals of the latches in the first packet cascade, the frequency-divided clock signals of the second bit, the sixth bit, the second bit and the sixth bit are the trigger clock signals of the latches in the second packet cascade, the frequency-divided clock signals of the third bit, the seventh bit, the third bit and the seventh bit are the trigger clock signals of the latches in the third packet cascade, and the frequency-divided clock signals of the fourth bit, the eighth bit, the fourth bit and the eighth bit are the trigger clock signals of the latches in the fourth packet cascade.
Further, for more embodiments of the combination between the number of divided clock signals and the number of latch groups, those skilled in the art can make various equivalent transformations according to the above descriptions, and details are not described herein again. But such equivalent changes do not depart from the content of the present application and are intended to be within the scope of the present application.
Further, in various embodiments, the shift register chain includes 6 or more latches of even number, which are combined two by two into 3 or more flip-flops, which are divided into at least two groups; wherein the first packet includes 1 or more number of triggers and the second packet includes 2 or more number of triggers; wherein two adjacent flip-flops in each packet are cascaded.
Further, as to the grouping manner of the flip-flops and the number of the flip-flops included in each group, which are similar to the above-mentioned embodiment of the latch, only a part of the exemplary description is given below to avoid unnecessary description.
Wherein, in one embodiment, the triggers are divided into 2 groups, wherein each group includes the same number of triggers. For example, an even number of flip-flops or a power of 2 flip-flop.
Further, in yet another embodiment, the triggers are divided into 3 groups, where each group includes a different number of triggers than the other groups. Further, in another embodiment, the flip-flops are divided into 4 groups, wherein each group includes the same number of flip-flops, each being a power of 2 flip-flop.
Further, in various embodiments, the flip-flop comprises at least one of a D flip-flop, an RS flip-flop, a JK flip-flop, and a T flip-flop.
Further, in various embodiments, wherein the flip-flop comprises at least one of a level flip-flop, an edge flip-flop, and a pulse flip-flop. Further, in various embodiments, wherein the flip-flop comprises at least one of a basic RS flip-flop and a clocked flip-flop. Further, in various embodiments, wherein the trigger comprises at least one of a static trigger and a dynamic trigger. Further, in various embodiments, the flip-flop comprises at least one of a bipolar type flip-flop and a MOS type flip-flop.
Further, in various embodiments, the delay between the trigger clock signals respectively input by two adjacent flip-flops in each group is greater than one system master clock period of the system in which the two adjacent flip-flops are located.
Further, in various embodiments, the phase difference between the trigger clock signals respectively input to two adjacent flip-flops in each group is greater than 90 °. The specific situation is similar to the situation of the latch, and in order to avoid unnecessary description, the description is not repeated here.
Further, in various embodiments, the trigger clock signal input by the flip-flop is a frequency-divided clock signal of a system master clock signal; the frequency division clock signal is used as the input trigger clock signal of each grouping trigger by alternately inputting each grouping trigger in turn according to the sequence of phases.
Further, in different embodiments, the same number of divided clock signals may correspond to different numbers of groups, for example, a divided clock signal of 8 may correspond to a group of 2 flip-flops, and may also correspond to a group of 4 flip-flops. The same number of frequency-divided clock signals may also correspond to the case of different numbers of flip-flops in the same group, for example, the frequency-divided clock signal may correspond to the case of 4 flip-flops per group in 2 groups, or may correspond to the case of 8 flip-flops per group, which may be determined according to actual needs, and is not limited. Some examples, but not limitations, will be given below.
Furthermore, for different combinations between the divided clock signals and the flip-flop blocks, which are similar to the above-mentioned embodiments of the latch, only some examples are given below to avoid unnecessary details. For example, in one embodiment, the flip-flops comprise 2 groups, each group comprising 2 cascaded flip-flops having an input trigger clock signal that is a divided by 4 clock signal of a system master clock signal, the divided by 4 clock signals alternating in phase sequence as trigger clock inputs for the first group and the second group of flip-flops; namely, the first bit and the third bit of the frequency-divided clock signal are the trigger clock signals of the first group of cascaded flip-flops, and the second bit and the fourth bit of the frequency-divided clock signal are the trigger clock signals of the second group of cascaded flip-flops.
In yet another embodiment, the flip-flops comprise 3 groups, each group comprising 3 cascaded flip-flops, and the input trigger clock signal of each group is a 9-frequency division clock signal of a system master clock signal, and the 9-frequency division clock signals are sequentially and alternately used as trigger clock inputs of the first group, the second group and the third group flip-flops in a phase sequence; namely, the frequency-divided clock signals of the first bit, the fourth bit and the seventh bit are the trigger clock signals of the first group of cascaded flip-flops, the frequency-divided clock signals of the second bit, the fifth bit and the eighth bit are the trigger clock signals of the second group of cascaded flip-flops, and the frequency-divided clock signals of the third bit, the sixth bit and the ninth bit are the trigger clock signals of the third group of cascaded flip-flops.
In yet another embodiment, the flip-flops include 4 groups, each group includes 8 cascaded flip-flops, and the input trigger clock signal of each group is a 16-bit frequency-division clock signal of a system master clock signal, and the 16 frequency-division clock signals are sequentially and alternately input as trigger clock signals of flip-flops of the first group, the second group, the third group and the fourth group in a phase sequence, that is, the frequency-division clock signals of the first bit, the fifth bit, the ninth bit, the thirteenth bit, the first bit, the fifth bit, the ninth bit and the thirteenth bit are trigger clock signals of the flip-flops of the first group cascade, the frequency-division clock signals of the second bit, the sixth bit, the tenth bit and the fourteenth bit are trigger clock signals of the flip-flops of the third group cascade, the third bit, the seventh bit, the eleventh bit, the fifteenth bit, the seventh bit, the fifteenth bit and the fifteenth bit are trigger clock signals of the flip-flops of the third group cascade, and the frequency-division clock signals of the fourteenth bit, the sixteenth bit, the fourth bit and the sixteenth bit are trigger clock signals of the flip-flops of the third group cascade.
Further, for more embodiments of the combination between the number of divided clock signals and the number of flip-flop groups, those skilled in the art can make various equivalent transformations according to the above descriptions, and details are not described herein again. Such equivalent variations are not to be regarded as a departure from the scope of the present disclosure.
Further, another embodiment to which the present invention relates provides an analog-to-digital converter, which includes a sample-and-hold module, a clock generation circuit and a sub-ADC array, wherein the clock generation circuit provides input trigger clock signals to the sample-and-hold module and the sub-ADC array, and the clock generation circuit includes the multi-phase clock generation circuit to which the present invention relates.
Further, in various embodiments, the shift register chain of the multi-phase clock generation circuit includes the latches divided into at least 2 groups, wherein a first group includes an even number of latches and a second group includes an even number of latches; wherein the phase difference between the trigger clock signals respectively input by two adjacent latches in each group is larger than 90 degrees.
Further, in various embodiments, the shift register chain of the multi-phase clock generation circuit includes two latches combined into flip-flops, the flip-flops are divided into at least 2 groups, wherein the first group includes the flip-flops of power of 2, and the second group includes the flip-flops of power of 2; the phase difference between the trigger clock signals respectively input by two adjacent triggers in each group is larger than the system clock period of a system in which the two adjacent triggers are located.
Further, in a different embodiment, wherein the sample-and-hold module includes 16 sampling channels, the duty ratio of the trigger clock signal CK16<15 > input by the multiphase clock generation circuit to the sample-and-hold module is 1:8; the sub-ADC array comprises 128 sub-ADCs, and the duty ratio of a trigger clock signal CK128<127 > input to the multi-phase clock generation circuit by the sub-ADC array is 1.
Further, in various embodiments, the analog-to-digital converter includes one of a SAR (SAR Successive Approximation Register) ADC, a pipeline ADC, and a multi-path time-interleaved ADC. Further, in various embodiments, the sub-ADCs of the sub-ADC array include SAR (Successive-Approximation Register) ADCs.
Compared with the prior art, the invention has the following beneficial effects: the invention relates to a multi-phase clock generating circuit, which provides a novel grouping shift register technology after the conditions of inevitable propagation delay in a shift register chain and small phase interval of each clock are considered in a compromise mode, latches or triggers are arranged in groups, and therefore, the tolerance margin of propagation delay of the latches or triggers is improved by increasing the phase interval between trigger clock signals input by each group of two adjacent latches or triggers.
Furthermore, compared with the conventional shift register method, the inventive packet shift register technique of the present invention has the advantage that the larger the interval of the phase difference of the input trigger clock signals between the latches or the flip-flops cascaded adjacent to each other in each packet is, the more favorable the output of the previous latch or flip-flop is to be sampled correctly, that is, the more sufficient the setup time for the next latch or flip-flop is, so as to output the correct timing more accurately.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a shift register chain according to the prior art;
FIG. 2 is an idealized timing diagram of the shift register chain shown in FIG. 1;
FIG. 3 is a timing diagram illustrating an error caused by a large propagation delay of the D flip-flop in the shift register chain shown in FIG. 1;
fig. 4 is a schematic diagram of a multi-phase clock generation circuit according to an embodiment of the present invention, including a shift register chain;
FIG. 5 is a schematic diagram of the output timing of the shift register chain shown in FIG. 4;
fig. 6 is a logic structure diagram of a multi-path time-interleaved ADC according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of the multi-phase clock generation circuit in the multi-path time-interleaved ADC shown in FIG. 6, which is used for generating clock signals to the sample-and-hold module;
FIG. 8a is a first part of a schematic circuit diagram of a multi-phase clock generation circuit in the multi-path time-interleaved ADC shown in FIG. 6, which inputs clock signals to a sub-ADC array module;
FIG. 8b is a second part of the schematic circuit diagram of the multi-phase clock generation circuit in the multi-path time-interleaved ADC shown in FIG. 6, which inputs clock signals to the sub-ADC array module;
FIG. 8c is a third part of the schematic circuit diagram of the multi-phase clock generation circuit in the multi-path time-interleaved ADC shown in FIG. 6, which inputs clock signals to the sub-ADC array module;
fig. 8d is a fourth part of the schematic circuit diagram of the multi-phase clock generation circuit in the multi-path time-interleaved ADC shown in fig. 6, which is used for inputting the clock signals to the sub-ADC array module.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. Based on the embodiments of the present invention, those skilled in the art can make several simple modifications and decorations without any creative work, and all other embodiments obtained are within the protection scope of the present invention.
Reference in the present specification to "an example" means that a particular feature, structure, or characteristic described in connection with the example may be included in at least one embodiment of the invention. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is explicitly and implicitly understood by a person skilled in the art that the embodiments described in the present invention can be combined with other embodiments.
Referring to fig. 4, a multi-phase clock generating circuit according to an embodiment of the present invention includes a shift register chain 100. Wherein the shift register chain 100 comprises flip-flops 10 of a first packet 101 and flip-flops 20 of a second packet 102, the flip- flops 10, 20 within each packet being cascade connected.
As shown IN fig. 4, the input clocks CK4_ IP, CK4_ QP, CK4_ IN, and CK4_ QN of the flip-flops are divided by 4 clocks of the system master clock CK _ master of the system IN which they are located, and are delayed by one system master clock cycle from each other by 90 ° and, correspondingly, are shifted by 180 ° from each other by CK4_ IP and CK4_ IN, and CK4_ QP and CK4_ QN. CK16_ IN is a division by 16 of the system master clock, whose duty cycle can be adjusted to 1:4 by suitable combinational logic.
According to the packet shift register technique of the present invention, the shift register chain 100 includes 4 flip-flops divided into 2 groups: first packet 101 and second packet 102, the divided by 4 clock of the corresponding system master clock CK _ master: CK4_ IP, CK4_ QP, CK4_ IN, CK4_ QN, are to provide the input trigger clock signal for the 2 flip-flop groups alternately according to the front and back phase sequence. As shown IN fig. 4, the CK4_ IP and CK4_ IN of the first bit and the third bit are used as the input trigger clock signals of the flip-flops 10 of the first packet 101, and the CK4_ QP and CK4_ QN of the second bit and the fourth bit are used as the input trigger clock signals of the flip-flops 20 of the second packet 102, so that the clock signals with a phase difference of 180 ° between the two trigger clock signals input IN each packet are used as the trigger signals, thereby reducing the influence of the propagation delay of signals between the flip-flops IN each packet, and being beneficial to obtaining the expected clock output IN high frequency applications. The output timing of the 2 group flip-flops is shown in fig. 5.
Furthermore, the multi-phase clock generation circuit can be used as a clock module in an ADC (analog to digital converter), and applied to an ADC to provide corresponding clock signals for other system modules. The analog-to-digital converter referred to herein may be an analog-to-digital converter of various known architectures, including but not limited to a SAR (SAR Successive Approximation Register), a pipelined ADC, a multi-path time-interleaved ADC, and so on.
Referring to fig. 6, another embodiment of the present invention provides a multi-channel time-interleaved ADC, which is a "16 × 8" direct sampling architecture multi-channel time-interleaved ADC, and includes a sample-and-hold module 201, the multi-phase clock generation circuit 202 according to the present invention, and a sub-ADC array 203.
Wherein the sample-and-hold module 201 comprises 16 channels and the sub-ADC array 203 comprises 128 sub-ADCs. In view of the data conversion characteristics of the SAR ADC, the duty ratio of the operating clock may be non-50%, which is very suitable for the ultra-high speed multi-path time interleaving architecture, in the present invention, the sub-ADC employed by the sub-ADC array module is the SAR ADC, but is not limited thereto. The multi-phase clock generation circuit 202 provides the required clock signals for the sample-and-hold module 201 and the sub-ADC array 203, and the clock signals need to satisfy both a definite phase sequence relationship and a certain duty ratio requirement.
Further, the clock signals involved in the multi-path time-interleaved ADC involved in the present invention are divided into different clock domains, wherein the sampling clock and the reset clock required by the 16 sample-hold channels of the sample-hold module 201 belong to a high-frequency clock domain; the clock signals required by the sub-ADC array 203 belong to the low frequency clock domain, and although the clock frequencies involved have been reduced, the phase delay between clocks is essentially still related to the period of the system master clock. The packet shift register technology related to the multiphase clock generation circuit 202 in the present invention ensures that each path of clock signal is correctly output, so as to provide corresponding clock signals for the sample-hold module 201 and the sub-ADC array, respectively, in this embodiment, the duty ratio of the clock signal CK16<15 > of the 16 paths of sample-hold channels is 1:8, and the duty ratio of the clock signal CK128<127 > of the 128 paths of sub-ADC arrays is 1.
Specifically, there are 16 sample-and-hold channels in the 128-channel time-interleaved ADC, the multiphase clock generation circuit 202 first needs to generate 16 clock signals to be used as the sampling clock signal and the reset clock signal of the sample-and-hold module 201, and the schematic diagram of the signal generation circuit is shown in fig. 7. As shown in fig. 7, the shift register chain of the multiphase clock generation circuit 202 includes 2 groups of flip-flops, each group includes 8 cascaded flip-flops, a frequency division 4 system clock signal is used as an input clock signal of each group of flip-flops alternately, and the output of the clock signal is a 16-way clock signal, corresponding to 16 sample-hold channels of the sample-hold module 201. In this embodiment, the duty ratio of CK16<15 > is 1:8.
After the sampling clock is generated, the operating clock for the 128-channel SAR ADC of the sub-ADC array 203 needs to be generated, and the signal generation circuit schematic thereof is shown in fig. 8a, 8b, 8c and 8 d. As shown in fig. 8a to 8d, unlike the conventional shift register chain, the shift register chain according to the present invention divides the flip-flops into 4 groups, that is, divides the trigger clock signal CK16_ m <15 > into 4 groups, where CK16_ m is used to distinguish the sample-and-hold clock signal CK16, and the duty ratios of the two are different from each other.
When CK16_ m <0> is used as a trigger clock, the following CK128< 0> is. Then, the clock signals are beaten by CK16_ m <4> to obtain a CK128< 4. The advantages of this are: compared to directly triggering the output with CK16_ m <1>, CK16_ m <4> and CK16_ m <0> are spaced apart by 4 times the system master clock cycle, effectively mitigating the effect of propagation delay between flip-flops in the shift register chain, CK128< 0.
Further, in this embodiment, the specific grouping of the clock signals generated by the multi-phase clock generation circuit 202 for the sub-ADC array 203 is as follows:
table 1: clock packet condition
Compared with the direct shift register mode of the existing shift register chain, the larger the trigger clock interval of the cascaded flip-flops is, the more beneficial the output of the previous stage flip-flop is to be correctly sampled, namely, the more abundant the setup time reserved for the next stage flip-flop is. The invention relates to a multi-phase clock generating circuit, which adopts a novel grouping shift register technology, and an output clock obtained by grouping shift register generates corresponding grouping along with the operation of a trigger clock, namely, the output clock generates regular intervals, thereby increasing the trigger time interval between cascade triggers in each grouping and ensuring correct time sequence output. In addition, in practical application, the sequence of the modules connected with the output clock can be properly adjusted according to the arrangement of the output clock, so that the overall splicing and combining effect of the multi-path clock is realized.
The invention relates to a multi-phase clock generating circuit applied to a multi-path time-interleaved ADC (analog to digital converter), which adopts a grouping shift register mode, can relieve the influence of propagation delay and establishment time in a shift register chain, defines the phase sequence relation of a multi-path clock and is suitable for a clock scheme of an ultra-high-speed ADC. In addition, the invention is also beneficial to realizing the generation of the ultra-high speed multi-path clock under a larger node process or realizing the output of the higher speed multi-path clock under a forward process.
The present invention has been described above with reference to specific features and embodiments thereof, and it is apparent that various modifications and combinations thereof can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely illustrative of the invention as defined by the appended claims and are intended to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention, and those modifications and variations are within the scope of the claims of the invention and their equivalents.
Claims (9)
1. A multiphase clock generation circuit includes a shift register chain; the method is characterized in that: wherein the shift register chain comprises 3 or more latches divided into at least 2 groups, wherein a first group comprises 1 or more latches and a second group comprises 2 or more latches; wherein two adjacent latches in each group are cascaded;
the trigger clock signal input by each group of latches is the frequency division clock signal of the main clock signal of the system where the trigger clock signal is, and the frequency division clock signal is input to the latches of each group in turn and alternately according to the sequence of phases and is used as the input trigger clock signal of each group of latches.
2. The multi-phase clock generation circuit of claim 1; the method is characterized in that: wherein the first packet comprises an even number of latches and the second packet comprises an even number of latches.
3. The multi-phase clock generation circuit of claim 1; the method is characterized in that: the delay between the trigger clock signals input by the two adjacent latches in each group is at least larger than one system main clock period of the system in which the two latches are positioned.
4. The multi-phase clock generation circuit of claim 1; the method is characterized in that: wherein the shift register chain comprises an even number of latches of 6 or more, the latches being combined two by two into a number of flip-flops of 3 or more, the flip-flops being divided into at least two groups; wherein the first packet includes 1 or more number of flip-flops, and the second packet includes 2 or more number of flip-flops; wherein two adjacent flip-flops in each group are cascaded.
5. The multi-phase clock generation circuit of claim 4; the method is characterized in that: wherein the first packet includes power of 2 flip-flops and the second packet includes power of 2 flip-flops.
6. The multi-phase clock generation circuit of claim 4; the method is characterized in that: wherein the phase difference between the trigger clock signals respectively input by two adjacent triggers in each group is larger than 90 degrees.
7. The multi-phase clock generation circuit of claim 4; the method is characterized in that: wherein the flip-flop includes at least one of a D flip-flop, an RS flip-flop, a JK flip-flop, and a T flip-flop.
8. An analog-to-digital converter comprising a sample-and-hold module, a clock generation circuit and a sub-ADC array, the clock generation circuit providing an input trigger clock signal to the sample-and-hold module and the sub-ADC array, respectively; the method is characterized in that: wherein the clock generation circuit comprises the multi-phase clock generation circuit of claim 1.
9. An analog-to-digital converter according to claim 8; the method is characterized in that: wherein the analog-to-digital converter comprises one of a SAR ADC, a pipelined ADC, and a multi-path time-interleaved ADC.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111364008.2A CN114070316B (en) | 2021-11-17 | 2021-11-17 | Multi-phase clock generation circuit and analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111364008.2A CN114070316B (en) | 2021-11-17 | 2021-11-17 | Multi-phase clock generation circuit and analog-to-digital converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114070316A CN114070316A (en) | 2022-02-18 |
| CN114070316B true CN114070316B (en) | 2023-04-14 |
Family
ID=80277845
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202111364008.2A Active CN114070316B (en) | 2021-11-17 | 2021-11-17 | Multi-phase clock generation circuit and analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114070316B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242939A (en) * | 2013-07-10 | 2014-12-24 | 西安电子科技大学 | Medium-resolution-ratio and high-speed configurable asynchronous successive approximation type analog-digital converter |
| CN105607689A (en) * | 2015-12-22 | 2016-05-25 | 邓晨曦 | High-speed multiphase clock synchronization method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2501513Y2 (en) * | 1989-04-27 | 1996-06-19 | 日本電気株式会社 | Parallel to serial converter |
| US9906235B2 (en) * | 2016-04-12 | 2018-02-27 | Microchip Technology Incorporated | Microcontroller with digital delay line analog-to-digital converters and digital comparators |
| CN109801663A (en) * | 2019-01-11 | 2019-05-24 | 广州华欣电子科技有限公司 | Shift-register circuit, circuit board, infrared touch frame and infrared touch device |
-
2021
- 2021-11-17 CN CN202111364008.2A patent/CN114070316B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104242939A (en) * | 2013-07-10 | 2014-12-24 | 西安电子科技大学 | Medium-resolution-ratio and high-speed configurable asynchronous successive approximation type analog-digital converter |
| CN105607689A (en) * | 2015-12-22 | 2016-05-25 | 邓晨曦 | High-speed multiphase clock synchronization method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114070316A (en) | 2022-02-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP1205030B1 (en) | A parallel analog-to-digital converter | |
| CN107634762B (en) | Data switching between random clock domain to fixed clock domain | |
| CN108155894B (en) | Synchronous hybrid delay type DPWM module based on FPGA | |
| US9584144B1 (en) | Asynchronous clock generation for time-interleaved successive approximation analog to digital converters | |
| JP2001308804A (en) | Interleaving method having redundancy, a/d converter and d/a converter utilizing the same, and track hold circuit | |
| US7012559B1 (en) | Hierarchical parallel pipelined operation of analog and digital circuits | |
| EP1973232A2 (en) | Analog-to digital converter system | |
| EP1973233A2 (en) | Analog-to-digital conversion | |
| JP6808647B2 (en) | A circuit for reading out a sensor having a pixel matrix using analog-to-digital conversion with a high acquisition speed, and an image sensor including such a circuit. | |
| US9973203B1 (en) | High frequency Digital-to-Analog conversion by interleaving without return-to-zero | |
| EP3772182B1 (en) | Voltage controlled oscillator based analog-to-digital converter including a maximum length sequence generator | |
| JP2008166910A (en) | Clock signal generator and analog/digital converter | |
| CN114070316B (en) | Multi-phase clock generation circuit and analog-to-digital converter | |
| US10924129B2 (en) | Time-interleaved analog-to-digital converter device and associated control method | |
| CN106788345B (en) | Ramp signal generator using resistance structure | |
| WO2019204318A1 (en) | High frequency digital-to-analog conversion by time-interleaving without return-to-zero | |
| CN116599531A (en) | Unidirectional slope ADC | |
| CN115933352A (en) | Low-power-consumption time-to-digital converter circuit based on delayed multi-sampling | |
| WO2024077541A1 (en) | Low-jitter random clock generation circuit | |
| CN109889197B (en) | Multi-path coherent frequency synthesis circuit based on linear frequency modulation continuous waveform | |
| CN115425979B (en) | Multichannel time-interleaved analog-to-digital converter | |
| KR102610407B1 (en) | Fast Successive Approximation ADC With series Time-Interleaved Architecture | |
| US20240223203A1 (en) | Circuit and method for channel randomization based on time-interleaved adc | |
| CN117240297A (en) | High-speed digital code serialization method and circuit suitable for time domain interleaving ADC | |
| WO2021136591A1 (en) | Analog-to-digital converter with single counter circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: Room 708-1, Building 1, Northwest District, Suzhou Nanocity, No. 99 Jinjihu Avenue, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Free Trade Pilot Zone, Suzhou City, Jiangsu Province, 215124 Patentee after: Xunxin Microelectronics (Suzhou) Co.,Ltd. Address before: Room 708-1, building 1, northwest Suzhou nano City, 99 Jinjihu Avenue, Suzhou Industrial Park, Suzhou area, China (Jiangsu) pilot Free Trade Zone, Suzhou 215000, Jiangsu Province Patentee before: ACELA MICRO CO.,LTD. |